JPS61208923A - Digital pll circuit - Google Patents

Abstract

PURPOSE:To obtain a stably phase locked signal with high accuracy and to reduce remarkably the scale of a delay circuit by setting a delay time circulating a phase locked loop within a prescribed range using a period of a reference signal. CONSTITUTION:A fixed oscillator 20 is operated in a frequency being an integral number (N) times of a frequency fi of the reference signal Si and sends its output to a delay circuit 21. The circuit 21 generates m-set of signals having a prescribed phase difference to input them to a phase switching circuit 15, a data selector 14 of the circuit 15 selects sequentially one signal in response to the phase of the signal Si among the m-set of signals and inputs the signal to a frequency divider 23 having 1/n frequency division. The frequency divider 23 inputs the signal So subject to 1/n into a phase comparator 11. The comparator 11 inputs a phase difference signal between the signals Si and So to a control pulse generating circuit 12, which inputs the output pulse to an up/down counter 13 of the circuit 15 to form a phase locked loop. The delay time (t) circulating through the phase locked loop is set to be in the relation expressed in equation I by using a period T of the signal Si. Thus, a stable phase locked signal with high accuracy is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital PLL circuit that obtains an output signal phase-locked to an input signal.

BACKGROUND ART In a conventional digital PLL circuit, for example, as shown in FIG. 4, a fixed oscillator 1 operating at a frequency f0 approximately equal to the frequency fi of a reference signal is used, and its output is divided into m' taps (the number of phase divisions). In addition to the delay circuit 2 with up/do
A phase switching circuit 16 composed of a wn counter 13 and a data selector 14 switches the tap position of the delay circuit 2 to control the phase of the output signal.

The phase comparator 11 compares the phase difference between the reference signal Sl and the signal S0 selected by the data selector 14, and determines the phase lead depending on whether the phase difference is larger or smaller than Δ/2 (Δ=2π/2 m'). A signal h1, a phase delayed signal h-1, and a normal phase signal h0 are output. Reference numeral 12 denotes a control pulse generating circuit which monitors the signal from the phase comparator 11 and generates a phase control pulse when the signal h1 or h-1 is detected l times in succession. The phase switching circuit 16 performs a phase switching operation of the output signal using a phase control pulse.

By controlling as described above, it is possible to extract an output signal phase-synchronized with the input signal with an accuracy of maximum phase difference Δ/2 (for example, Japanese Patent Publication No. 11008/1982).

In order to reduce the problem that the invention seeks to solve (Δ/2=2x/2m') and increase the accuracy of phase synchronization, the number of delay circuits must be increased, and as a result, the total cost of the digital PLL circuit is There was a problem with the scale.

The present invention has been made in view of the above points, and an object of the present invention is to provide a digital PLL circuit which can significantly reduce the scale of the delay circuit and still extract a stable and highly accurate synchronization signal.

Means for Solving the Problems In order to solve the above problems, the present invention uses a fixed oscillator that operates at an integer multiple of the reference signal independently of the reference signal, and its output is divided into m signals with an appropriate phase difference. In addition to a delay circuit that generates a signal, switching is performed to sequentially select one signal according to the phase of the reference signal from among the m signals,
After the frequency is further divided by n, a synchronized loop is formed to compare the phase with the reference signal. Then, the synchronization loop is configured to have a slow (...) relationship.

Effect The present invention has the above-described configuration, so that the delay time t for completing the synchronous loop is 1 T 1 T (k+-)-(t((k+1--)-m nm
By setting n, the number of elements in the delay circuit can be significantly reduced, and the circuit scale of the entire digital PLL can be reduced.

Embodiment FIG. 1 shows an embodiment of the digital PLL circuit of the present invention. Note that circuits that are the same as those in the prior art are given the same numbers as those used in FIG. 4, and their operations will be omitted here.

In FIG. 1, 2o is a fixed oscillator operating at a frequency N times the integer of the reference signal Si, 21 is a delay circuit that generates m signals with a phase difference Δ, and 16 is an up/down counter 13.
and a data selector 14, a phase switching circuit 23
is a frequency divider that divides the frequency of the signal selected by the data selector 13 by n and outputs the result.

Next, the frequency of the fixed oscillator is four times that of the reference signal (N = 4)
Now, the operation of the circuit shown in FIG. 1 will be explained in the case where the division ratio of the frequency divider is 4 (n=4).

Now, the allowable phase shift in a certain transmission system is 11.
Assuming that it is 3 degrees, in the conventional circuit shown in Fig. 4,
Since the number of phase divisions that determines the phase accuracy is the same as the number of delay circuits, the delayed signals are divided into signals A0 to A1. as shown in FIG. 2A. Up to 16 pieces are required.

Δ 360, that is, 2=2
By creating only four signals from a to a3 shown in the figure, and sequentially dividing the frequency of one of these signals by four as shown in the signal shown in B in the same figure, the phase difference with respect to the phase of the fundamental wave can be obtained. It is possible to create a signal close to the fundamental frequency below a predetermined value. That is, if this is expressed as an equation, Δ 360 2 =2X4X4 ="°3. Therefore, in the above case, the number of delay circuits can be increased to K by adding one frequency divider 23.

By the way, at time 1=0, the signal a shown in FIG. 2B is selected by the data selector 13, and the signal a shown in FIG. Suppose you are in a situation where

However, since the frequency f of the reference signal Sl and the frequency of the signal S in Figure B are not strictly equal, a phase shift will occur over time. Therefore, in order to maintain synchronization, the phase of the output signal must be switched by selecting signal a0 or signal a2 shown in FIG. If this phase switching is performed, for example, within the time period t = -'r to -T, then the signal a2, which is in a delayed phase with respect to the signal a1, can be selected at the time l = -'r. Signal a is in leading phase. cannot be selected until time t=πT. As a result, when the phase of the PLL output signal is advanced, the frequency range in which phase synchronization can be achieved is half of the theoretical one.

On the other hand, if the next phase switching operation is performed within the time period t=-T to -LT, the phase is advanced.

In-phase and delayed-phase signals can be selected at times j = 7T, πT, , , T immediately after the phase switching, and their 4-frequency divided outputs are shown in the solid line and 1 As shown by the dotted chain line, phase synchronization can be achieved in a wide allowable frequency range for any phase difference. That is, at a certain time (1=0), the signal a1
is selected, in order to achieve phase synchronization between the input reference signal to the PLL and the output signal, the phase must be switched between the falling edge of signal d0, which is the leading phase of signal a1, and the next rising edge. Completing the operation is a condition for obtaining a stable output signal. Since the timing of switching this phase is determined by the delay time t that passes through the synchronization loop, the condition for maintaining stable synchronization is when the delay time t satisfies the following equation.

(k+4-)k<t<(k+1-!-)km n
m n where t is the period of the reference signal, m is the phase division number n is the frequency division ratio of the frequency divider, and k is 0 or a natural number.

If the delay time for completing the synchronized loop does not satisfy the condition shown in the above formula, the condition can be satisfied by inserting a delay element 30 in the middle of the synchronized loop, for example, as shown in FIG. Bye.

Effects of the Invention As described above, according to the present invention, it is possible to obtain a stable and highly accurate synchronization signal with a small number of circuit elements, so it is extremely effective in reducing the circuit scale and economically.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a digital PLL circuit in one embodiment of the present invention, FIGS. 2A and B are time charts explaining the present invention in detail, and FIG. 3 is a block diagram showing another embodiment of the present invention. Figures and fla diagrams are conventional digital P
FIG. 2 is a block diagram showing an example of an LL circuit. 11... Phase comparator, 12... Control pulse generation circuit, 13...--up/down counter, 14... Data selector, 20...
...Fixed oscillator, 21...Delay circuit, 22
...Frequency divider, 30...Delay element. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 20 To I Ward Figure 3 Figure 4

Claims (1)

[Scope of Claims] An oscillator that operates independently of a reference signal that serves as a reference for synchronization at a frequency that is an integral multiple of the reference signal, and a circuit that has several delay functions for the output of the oscillator, a delay circuit that generates m signals with a predetermined phase difference;
a phase switching circuit that performs switching to sequentially select one signal according to the phase of the reference signal from among the signals;
A synchronous loop is formed by a frequency divider that divides the frequency of the signal selected by the switching operation by n, and a phase comparator that compares the phase of the output signal of the frequency divider and the reference signal. Using the period T of the reference signal, the delay time t to
A digital PLL circuit characterized by having the following relationship: n (k=0, 1, 2, . . .).