JPS63107318A - Variable frequency divider - Google Patents

Abstract

PURPOSE:To attain a fine step of change in the frequency division ratio and to increase the upper limit frequency to be extracted by inputting an input pulse signal to a multiplexer while being converted into a polyphase signal and giving the said signal to a programmable counter while its interval of the phases is varied in extracting the signal from the multiplexer. CONSTITUTION:A pulse signal to be frequency-divided is converted into a polyphase signal by a polyphase signal forming circuit 20, one of the results is selected by a multiplexer 30 and given to a programmable counter 40, where the number of leading or trailing edges is counted, and every time its count reaches a setting value (M-1) set by a 1st setting device 50, a frequency division signal is outputted to a terminal 41. The counter 40 loads the setting value (M-1) again by using the frequency division signal, enters the next counting and outputs the frequency division signal. Moreover, the frequency division signal is outputted at an output terminal 60 and given to a latch control circuit having a differentiation function, where the signal becomes a single pulse Pi, which is given to a latch circuit 80. The latch circuit 80 latches the sum of a numeral N set by a 2nd setting device 100 and a value of a latch output signal of the latch circuit 80 by an adder 90 every time the counter 40 outputs a frequency division signal to control the multiplexer 30 switchingly.

Description

[Detailed Description of the Invention] "Field of Industrial Application" This invention relates to a variable splitter that can be used in various timing generators, etc., and in particular, it is capable of finely changing the splitting ratio, and The present invention aims to provide a variable frequency divider that can increase the upper limit frequency that can be extracted.

"Prior Art" For example, there is a demand for generating various timing signals by changing the repetition frequency of clock pulses.

To meet such requirements, a variable frequency divider as shown in FIG. 4 or FIG. 5 has conventionally been used.

The variable frequency divider shown in FIG. 4 is also called a prescaler type and is constructed by cascading a 1/N fixed frequency divider 1 and a 1/M variable frequency divider 2.

According to this circuit structure, the frequency division ratio is 1×1, which is M The rectangular wave number f is f=f...''-Total.

0 0 1 N-M On the other hand, the variable frequency divider shown in Fig. 5 is called a swallow type.
A variable frequency divider 3 whose input signal can be divided by N N+1 by switching upwards and upwards, and a first frequency divider which is given the division ratio power of this variable divider 3 and divides the divided output into M frequencies. 4 and
Similarly, the frequency divider 5 is provided with the frequency divided output of the variable frequency divider 3, and is configured with a second frequency divider 5 which further divides the frequency of the frequency divided output.

The divided outputs of the first frequency divider 4 and the second frequency divider 5 are given to the controller 6, and the output of the controller 6 changes the division ratio of the variable frequency divider 3 into the - state and the "-" state. Switching N N
+1 Well, the structure is such that the output signal is taken out from the output terminal of the second frequency divider 5.

According to this one-way system, the frequency division ratio of the variable frequency divider 3 is divided into 1 and 2 at a period determined by the frequency division ratio - of the first frequency divider 4 within the time interval in which the frequency-divided output signal is taken out.
N N+1 switching control is used to make it possible to minutely change the division ratio. Input frequency f and output frequency f according to this method. The ratio, that is, the division ratio is -1-.

N-X+M "Problems to be Solved by the Invention" According to the grise scaler system shown in FIG. 4, the frequency is changed at the step of frequency division. In other words, the division ratio changes with increasing steps, and there is a drawback that only discrete frequency division ratios can be obtained.

On the other hand, according to the Swaro one-way system, the division ratio is N-X+4, and by setting the value of N large, set X and M to arbitrary integers, for example, X = 10.20.30...2M = 1.2 .3...
- By selecting 9, the upstream frequency division ratio can be changed minutely.

However, since M must be selected with respect to X in the relationship of X)M, the value of X cannot be set to a small value. For this reason, there is a drawback that the minimum division ratio cannot be made small. In other words, when the input frequency f is determined,
There is a drawback that a signal with a frequency close to the input frequency cannot be extracted, and the upper limit frequency is suppressed low.

SUMMARY OF THE INVENTION An object of the present invention is to provide a variable splitter that can change the division ratio in fine steps and can also increase the maximum frequency that can be extracted.

``Means for Solving the Problems'' In this invention, a multiphase signal is synchronized with the pulse signal to be divided by A9 and outputs a multiphase signal whose phase is shifted by the pulse interval of the pulse signal. B. A multiplexer that selects and extracts one of the multiphase signals output from this multiphase circuit; C. Counts the number of leading or trailing edges of the signal selected by this multiplexer. , a programmable counter that outputs a frequency division signal when its count value reaches a predetermined value, and also loads a program with a set value using the frequency division signal;
a setting device; E6 a latch means for applying a switching control signal to the multiplexer; F. a second setting device for setting the fine frequency division ratio; G. this second setting device;
an adder that adds the setting value set in the setting device and the digital value of the switching control signal of the latch means; A latch control circuit that latches the added value of the divider and a latch control circuit that latches the added value of the divider.

"Operation" According to the configuration of the present invention, a pulse signal to be frequency-divided is converted into a multiphase signal by a multiphase circuit, one of the multiphase signals is selected and applied to a programmable counter, and the selected one is applied to a programmable counter. The number of leading edges or trailing edges of one multiphase signal is counted, and a branch signal is output every time the counted value reaches a predetermined value set in the first setting device.

Using this frequency-divided signal, the programmable counter loads the set value M-1 set in the first setter again into the program, enters the next counting operation, and outputs the branch signal, and repeats this process.

Therefore, by changing the set value M-1 of the first setter, the frequency division ratio can be changed by M.

On the other hand, the multiphase signal selected by the multiplexer is switched every time a branch signal is output from the programmable counter, and the phase of the signal given to the programmable counter is changed, for example, by
By sequentially shifting the frequency division signal in the direction of delay by the pitch of the pulse time interval T, the period of the divided signal output from the programmable counter can be made longer than the normal period by the pitch of the pulse time interval T of the input pulse. . As a result, the frequency of the branch signal output from the programmable counter can be slightly lowered.

By selecting the phase interval of the multiphase signal taken out from the multiplexer to be a two-phase interval, the period of the frequency-divided signal output from the programmable counter is 2 times the time interval T between the input signal and the signal.
It becomes twice as long, that is, 2T.

By selecting a three-phase interval as the phase interval of the multiphase signal taken out from the multiplexer, the cycle of the frequency-divided signal output from the programmable counter is lengthened by 3T.

In this way, by changing the phase interval of the multiphase signal F taken out from the multiplexer, the period of the frequency-divided signal output from the programmable counter can be changed by the time corresponding to the interval T between the input signal and the frequency division signal. The ratio can be changed minutely.

If the phase interval of the multiphase signal taken out from the multiplexer is N, the frequency division ratio of the programmable counter is IA, and the frequency division ratio of the multiphase circuit is 1/P, the overall frequency division ratio is P1M+
It becomes N. M can be set by the first setter, and its value can be set to a positive integer. Therefore, M
=1. By setting N=O, the division ratio can be minimized, and an upper limit frequency that is 1/P lower than the input frequency can be obtained.

"Embodiment" FIG. 1 shows an embodiment of the present invention. An input pulse Pa (FIG. 2A in IE 2) inputted from the input terminal 10 is inputted to the multiphase circuit 20. As shown in FIGS. 2B-E, the multiphase circuit 10 generates multiphase signals Qa, IQb, Qc, Q whose phases are shifted by the pulse interval T of the input canoculus Pa, for example.
Output d. In this example, a configuration is shown in which a four-phase polyphase signal is output, but the number of phases can be arbitrarily selected. A specific example of the multiphase circuit 10 is a shift register.

The multiphase signals Qa to Qd outputted from the multiphase circuit 20 are applied to a multiplexer 30, and the multiplexer 30 selects and takes out one of the signals.

An example thereof is shown in FIG. 2F. The figure shows a state in which the multiphase signal Qa is selected up to time T1, and the state is switched to the state in which the multiphase signal Qb is selected at time T1.

The signal taken out by the multiplexer 30 is input to a programmable counter to count the number of leading or trailing edges. The waveform diagram of each part shown in FIG. 2 shows the case where the leading edge is counted. The output terminal 41 of the programmable counter 40 is connected to the load terminal 42, and the first setter 50 is connected to the set value input terminal group 43. The first setter 50 has a set value M that determines the frequency division ratio 1/M of the programmable counter 40.
-1 is set.

The branch signal output to the output terminal 41 of the programmable counter 40 is output to the final output terminal 60. Further, the frequency-divided signal outputted to the final output terminal 60 is given to a latch control circuit 70 having a differentiation function.

When the programmable counter 40 outputs the division signal, the latch control circuit 70 differentiates and rectifies the frequency division signal and outputs, for example, a positive polarity single signal Pi as shown in FIG. 2I. This single signal Pi is applied to a latch circuit 80, and the latch circuit 80 latches the addition output of the adder 90.

A second setter 100 is connected to one input terminal 91 of the adder 90.
is connected to the other input terminal 92, and a latch circuit 80 is connected to the other input terminal 92.
gives a latch output signal. Therefore, the latch circuit 80 latches the sum of the value set in the second setter 00 and the latch output signal of the latch circuit 80 every time the programmable counter 40 outputs the frequency-divided signal.

The latch output signal of the latch circuit 80 is sent to the multiplexer 30.
and controls switching of the multiplexer 30 according to the value of the latch output signal. In other words, this example shows the case where the latch output signal uses a 2-bit digital signal, and when the 2-bit digital signals are IQ and OJ, the multiplexer 30 is in a state where it selects and outputs the multiphase signal Qa, and the signal becomes "0". When ゜1'', the multiphase signal Qb is selected and output, when rl, OJ, the multiphase signal Qc is selected and output, and when rl, 1'', the multiphase signal Qd is selected and output. It will be in the state to output.

Here, if N=O is set in the second setter 100, the added value of the adder 90 is O, so the latch circuit 80 has ro
, OJ are latched. Therefore, in this case, even if the programmable counter 40 outputs a frequency-divided signal, the latch circuit 8
By simply latching IQ and OJ to 0, the multiplexer 30 is maintained in a state in which the multiphase signal Qa is selected.

Therefore, the frequency division ratio in this case is P=4. Since N=O -
It becomes

M The second setter 100 has N=1, that is, rO as a digital signal.
, IJ are set, the initial state of the latch output of the latch circuit 80 is ro, OJ, and thereafter, each time a branch signal is output from the programmable counter 40, the latch output of the latch circuit 80 becomes rO, IJ.
rl, 0jr1.1jrO, 0JrOtlj...
...and this is repeated. Therefore, in this case, the multiplexer 30 sequentially converts the multiphase signal Qa = Qd into 1
Select and output by phase spacing.

Each time the multiplexer 30 outputs the frequency-divided signal from the programmable counter 40, it sequentially selects the multiphase signals Qa to Qd and supplies them to the programmable counter 40, so that the timing at which the frequency-divided signal is output is the same as when N=O. When looking at the phase of the frequency-divided signal as a reference, the output timing of the branch signal in the case of N=1 is delayed by -Grus of the input signal Pa with respect to the reference phase.

In other words, when the multiplexer 30 selects the multiphase signal Qa as shown in FIG. 2G, the count value of the programmable counter 40 reaches a predetermined value, and the divided signal Ph (FIG. 2H) is output to the output terminal 41. When output, the latch circuit 80 latches the added value of the adder 90. As a result, latch circuit 8
The latch output of 0 becomes "1", that is, ro, IJ, and the multiplexer 30 is switched to a state in which the multiphase signal Qb is selected.

As a result, if the state in which the multiphase signal Qa is selected continues, the division signal Ph is returned to H logic at the timing shown by the dotted line in FIG. The rise of the signal is delayed by a time T corresponding to 1.times.of the input signal Pa. In other words, the rise of the frequency-divided signal is defined by the rise timing of the multiphase signal Qb.

Therefore, the timing of the fall of the branch signal output from the programmable counter 40 is delayed by the time T.

The falling timing of the frequency divided signal is 1 of the input Noculus Pa.
When the signal falls with a delay of 7 pulses of time T, the multiplexer 30 is switched to select the multiphase signal Qc. By this switching, the rising timing of the frequency-divided signal becomes the rising timing of the multiphase signal Qc. In this way, the multiplexer 30 sequentially switches the multiphase signal Qa = Qd at one-phase intervals, so that the υ programmable counter 4
The timing at which 0 outputs the frequency-divided signal is the input pulse Pa.
is sequentially delayed by a time period T corresponding to lnorth of
Garu.

When the second setter 100 is set to the numerical value "2", the numerical values latched by the latch circuit 80 are "0", "2" rOJ, r
2J...... As a result, multiplexer 30
selects Qa and Qc in the multiphase signal alternately, and selects and extracts the multiphase signal at two-phase intervals.

Therefore, in this case, the cycle of the frequency-divided signal output from the programmable counter 40 becomes longer by the time interval 2T corresponding to the two input pulses Pa, and the division ratio becomes 1/1.

4M+2 When the value "3" is set in the second setter 100, the latch output of the latch circuit 80 is roj r3J r2 jrl
jrOJr3J...... In other words, the digital code is ro, OJ, [, Brx, o''ro, 1''ro
, o'11, IJ... Therefore, multiphase signals are selected and extracted at three-phase intervals like Qa - Qd - Qc - Qb - Qa . . . .

Therefore, in this case, the period of the branch signal outputted from the programmable counter 40 is lengthened by the time interval 3T corresponding to three input signals Pa, and the frequency division ratio becomes "-4M+3".

In this way, by changing the numerical value N set in the second setting device 100, the frequency division ratio can be changed minutely, and by changing the setting value M-1 of the first setting device 50, the frequency division ratio can be changed finely. It can be changed significantly.

"Effects of the Invention" As explained above, according to the present invention, the division ratio can be adjusted by appropriately selecting the set value M-1 set in the first setter 50 and the numerical value N set in the second setter 100. It can be set to any value, and the division ratio can still be changed minutely. Furthermore, since M can be set to 1, the minimum frequency division ratio can be made smaller than in the case of the conventional one-soflo type. Therefore, the maximum frequency that can be extracted from a single frequency input pulse Pa can be increased,
Signals of various frequencies can be extracted from high frequencies to low frequencies.

Again, human power/? Since the pulse Pa is divided in advance by 1/P in the multiphase circuit 20 and given to the programmable counter 40, the frequency of the manual pulse Pa must be selected to be P times the number of station waves that the programmable counter 40 can respond to. Can be done. Therefore, a signal having a frequency P times higher than the frequency to which the zorogram pull counter 40 can respond can be divided.

In other words, since the multiphase circuit 20 can be constructed from a circuit such as a shift register, there are actually high-speed response elements that operate in the GHz % range. On the other hand, the frequency at which the programmable counter can respond is lower than the frequency at which the shift register can respond. Therefore, by providing the pre-stage trap multiphase circuit 20 of the programmable counter, it is possible to obtain the advantage of being able to divide the frequency of a signal having a higher frequency than the number of station waves to which the zorogram pull counter can respond.

In this embodiment, if the setting value N set in the second setting device 100 is selected to be a value other than 0, jitter may occur in the frequency-divided signal, but in such a case, as shown in FIG. For example, D
The jitter generated in the variable frequency divider 200 can be removed by using a timing circuit 300f, which may be configured with a type flip-flop, and by extracting a frequency-divided signal in synchronization with the human pulse Pa in the retiming circuit 300.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining one embodiment of this invention, FIG. 2 is a waveform diagram for explaining the operation of this embodiment, and FIG. 3 is a diagram for explaining another embodiment of this invention. FIG. 4 and FIG. 5 are block diagrams for explaining a conventional variable splitter. 10... Output terminal, 20... Multiphase circuit, 30...
- Multiplexer, 40... Programmable counter, 50... First setting device, 60... Output terminal, 70...
...Latch control circuit, 80...Latch circuit, 90...
-Adder, 100...second setter. Fang 2 Figure i J Wordsman Kutsubun value I M-+ l M-
2 (blank 1 1 0 1M-1o 3 ma

Claims (1)

[Claims] (1) A, a multiphase circuit that outputs a multiphase signal whose phase is shifted by the pulse interval of the pulse signal in synchronization with the pulse signal to be frequency-divided; and B, a multiphase signal that is output from this multiphase circuit. A multiplexer that selects and extracts one of the multiphase signals; C. Counts the number of leading edges or trailing edges of the signal selected by this multiplexer, and when the counted value reaches a predetermined value, a programmable counter that outputs a frequency-divided signal and loads a set value into a program using the outputted frequency-divided signal;
a setting device; E. a latch means for supplying a switching control signal to the multiplexer; F. a second setting device for setting the fine frequency division ratio; an adder that adds the digital value of the switching control signal; and H, a latch that applies a latch signal to the latch means and causes the latch means to latch the added value of the adder each time the count value of the programmable counter reaches a predetermined value. A variable frequency divider consisting of a control circuit and.