JPH01318179A - Multiplier - Google Patents

Abstract

PURPOSE:To reduce an error included in an output and to obtain a highly accurate multiplier by providing the multiplier with a correcting function for correcting an error generated in a conversion means due to the alternate inputs of an input signal obtained through a switching means and its inverted signal. CONSTITUTION:A switch 22 is turned on and off by the output of a timing circuit 25 and a switch 23 is turned on and off by the output of the circuit 25 inverted by an inverter gate 24. The circuit 25 continuously oscillates pulses at the duty ratio of 1 to 1 in a frequency band sufficiently slower than the oscillation frequency of pulse width converters 3, 4 and an oscillator 5 to switch the switches 22, 23 at the time ratio of 1 to 1 under input voltages Va, the inverse of Va. Consequently, an error included in a pulse width changing signal generated in a conversion means can be remarkably offset between the input signal and its inverted signal and sharply reduced. Thereby, highly accurate multiplication reducing the influence of an error due to the conversion means can be attained.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a multiplier that obtains a digital output signal proportional to the product of input signal levels, and is particularly configured to be suitable for integration. Moreover, the present invention relates to a multiplier having an error correction function.

(Prior Art) As a multiplier that obtains a digital signal output proportional to the product of each input signal, and which is configured to be suitable for integration, the "Multiplication The application has been filed for ``Vessel''.

FIG. 3 is a circuit diagram showing one embodiment of this "multiplier". In this embodiment, in order to compare with the explanation of one embodiment of the present invention described later, the arrangement of gates is slightly changed from that described in the above "Multiplier" for convenience, but essentially the two are the same. Based on the same technical philosophy. That is, this multiplier is
It is composed of a pulse width modulator 3.4, an oscillator 5, a frequency divider 11, an inverter gate 6.7, an AND gate 8, 9, 12, and an OR gate 10, each receiving an input signal from a corresponding input terminal 1.2. There is. Note that 13 and 14 are output terminals.

In this circuit, the pulse width modulator 3.4 is shown in FIG.
As shown in a) and (b), one period is 2t, 2tb, and the pulse width T, , Tb is set as shown in the following equation according to the input voltage V, , Vb from the input terminal 1.2. Modulate the signal.

T,=t,+τ.

Tb''tb+τb Here, τ1 and Tb are values proportional to the input voltages V, , Vb.Furthermore, in the pulse width modulator 3 and pulse width modulator 4, the period 2t of the output pulse signals a, b, , 2t
b are set not to synchronize for a certain period of time so that the phases are mutually random. Pulse width modulator 3.4
The output of is applied to AND gate 9.8 via inverter gate 6.7. (C) and (d) of FIG. 4 are output waveform diagrams of this inverter gate 6.7. And-
The output of the inverter gate 7.6 and the output signal of the pulse width modulator 3.4 are input to the gate 8.9, and their AND is calculated. (e) and (f) of FIG. 4 show the output waveforms of each Antogame 1 and 8.9.

Next, in the OR gate 10, the logical sum of the outputs of the AND gates 8.9 is calculated as shown in FIG. 4 (g>).

On the other hand, as shown in FIG. 4 (h), the oscillator 5 outputs a regular pulse train signal at a frequency sufficiently higher than the frequency of each output pulse signal of the pulse width modulator 3.4. The pulse train signal generated by the pulse train is applied to the AND gate 12 and the frequency divider 11. Frequency divider 11 is oscillator 5
A pulse train signal j whose frequency is divided by 1/2 is given to the output terminal 14.

The AND gate 12 calculates the AND of the output g of the OR gate 10 and the pulse train signal 11 from the oscillator 5. This output i shown at N) in FIG. 4 is applied to the output terminal 13.

Next, the operation of the multiplier will be explained with reference to the waveform diagram of FIG.

Each input signal is applied to the corresponding input terminal 1.2, and the pulse width modulator 3.4 outputs the signals as shown in (a>, (b) in FIG. 4) according to the respective input voltages v, , Vb. is modulated into output pulse signals a and b.During a fixed period of time that is sufficiently longer than one period of these output pulse signals a and b,
Assume that the pulse train signal outputs F pulse signals as shown in FIG. 4(h). At this time, the logical product output of the AND gate 12 is as shown in FIG. 4(i), and the output pulse number pI is as shown in the following equation.

pt = ((a-d)+(b-c)lxF=-(2
t, Lb~2τ, τ,) 4t, tb On the other hand, since the pulse number p of the pulse train signal j given from the frequency divider 11 to the output terminal 14 is F/2, it is output to the output terminal 13.14. By counting the number of pulses of the pulse signal with a counter or microcomputer (not shown), and subtracting the number of pulses of the pulse train signal j from the number of pulses of the AND output i, the number of pulses as shown below is obtained.

Since this is an example value, by subtracting the number of pulses of the pulse signal given to the output terminal 13 from the number of pulses of the pulse signal given to the output terminal 14, the product of the respective input voltages (
v, xVb) can be obtained.

(Problems to be Solved by the Invention) In the multiplier configured as described above, in an ideal state, it is possible to obtain a digital signal proportional to the product of the respective input voltages. However, such circuits generally have the disadvantage that errors tend to occur in the output waveform in pulse width modulators and the like, and therefore the sampling frequency cannot be increased. Additionally, changes over time may cause errors in pulse width modulation.

This invention has been made to address the following drawbacks of conventional devices, and aims to reduce errors included in the output by adding an error correction circuit, thereby obtaining a multiplier with higher precision. With the goal.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention converts each input signal into asynchronous pulse signals whose pulse widths vary depending on the level of the input signals. means for converting; oscillation means for outputting a pulse signal with a frequency higher than the frequency of the pulse signal output from the converting means; and an inverted signal of at least one input signal with a duty of 1; 1, switching means alternately switched by a pulse signal having a frequency sufficiently slower than the pressure of the oscillating means and inputted to the converting means of the pulse signal; and an output from the converting means including an output based on an inverted signal of the input signal. A predetermined logical operation is performed in response to a pulse signal outputted from the oscillation means, a pulse signal outputted from the oscillation means, and a switching signal of the switching F stage, and according to the pulse width of the pulse signal outputted from the conversion means. logical operation means for calculating the number of pulses output from the oscillation means in a predetermined time to obtain a digital signal proportional to the product of the input signal levels; 9 (Function) In the above configuration, the converting means receives an input signal and an inverted signal of this input signal]21. Since the input signals are switched at a time ratio, the logic of digitally processing the input signals by multiplying them is necessary.
In the llj arithmetic circuit, a considerable portion of the error contained in the pulse width displacement signal generated by the conversion means is canceled out between the input signal and its inverted signal, and is significantly reduced. Therefore, the influence of errors in the conversion means is small,
It is possible to perform multiplication with high precision.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a multiplier according to an embodiment of the present invention,
FIG. 2 is an operational waveform diagram of the multiplier shown in FIG. 1. In the embodiment of the present invention shown in FIG. 1, the same reference numerals as in the circuit diagram shown in FIG. 3 indicate the same constituent members and their operations are also the same, so a detailed explanation of the IM will be omitted.

In FIG. 1, 21 is the voltage 1 [V
, a voltage with opposite polarity and equal absolute value −■
, 22.23 is the input terminal for applying]
and the pulse width modulator 3, and a switch inserted between the input terminal 21 and the pulse width modulator 3. As shown in the figure, the switch 22 is on/off controlled by the output of the timing circuit 25, and the switch 23 is the inverter gate. 24
The on/off control is performed by the output of the timing circuit 25 which is inverted by . The timing circuit 25 continuously oscillates pulses with a duty of 1:l at a frequency sufficiently slower than the oscillation frequencies of the pulse width modulators 3, 4 and the oscillator 5, thereby adjusting the input voltages V, , -V,
The switches 22 and 23 are switched so that the pulse width modulator 3 is applied to the pulse width modulator 3 in a time ratio of 1:1-. 26 is an exclusive NOR gate 1- (EX-NOR gate) which receives the exclusive OR of the output signal of the OR gate 10 and the output of the timing circuit 25. The output of the EX-NOR gate 26 becomes one input of the AND gate 12, where it is ANDed with the output of the oscillator 5.

One embodiment of the present invention is constructed as described above, and its operation will next be described with reference to FIG. 2.

In an ideal state, the pulse width modulator 3 in FIG. 1 performs pulse width modulation in accordance with the input voltage .

Outputs a pulse that is . Note that τ has a magnitude proportional to the input voltage V. However, in the actual circuit,
Errors occur in the output pulse width due to the offset, slew rate, etc. of the operational amplifier used in the pulse width modulator. Letting A be the error generated in the pulse width modulator 3, it can be expressed as r,=t,+τ,+A (see FIG. 2(a)). One terminal 2
When voltage -■, is input from 1 to pulse width modulator 3 through switch 23, T, +- becomes T, -=t, -τ, +
Indicated by A (Fig. 2 (al).

Similarly, the output pulse width Tb of the pulse width modulator 4 including the error B is expressed as Tb''tb+τゎ+B (Fig. 2(b)). Note that τ is the input voltage ■
, has a size proportional to .

Now, in FIG. 1, when the timing circuit 25 is at a high level and the switch 22 is on, that is, when the voltage ■ is input to the pulse width modulator 3 from the terminal 1, the output pulse of the AND gate 8 is turned on. The time ratio P, is expressed as: Further, the on-time ratio P of the output pulse in the AND gate 9 is expressed as follows. Therefore, the on-time ratio Pt of the output in the OR gate 10 is Pr=P-+Pb=ta tb-τ1τb-τ, B-Aτゎ-A-[3ta
tb...(1). Since the timing circuit 25 is now sending out a high level signal, the output pulse at the EX-NOR gate 26 is the same as the output pulse from the OR gate 10.

Next, consider a case where the timing circuit 825 is sending out a low level signal. At this time, since the switch 23 is on, the voltage -■ is inputted to the pulse width modulator 3 from the terminal 21, and therefore the on-time ratio P, - in the output pulse of the AND gate 8 is expressed as -. Similarly, the on-time ratio P, - in the output pulse of the AND gate 9 is also expressed as follows. Therefore, the on-time ratio P (-) of the output pulse in the OR gate 10 is as follows: Pt-=P, -+Pb-=t-tb+τ, τb+τ, B-τbAA-B. Since the output of timing #125 is at low level, ,
The EX-NOR gate 26 becomes an inverter, and its output pulse becomes Pb-1, that is, Pi −=I Pt −= 2゛°” (2) −.

Assuming that the timing circuit 25 repeatedly sends out low-high signals with a duty ratio of 1:1 at a constant cycle, EX
- The on-time ratio Pt of the output of Noah game l~26 is (1)
, From equation (2), it becomes.

When this equation (3) is compared with the above equation (1), the term including errors A and B becomes only (-τ, B)/2t, tb in equation (3), and in the output of the EX-NOR gate 26, It can be seen that the error contained in the output of the pulse width modulator 3.4 is considerably canceled out and reduced.

Assuming that the oscillator 5 outputs F pulses within a unit time, the number of output pulses Pr per unit time in the AND gate 12 is expressed as ×F. Further, since the output of the 1/2 frequency divider 11 is F/2, subtracting the number of output pulses of the AND gate 12, that is, the number of output pulses at the terminal 13 from the number of output pulses at the terminal 14, yields. B is the error, τ1
, τb, the error term in equation (4) is quite small. Therefore, by taking the difference between the outputs at terminals 14 and 13, a pulse output proportional to the product of the input signals can be obtained. I can do it.

Furthermore, if the input voltage V is AC, the above (4)
Since the term τa-B in the equation is canceled out and reduced by the first half cycle of AC and the second half cycle, the output difference between terminal 14 and terminal 13 is as follows, and a pulse output that does not include any error is obtained. I can do it.

In this way, according to the circuit shown in Fig. 1, it is possible to perform multiplication of input signals with extremely small influence of errors, or without including errors at all, so it is highly accurate, and moreover, A multiplier that does not cause a decrease in precision can be obtained.

Note that the present invention is not limited to the embodiment shown in FIG. 1 above. For example, the gates in FIG. 1 may be arranged in any manner as long as they perform similar logical operations. 1
By way of example, gate 6.7.8.9.10 can of course be replaced by an exclusive OR gate. Further, in the above embodiment, the timing circuit 25 controls the switch 22.
However, the output frequency of the pulse width modulator 3.4 or the oscillator 5 may be divided to perform on/off control of the switches 22.23.

Alternatively, the output of the pulse width modulator 3.4 may be directly input to a microcomputer or the like and processed by software without using the output signals from the oscillator 5 and timing circuit 25.

Furthermore, in the above embodiment, the pulse signal corresponding to the product of the input signals is obtained by taking the output difference between the output terminals 13 and 14, but by taking the difference between the above equations (1) and (2),
Specifically, at the output of the OR gate 10, the switch 2
Output pulse on time when switch 23 is on and switch 23
Similarly to the above embodiment, a signal proportional to the product of the input signals can be obtained by taking the difference from the output pulse on time when is on.

[Effects of the Invention] As described above with reference to the embodiments, the multiplier of the present invention reduces the error in the output of the pulse width modulator to the minimum. Furthermore, it is possible to perform multiplication without any errors. Furthermore, the circuit required for correcting this error can be constructed only from semiconductors, so it can be easily integrated into an IC. Furthermore, since the circuit has an error correction function, there is no need to use a high-performance operational amplifier in the pulse width modulator, so costs can be reduced. Similarly, since the circuit has an error correction function, it is possible to increase the frequency of the pulse width modulator, that is, the sampling frequency, and it is possible to obtain a multiplier that is resistant to fluctuations in the input signal.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a multiplier according to an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the circuit in FIG. 1, and FIG. 3 is a circuit diagram of a conventional multiplier. This figure is a waveform diagram for explaining the operation of the circuit of FIG. 3. 1.2... Input terminal 3.4... Pulse width modulator 5... Oscillator 6.7... Inverter gate 8.9.12... AND gate 10... OR gate 11... Frequency divider 13.14
...Output terminal 21...Input terminal

Claims (1)

[Claims] Means for converting each input signal into a pulse signal whose pulse width varies according to the level of the input signal and is asynchronous with each other, and a frequency higher than the frequency of the pulse signal output from the conversion means. an oscillation means for outputting a pulse signal of the above-mentioned oscillation means; and an inverted signal of at least one input signal is alternately switched together with this input signal by a pulse signal having a duty ratio of 1:1 and a frequency sufficiently slower than the output of the oscillation means to generate the above-mentioned pulse. a switching means input to the signal converting means; a pulse signal output from the converting means including an output based on an inverted signal of the input signal; a pulse signal output from the oscillating means; and a switching signal of the switching means; A digital signal proportional to the product of the input signal levels is obtained by performing a predetermined logical operation on the input signal and calculating the number of pulses output from the oscillation means in a predetermined time according to the pulse width of the pulse signal output from the conversion means. logical operation means for obtaining , and a function of correcting an error occurring in the conversion means due to alternate input of an input signal and its inverted signal via the switching means. Multiplier.