JPH025051B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a bipolar analog-to-frequency conversion circuit with a polarity display function that converts an analog signal such as voltage or current into a frequency and displays the polarity of the analog signal.

Conventional bipolar analog to frequency conversion circuits utilize unipolar analog to frequency conversion circuits, in which case a bias input is applied in advance or an analog signal is converted to an absolute value by an absolute value circuit, and the absolute value is Measures such as inputting the data into an A/D converter have been taken. However, these means cannot equalize the conversion accuracy of positive and negative analog signals, and narrow the input range of analog signals.
When the input level of the analog signal became low, there were problems such as incorrect polarity display. Another problem was to reduce offset drift errors that affect when a minute analog signal is input, and to prevent activation due to offset drift when no input is input.

An object of the present invention is to solve the above-mentioned problems and problems, to make the conversion accuracy equal for positive and negative signals, to reduce the input level of analog signals without narrowing the input range of analog signals. To provide a bipolar analog-to-frequency conversion circuit capable of accurately determining polarity even when no input is applied, greatly reducing offset drift errors, and eliminating startup due to offset drift during no input. That's true.

In order to achieve this object, the present invention provides an input switching circuit that alternately switches an input analog signal having a polarity and an input analog signal with a polarity opposite to that of the input analog signal, and an input analog signal that is input from the input switching circuit. An integration circuit that integrates a signal using circuit elements that share both polarities and outputs integrated output signals of different polarities depending on the polarity of the analog signal, and when the integrated output signal level of one polarity exceeds the reference value of one polarity. When the integrated output level of the other polarity exceeds the reference value of the other polarity, the comparison output signal is outputted from the second output signal, and the comparison output signal is outputted from the first output terminal and the second output terminal. A comparator circuit that resets the integrator circuit by a comparison output signal from an output terminal, a comparison output signal from a first output terminal of the comparison circuit, and a comparison output signal from a second output terminal following the signal. a frequency output signal generation circuit that generates a frequency output signal; a switching control circuit that switches the input switching circuit according to the rising edge of the comparison output signal from the first output terminal and the second output terminal of the comparison circuit; and an integration circuit of the integration circuit. The apparatus includes a polarity display circuit that determines and displays the polarity according to the polarity of the output signal and the switching state of the input switching circuit.

Hereinafter, the present invention will be explained in detail based on illustrated embodiments.

FIG. 1 shows an embodiment of the invention. Input terminal t ₁
An input analog signal Ex with polarity is input to
A reverse polarity input analog signal -Ex having a polarity opposite to that of the input analog signal Ex is input to the input terminal _t2 . The input switching circuit 1 consists of changeover switches 2 and 3 and switch drivers 4 and 5. The integrating circuit 6 consists of a resistor R, a capacitor C, an operational amplifier 7, a reset switch 8, and a reset switch driver 9, which are bipolar circuit elements. 10
is a comparator circuit consisting of two comparators 11 and 12 and reference power supplies 13 and 14 having the same reference voltage Es. A positive reference voltage +Es is applied to the inverting input terminal of the comparator 11, and a negative reference voltage -Es is applied to the non-inverting input terminal of the comparator 12. The first output terminal 15 and the second output terminal 16 of the comparison circuit 10 are buffers 17 and 18 for waveform shaping.
After that, RS flip-flop 19, or gate 2
0 and the polarity display circuit 21, respectively.
A frequency output signal is output from the output terminal Q of the RS flip-flop 19. A reset switch driver 9 and a single pulse generation circuit 22 are connected to the output side of the OR gate 20, and a T flip-flop 23 is connected to the output side of the single pulse generation circuit 22. Output terminal Q of T flip-flop 23
are connected to the polarity display circuit 21 and to the switch driver 5 via the switch driver 4 and inverter 24, respectively. The polarity display circuit 21 outputs a polarity display signal P, and in this embodiment, the polarity display signal P is low level and positive;
High level and negative are respectively displayed. Note that the changeover switches 2 and 3 and the reset switch 8 are constituted by, for example, field effect transistors.

Next, the operation will be explained with reference to the time chart shown in FIG. When the polarity of the input analog signal Ex is positive, the input analog signal +|Ex| is applied to the input terminal t ₁ , and the opposite polarity input analog signal - |Ex| is applied to the input terminal t ₂ . . When the initial output state of the T flip-flop 23 is at a low level, the switch driver 5 operates via the inverter 24, and the changeover switch 3 is turned on. Since the switch driver 4 does not operate, the changeover switch 2 is off. As a result, the reverse polarity input analog signal −|Ex| is input to the integrating circuit 6,
It is integrated in the positive direction. The comparator 11 compares the positive integrated output signal with a positive reference voltage +Es, and outputs a high-level comparison output signal from the first output terminal 15 when the integrated output signal level exceeds the positive reference voltage +Es. As a result, the outputs of the buffer 17 and the OR gate 20 also become high level. The reset switch 8 is turned on by the high level output of the OR gate 20, discharges the charge in the capacitor C, and sets the level of the integral output signal to zero potential, which is the integration start potential. At the same time, Batsuhua 17
The RS flip-flop 19 is set by the output of the RS flip-flop 19, and the output level of its output terminal Q becomes high level. Furthermore, the single pulse generating circuit 22 generates a single pulse with a predetermined pulse width due to the rise of the output of the OR gate 20, and the T flip-flop 23 generates a single pulse with a predetermined pulse width.
input terminal T, and sets the output level of its output terminal Q to high level. As a result, the switch driver 4 operates and turns on the changeover switch 2, and the switch driver 5 stops operating and turns off the changeover switch 3, so that the input analog signal + |Ex| is input. As the integration output signal level returns to zero potential, the comparison output signal becomes zero level, so the reset switch 8 turns off, and the integration circuit 6 now inputs the input analog signal +|Ex| in the negative direction. Integrate. The comparator 12 outputs a high level comparison output signal from the second output terminal 16 when the negative integrated output signal is less than the negative reference voltage -Es. the result,
The outputs of the buffer 18 and the OR gate 20 become high level, the RS flip-flop 19 is reset, the output level of its output terminal Q becomes low level, the reset switch 8 is turned on, and the charge in the capacitor C is discharged. The single pulse generating circuit 22 generates a single pulse to bring the output of the T flip-flop 23 to a low level, turning off the changeover switch 2 and turning on the changeover switch 3. As long as this operation is repeated and the polarity of the input analog signal Ex does not change, the integrated output signal of the integrating circuit 6 will have a periodicity as shown in FIG.
The waveform is a sawtooth wave that is alternately folded back at T ₁ and T ₂ . Then, while the polarity of the input analog signal Ex does not change, the first output terminal 15 and the second output terminal 16 of the comparator circuit 10 output comparison output signals alternately, and the comparison output signal from the first output terminal 15 and Both subsequent comparison output signals from the second output terminal 16 cause the RS flip-flop 19 to generate a pulse, which it outputs as a frequency output signal.

The polarity display circuit 21 determines and displays the polarity of the input analog signal Ex according to the outputs of the buffers 17 and 18 and the T flip-flop 23, and an example thereof is shown in FIG. 25 is a delay circuit;
26 and 27 are inverters, 28 to 31 are AND gates, 32 and 33 are OR gates, and 34 is an RS flip-flop. This polarity display circuit 21 is
T just before buffer 17 outputs a high level output
If the output of the flip-flop 23 is low level, the polarity is determined to be positive, and if it is high level, the polarity is determined to be negative, and the output of the T flip-flop 23 immediately before the buffer 18 outputs a high level output is determined to be low level. If so, the polarity is determined to be negative, and if it is high level, the polarity is determined to be positive. That is, immediately before the buffer 17 outputs a high level output, the integration circuit 6 is integrating in the positive direction, so the polarity of the analog signal input to the integration circuit 6 is negative, and at that time the output of the T flip-flop 23 is Since the low level means that the changeover switch 3 is on, the input analog signal is the reverse polarity input analog signal -Ex, and if its polarity is negative, the polarity of the input analog signal Ex is positive. It will become.

In FIG. 3, when the high level output of the buffer 17 is input to the AND gates 28 and 31, the output of the T flip-flop 23 immediately before it is delayed by the delay circuit 25, and is directly input to the AND gate 28 and then to the AND gate 28, 31. Inverter 27 to gate 31
Since the output of the delay circuit 25 is low level, the AND gate 31 inputs the high level output through the OR gate 33.
Reset input terminal R of RS flip-flop 34
This is reset, and the polarity display signal P is set to low level, indicating that the polarity is positive. If the output of the delay circuit 25 is high level, the AND gate 28 sends the high level output to the OR gate 32.
The signal is sent to the set input terminal S of the RS flip-flop 34 through the RS flip-flop 34, and is set to set the polarity display signal P to a high level, indicating that the polarity is negative.

When the high level output of the buffer 18 is input to the AND gates 29 and 30, the output of the T flip-flop 23 immediately before it is delayed by the delay circuit 25,
and directly to the AND gate 30, so if the output of the delay circuit 25 is low level, the AND gate 29 outputs a high level output, sets the RS flip-flop 34, and displays the polarity. When the signal P is set to high level and the output of the delay circuit 25 is high level, the AND gate 30 outputs a high level output, the RS flip-flop 34 is reset, and the polarity display signal P is set to low level.

The relationship between the input analog signal Ex and the frequency output signal, including the influence of the offset drift V, is as follows.

Frequency output signal is RS flip-flop 19
Therefore, its period is equal to the period T=T ₁ +T ₂ of the integral output signal of the integrating circuit 6. period
T ₁ and period T ₂ are expressed by the following formula.

T ₁ = C・R・Es/Ex+V (1) T ₂ =C・R・(−Es)/−Ex+−V=C・R・Es/E
x−V(2) Therefore, T=T ₁ +T ₂ = C・R・Es/Ex+V+C・R・Es/Ex
-V= 2Ex・C・R・Es/E ² / _x −V ² / _y (3) = 1/T=E ² / _x −V ² / _y /2Ex・C・R・Es= Ex/2・C・R・Es−V ² / _f /E ² / _x /2・C・R・Es(4
) That is, the second term in equation (4) is the conversion error due to the offset drift V. Let this conversion error be △,
Let ' be the frequency output signal when there is no offset V, then equation (5) is obtained.

△=-'/'=-V ² / _f /E ² / _x (5) In other words, the influence of offset drift V within one period T of the frequency output signal can be seen from equations (1) and (2). Thus, the influence of the offset drift V is reduced to -V ² /E ² _x .

Input analog signal Ex for integration direction of integration circuit 6
The input analog signal Ex can be converted into a frequency by limiting it to only the positive direction or only the negative direction depending on the polarity of , the influence of offset drift V is not reduced. For example, in the case of positive integration only, the frequency output signal
₁ and the conversion difference △ ₁ are as follows.

₁ = 1/T ₁ = Ex+V/C・R・Es (6) △ ₁ = ₁ −′ ₁ /′ ₁ = V/Ex (7) As an example, when Ex=100mV and V=10mV, When calculating the conversion error, it is -1% in this embodiment, whereas it is 10% in the case of only integration in the positive direction.

Furthermore, the following advantages arise by inverting the polarity of the integral output signal within one period T of the frequency output signal. That is, in the case of integration only in the positive or negative direction, if Ex=0, equation (6) becomes the following (8)
Therefore, even when there is no input, a frequency output signal ₁ proportional to the offset drift V is output.

₁ = 1/T ₁ = V/C・R・Es (8) On the other hand, according to this embodiment, if Ex=0 in equation (4), then =−∞ (9), that is, It will not start if there is no input.

According to this embodiment, each circuit element of the integrating circuit 6 is shared by the input analog signal of positive and negative polarity +|Ex| or -|Ex|, and the level of the integral output signal is positive or negative and absolute. Since the values are the same, the conversion precision for positive and negative can be made equal. On the other hand, in conventional bipolar analog-to-frequency conversion circuits with absolute circuits, the absolute value of the circuit has errors of one polarity, such as resistor matching errors and offset errors, and these errors are caused by the positive input. and negative inputs have the opposite effect, so it is not possible to equalize the conversion accuracy for positive and negative inputs. Further, according to this embodiment, the buffer 1
Since the polarity of the input analog signal Ex is determined according to the outputs of 7, 18 and the T flip-flop 23, the polarity can be accurately determined even if the level of the input analog signal Ex is small. In bipolar analog-frequency conversion circuits, the polarity is determined by comparing the level of the input analog signal with the zero level using a comparator, so when the level of the input analog signal becomes small,
The output of the comparator becomes unstable and the polarity cannot be determined accurately. Furthermore, according to the present embodiment, the integrating circuit 6 outputs integral output signals of different polarities, and can use the full range of both positive and negative polarities, so the input range of analog signals is not narrowed. In conventional bipolar analog-to-frequency conversion circuits that apply a bias input, the integrator circuit uses only the positive output range for both positive and negative inputs, so the input range of the analog signal is narrowed to 1/2. I end up.

In the illustrated embodiment, the RS flip-flop 1
9 corresponds to the frequency output signal generation circuit of the present invention,
Single pulse generation circuit 22, T flip-flop 2
3 and the inverter 23 correspond to the switching control circuit of the present invention.

In addition, in FIG. 2, the time during which the input analog signal Ex is held positive or negative is approximately twice the period T of the integral output signal of the integrating circuit 6, but this is due to the relationship in the diagram. Actually, it is significantly longer than the period T.

The integrating circuit 6 is not limited to one using the operational amplifier 7. For example, if the input analog signal is a current, it may consist only of a resistor, a capacitor, and a reset switch.

The comparison circuit 10 includes two comparators 11 and 12.
However, the present invention is not limited to using one comparator, and the output may be distributed to the first output terminal 15 and the second output terminal 16 according to the positive or negative sign of the integral output signal.

The polarity display circuit 21 is not limited to that shown in FIG. In the integrating circuit 6, it is detected analogously or digitally that negative integration has continued twice or positive integration has continued twice, and the polarity is determined based on the output of the T flip-flop 23 at that time. You may also do so.

As explained above, according to the present invention, since the input analog signal or the reverse polarity input analog signal is integrated by the circuit element that can be used for both polarities in the integrating circuit, the conversion precision for positive and negative signals is equalized. be able to. Further, since the integration circuit outputs integrated output signals of different polarity depending on the polarity of the analog signal inputted thereto, the input range of the analog signal is not narrowed. Furthermore, since the polarity is determined and displayed according to the polarity of the integral output signal of the integrating circuit and the switching state of the input switching circuit, the polarity can be accurately determined even when the input level of the analog signal becomes low. Can be done. Moreover, each time the integrated output signal exceeds the reference value, the input analog signal and the reverse polarity input analog signal are alternately switched and input to the integrating circuit.
Offset drift errors can be significantly reduced, and activation due to offset drift during no input can be eliminated. As a result, excellent linearity can be achieved during minute inputs.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a time chart of voltage waveforms at various parts thereof, Fig. 3 is a circuit diagram of a polarity display circuit in an embodiment of the invention, and Fig. 4 is its circuit diagram. This is a time chart of voltage waveforms at various parts. 1...Input switching circuit, 2, 3...Switching switch, 6
...Integrator circuit, 8...Reset switch, 10...Comparison circuit, 13, 14...Reference power supply, 15...First output terminal, 16...Second output terminal, 19...RS flip-flop, 21...Polarity display circuit, 22...Single Pulse generation circuit, 23...T flip-flop, Ex...input analog signal, -Ex...reverse polarity input analog signal, Es...reference voltage,...frequency output signal, P...
Polarity display signal.

Claims (1)

[Claims] 1. An input switching circuit that alternately switches an input analog signal having a polarity and a reverse polarity input analog signal that has a polarity opposite to that of the input analog signal, and a circuit element that can share the analog signal input from the input switching circuit with both polarities. an integrating circuit that integrates the signal and outputs an integral output signal of different polarity depending on the polarity of the analog signal;
A comparison output signal is output from the second output terminal when the integrated output signal level of the other polarity exceeds the reference value of the other polarity, and the comparison output signal of the first output terminal and the second output terminal is output from the second output terminal. a comparator circuit that resets the integrator circuit by
The comparison output signal from the output terminal and the second signal following this signal
a frequency output signal generation circuit that generates one frequency output signal based on the comparison output signal of the output terminal;
A switching control circuit in which the first output terminal and the second output of the comparison circuit switch the input switching circuit according to the rising edge of the comparison output signal from the terminal, and a switching control circuit that switches the input switching circuit depending on the polarity of the integral output signal of the integrating circuit and the switching state of the input switching circuit. A bipolar analog-to-frequency conversion circuit comprising a polarity display circuit for determining and displaying polarity.