JPH0360525A - Pwm system a/d converter - Google Patents

Abstract

PURPOSE:To remove off-set from the output of a PWM integrator and to improve accuracy for an A/D converter by dividing the frequency of a clock, which passes a photocoupler and generates the off-set, by a frequency dividing circuit in a simple configuration and executing waveform shaping. CONSTITUTION:The frequency of a reference clock E to be generated from a reference clock generating circuit 6 of a digital part 2 is made double to a frequency required as a clock for measurement. In an analog part 1, a two- frequency dividing circuit 12 is newly provided between a buffer amplifier 7 and a resistor R2. The frequency of the reference clock E to be inputted to a photocoupler 5 is made double to a conventional example (namely, a half period is T/2.) After transmission by the photocoupler, the waveform in a B point is rounded samely as the conventional example and the duty of the clock through the buffer amplifier 7 is deviated from 50%. However, since the frequency of this clock is divided into two by the two-frequency dividing circuit 12 composed of a T type flip-flop and the waveform is shaped, the clock for measurement (waveform in a D point) can be obtained with the deisred period (2T) and duty 50%.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an A/D converter, and particularly to a PWM (Pulse Width Modulation) type A/D converter.

(Prior art) A PWM type A/D converter does not need to feed back the digital output to the analog section at the input end, making it easy to separate the analog section and digital section, and also has excellent noise removal characteristics in normal mode. It has characteristics such as very good
Widely used as a low-speed A/D converter.

FIG. 3 is a circuit diagram showing the configuration of an example of a conventional PWM type A/D converter.

In this conventional example, an analog section 1 and a digital section 2 are separated, and an input signal (DC voltage) Vl is inputted to an integrator 4 composed of an operational amplifier 3 and a capacitor C1 via an input resistor R1. . A measurement clock is supplied to the input terminal of the integrator 4 (common connection point of the operational amplifier 3, capacitor C1, and input resistor R1), and this measurement clock is a reference signal generated from the reference clock generation circuit 5 in the digital section 2. The clock A is connected to the analog section 1 via the photocoupler 6.
This measurement clock is supplied to the input terminal of the integrator 4 via a resistor R2° and a capacitor C2.

The output signal of the integrator 4 is input to a comparator 8, whose complementary output Q1. Q2 is input to control logic 9 and amplifier IO, respectively. The switch svl is switched by the output of the amplifier IO, and thereby two reference currents +1. , -1. are supplied alternately.

The output signal of the control logic 9 is input to the counter and latch ti, a predetermined count is performed, and the input signal 1 is converted into a digital signal.

Note that the reason why the analog section 1 and the digital section 2 are separated is to prevent digital noise from being superimposed on the analog section and to prevent adverse effects caused by different reference voltages, etc. used. be.

The A/D conversion operation in this conventional example will be explained using FIG. 4.

When the input signal V1 is applied to the input end of the integrator 4, the input signal current 11 flows through the input resistor R1.

In addition to this, a measurement clock signal with a duty of -50% (that is, a clock current of ±Ic) is supplied. In addition, the switch SW is set according to the polarity of the output of the comparator 8.
I is switched and the reference current +I□ or -IR is supplied.

This operation results in tl during one prescribed cycle.

t2. t3. Each integration period of t4 occurs. input signal v
If 1 is positive, during t1 period (-IC+IR+I+)
Then, during the t2 period, it is (+IC+IR+1,), during the t3 period, it is (+ICIR+I+), and during the t4 period, it is (ICIR
+I is respectively integrated, and this integration operation is performed so as to satisfy tl+t4-t2+t3. As a result, the following conversion formula is obtained.

Vl-R1・I3・(T2-TI)/(TI+T2
) Therefore, by counting the period until the polarity of the output Q1 of the coverlet 8 is reversed, the digital value is uniquely determined by applying the counted value to the above conversion formula, and thereby converts the input signal V1 to a digital signal. can do.

(Problems to be Solved by the Invention) Since the conventional PWM type A/D converter described above uses a photocoupler to couple the analog part and the digital part, problems arise due to the response characteristics of this photocoupler. Therefore, the duty of the supplied measurement clock deviates from 50%, resulting in an offset in the output of the PWM integrator.

That is, as shown in FIG. 5, even if the duty of clock A (period 2T) output from the reference clock generation circuit 5 is 50%, due to the characteristics of the photocoupler, B in FIG. The waveform becomes dull at point C, and as a result, a delay of τ]1 τ2 occurs at point C, and the duty becomes (T-τ1
+τ2)/(1-τ2 at T+). Here, T is the half cycle of clock A, τ1 is the delay time until high level detection due to the rising characteristics of the photocoupler, and τ2 is the delay time until low level detection due to the falling characteristics of the photocoupler. It is.

In order to reduce the offset caused by this delay, it is necessary to use a high-speed photocoupler, but this increases the cost.

It is also conceivable to remove the offset by providing an offset correction circuit and performing fine adjustment, but in this case, the device becomes larger and the cost increases.

The present invention has been made in view of the above-mentioned problems, and
Its purpose is to reduce the PW generated due to the characteristics of photocouplers.
The purpose of the present invention is to improve the reliability of an A/D converter by removing the offset of an M integrator without complicating the circuit or increasing costs.

(Means for Solving the Problems) A PWM type A/D converter of the present invention includes a reference clock generating means for generating a reference clock having a frequency n times that of the measurement clock (n is a natural number of 2 or more). a photocoupler for transmitting the reference clock to a part electrically separated from the reference clock generation means, and a duty-50 divided by n frequency of the reference clock obtained through the photocoupler. % of the measurement clock.

(Function) Transmits the frequency-multiplied clock using a photocoupler,
The resulting offset clock is frequency-divided and waveform-shaped using, for example, either the rising edge or the falling edge as a trigger edge, thereby obtaining a measurement clock with a duty of -50%.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation of this embodiment.

Since the basic A/D conversion operation of this embodiment is the same as that of the conventional example shown in FIG. 3, the explanation will be omitted, and only the characteristic parts and their operations will be explained. In the drawings, parts that are the same as or correspond to those of the conventional example are given the same reference numerals.

The features of this embodiment are that the frequency of the reference clock E generated from the reference clock generation circuit 6 of the digital section 2 is twice the frequency required as a measurement clock, and
In the analog section 1, a divide-by-2 circuit 12 is newly provided between the buffer amplifier 7 and the resistor R2. This divide-by-2 circuit 12 is composed of a positive edge trigger T-type flip-flop.

As shown in FIG. 2, the frequency of the reference clock E input to the photocoupler 5 is twice that of the conventional example (that is, the half cycle is T/2). The waveform at point B after transmission by the photocoupler becomes dull as in the conventional example, and the duty of the clock passed through the buffer amplifier 7 deviates from 50%.

However, by dividing this frequency by 2 using a divide-by-2 circuit I2 consisting of a T-type flip-flop and shaping the waveform, a measurement clock (waveform at point D) with a desired period (2T) and a duty of -50% can be obtained. Obtainable.

In this embodiment, the photocoupler 5 can be the same inexpensive one as the conventional one, and it is only necessary to add one divide-by-2 circuit composed of a flip-flop or the like, so that the device does not become larger or more expensive. do not have.

In this embodiment, the original clock is multiplied by 2, and the frequency is divided by 2 after passing through the photocoupler. However, the multiplication ratio (frequency division ratio) can be arbitrarily selected without being limited to this.

(Effects of the Invention) As explained above, the present invention has a configuration in which a clock that has passed through a photocoupler and has an offset is divided by a frequency divider circuit of a simple configuration and shaped into a waveform. The offset can be removed from the output of PW
The accuracy of the M-type A/D converter can be improved.

Furthermore, since an expensive photocoupler is not required and the added circuitry can be simple, it can be easily implemented without increasing the size of the device or increasing costs.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the characteristic operation of the embodiment of FIG. 1, and FIG. 3 is a circuit diagram of a conventional example. FIG. 4 is a timing chart for explaining the basic operation of the conventional example shown in FIG. 3, and FIG. 5 is a waveform diagram for explaining problems in the conventional example shown in FIG. 1...Analog section 2...Digital section 3...
- Operational amplifier 4... Integrator 5... Photocoupler 6... Reference clock generation circuit 7... Buffer amplifier 8... Comparator 9.
...Amplifier IO...Control logic ll...Counter and latch R1...Input resistance R2...Resistance C1, C2
... Capacitor h ... Input signal current ±IR ... Reference current E ... Frequency multiplied reference clock Fig. 2

Claims (1)

[Scope of Claims] An analog signal to be A/D converted is input to the input end of an integrator, a measurement clock with a duty of 50% is supplied to the input end separately from the analog signal, and the integrator is The output is input to a comparator, and two reference currents with different polarities are alternately switched and supplied to the input terminal of the integrator according to the polarity of the output of the comparator, and the integration period in the integrator is counted by a counter. , P converts the analog signal into a digital signal using the count.
In the WM type A/D converter, a reference clock generating means for generating a reference clock having a frequency n times that of the measurement clock (n is a natural number of 2 or more); is a photocoupler for transmitting to an electrically isolated part, and the reference clock obtained through the photocoupler is n
A PWM type A/D converter comprising: an n frequency divider circuit that divides the frequency and outputs the measurement clock having a duty of 50%.