JP2007081656A - Periodic pulse generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a periodic pulse generation circuit capable of inexpensively achieving a high-frequency periodic pulse signal with a narrow circuit area. <P>SOLUTION: The periodic pulse generation circuit is provided with inverter circuits 101-103 for generating n-phase (n is an integer of ≥3) periodic signals, n sets of negative AND circuits 104-106 for extracting a phase-shift difference between respective phases of the periodic signals from the inverter circuits 101-103, and a negative OR circuit 107 for taking the OR of output signals of the negative AND circuits 104-106. Namely, it is possible to generate the high-frequency periodic pulse signal up to the element performance limit in order to generate a higher-frequency periodic pulse signal on the basis of an oscillation frequency of an oscillation circuit, by constituting the periodic pulse generation circuit after adding a small number of AND circuits to the oscillation circuit generating the n-phase periodic signals. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a periodic pulse generation circuit that generates a periodic pulse signal having a high frequency.

  A periodic pulse signal is often used as a clock signal for a digital circuit, a carrier wave signal for communication in an analog circuit, or a local oscillation signal. Oscillator circuits for this purpose have been extensively studied. In addition, the oscillation circuit often determines the performance of the system in essence, and is required to oscillate at a high frequency as much as possible in order to operate the system at high speed. In recent years, the demand for system-on-chip has increased, and there are many demands for forming an entire system including an oscillation circuit on a semiconductor chip.

When the oscillation circuit is formed on the semiconductor chip, the LC oscillation circuit using the cross-coupled element is in a state in which the charge charged in the stray capacitance on the semiconductor chip is pulled back by the inductance and compensated. For this reason, it is said that it is possible to oscillate at a high frequency up to the limit of the device performance with low power consumption (see Non-Patent Document 1).
However, the inductance element that must be formed on the semiconductor chip is large and expensive.

  A ring oscillation circuit is an example that is often used as an oscillation circuit formed on a semiconductor chip. This does not require an inductance element, so it can be made very compact and there is no cost problem. However, since there is no element that limits the oscillation frequency like an LC resonance circuit, there is a lot of noise equivalent to phase noise. It is said that. In addition, it was difficult to make the performance of the stray capacitance on the integrated circuit and the active element that drives the load constant, and it was difficult to perform high-precision oscillation. Difficulties are being removed (see Patent Document 1).

As an example of the ring oscillation circuit, FIG. 7 shows a conventional simplest three-stage ring oscillation circuit. When the three-stage inverter circuits 701, 702, and 703 are connected in a ring shape, the inverter outputs N1, N2, and N3 oscillate as shown in the waveform shown in FIG. Assuming that the delay time of each inverter is td, the oscillation period is 6 td. However, for the sake of simplicity, it is assumed that the time from the input rising to the output falling of the inverters 701 to 703 is the same as the time from the input falling to the output rising.
Japanese Patent No. 2737747 A 90-GHz Voltage-Controlled Oscillator with a 2.2 GHz Tuning Range in a 130-nm CMOS Technology, Changhua et. al, 2005 Symposium on VLSI Circuits Digest of Technical Papers, pp242-243.

However, the ring oscillation circuit, which is a conventional periodic pulse generation circuit, has a problem in that a pulse signal having a higher frequency cannot be obtained because the maximum oscillation frequency is essentially determined by the stray capacitance of the circuit. In the three-stage ring oscillation circuit shown in FIG. 7, the reciprocal of the oscillation period 6td shown in FIG. 8 is the limit of the maximum oscillation frequency.
In addition, the LC oscillation circuit can generate a periodic pulse signal having a higher frequency than the ring oscillation circuit, but there is a problem that the element area is large and the cost is high.

  Accordingly, an object of the present invention is to provide a periodic pulse generating circuit capable of realizing a high-frequency periodic pulse signal at a low cost and a small circuit area.

In order to achieve the above object, according to a periodic pulse generating circuit according to an aspect of the present invention, an oscillation circuit that generates an n-phase (n is an integer of 3 or more) periodic signal, and each phase of the periodic signal It is characterized by comprising n sets of AND circuits for extracting the phase shift difference and an OR circuit for calculating the logical sum of the output signals of the n sets of logic circuits.
As a result, a periodic pulse generation circuit is configured by adding a small number of AND circuits to an oscillation circuit that generates an n-phase periodic signal, so that a higher frequency can be obtained based on the oscillation frequency of the oscillation circuit. In order to generate a periodic pulse signal, it is possible to generate a periodic pulse signal having a high frequency up to the element performance limit.

In the periodic pulse generation circuit according to one aspect of the present invention, the oscillation circuit is a ring oscillation circuit.
As a result, a small ring oscillation circuit can be used as an oscillation circuit instead of an oscillation circuit having a large element area such as an LC oscillation circuit, so that the conventional LC oscillation can be achieved with a circuit scale as small as a conventional ring oscillation circuit. It is possible to generate a periodic pulse signal with a frequency as high as that of a circuit.

Further, according to the periodic pulse generation circuit of one aspect of the present invention, the ring oscillation circuit has a means for controlling the inflow current, and the oscillation frequency of the ring oscillation circuit is set in accordance with an input signal to the means. The periodic pulse generating circuit according to claim 2, wherein the periodic pulse generating circuit is variable.
As a result, the oscillation frequency of the ring oscillation circuit can be controlled by an external input signal, which enables control of the frequency and accuracy of the generated periodic pulse signal, enabling stable and highly accurate signal generation. To do.

In addition, according to the periodic pulse generation circuit of one aspect of the present invention, an oscillation circuit that generates two periodic signals having a phase difference of 90 degrees and an exclusive OR that takes an exclusive OR of the two signals are provided. And a circuit.
As a result, a periodic pulse signal train is generated by taking the exclusive OR of two periodic signals having different phases of 90 degrees generated by the oscillation circuit, so that the periodic pulse signal having a frequency twice the maximum frequency that the oscillation circuit can oscillate. Can be generated.

According to the periodic pulse generation circuit of one aspect of the present invention, the oscillation circuit is configured by an inverter circuit configured by a CMOS current mode logic circuit, and the oscillation frequency is variable by controlling the inflow current of the inverter circuit. It is possible to make it possible.
As a result, since the oscillation circuit is constituted by a CMOS current mode logic circuit, it is possible to perform oscillation with high energy efficiency at a high frequency, and it is possible to adjust the oscillation amplitude and frequency.

In the periodic pulse generation circuit according to one aspect of the present invention, any one of the logical product circuit, the logical sum circuit, and the exclusive logical sum circuit is configured by a CMOS current mode logic circuit. And
As a result, since the logic circuit is constituted by the CMOS current mode logic circuit, a high frequency and energy efficient circuit can be constructed, and the amplitude of the signal generated can be adjusted.

In the periodic pulse generation circuit according to one aspect of the present invention, the ring oscillation circuit is included in a phase locked loop, and the phase locked loop is controlled to be phase-synchronized with a predetermined reference frequency signal. It is characterized by.
As a result, the ring oscillation circuit is included in the phase lock loop and phase-locked to a predetermined reference frequency, so that the oscillation frequency is fixed to a predetermined value and a periodic pulse signal having an accurate frequency can be generated.

  The periodic pulse generation circuit according to one aspect of the present invention includes a second ring oscillation circuit configured by an element having characteristics similar to the ring oscillation circuit, and the second ring oscillation circuit. And a second phase locked loop controlled so as to be phase-synchronized with a signal having a reference frequency of the second frequency, and an inflow current of the second ring oscillation circuit is controlled by phase locked control of the second phase locked loop. It is characterized by that.

  Accordingly, there is a second ring oscillation circuit having characteristics similar to those of the ring oscillation circuit used for generating the periodic pulse, and when the second ring oscillation circuit is phase-locked to a predetermined reference frequency by a phase-locked loop. Since the oscillation frequency of the periodic pulse generation circuit is controlled by a signal similar to the oscillation frequency control signal of the second ring oscillation circuit, it is possible to generate a periodic pulse with an accurate frequency.

Hereinafter, a pulse generation circuit according to an embodiment of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a circuit diagram showing the main part of a periodic pulse generating circuit according to the first embodiment of the present invention, and FIG. 2 is a time chart schematically showing its operation.
In FIG. 1, reference numerals 101 to 103 denote inverter circuits connected in a ring shape, which constitute a ring oscillation circuit. Each output terminal is given a terminal name such as N1 to N3. As shown in FIG. 2, each output terminal N1, N2, N3 generates a periodic signal with a delay of each delay time td of each inverter circuit 101-103.

The NAND circuits 104 to 106 have their input terminals connected to the output terminals N1 to N3 of the inverter circuits 101 to 103, and the signals of both the output terminals N3 and N1, N1 and N2, and N2 and N3 are received. When H (high level), L (low level) is output to the terminals ND1 to ND3.
The negative logical sum circuit 107 (negative logical negative logical sum circuit) has its input terminal connected to the output terminals ND1 to ND3 of the negative logical product circuits 104 to 106, and even if one of each ND1 to ND3 is L When H is output to the output terminal NR, the target pulse waveform is obtained.

FIG. 2 also shows a situation in which each of the NAND circuits 104 to 106 and the NOR circuit 107 outputs a signal with a delay. For example, in the figure, N1 and N2 are H at time t1, but ND1 does not immediately output L but delays by time td and outputs L at time t2. Further, NR outputs H at time t3 with a delay of time td.
Note that FIG. 2 is a schematic diagram, and the output of each node is digitally drawn. However, when operating at a high frequency near the limit of the device performance, the signal output can be swung to a sufficient logic level. Therefore, an analog signal almost similar to a sine wave is output.

The pulse width of the pulse signal output from the NAND circuits 104 to 106 is only the delay time td of the inverter circuits 101 to 103, and the period of the periodic signal output to the final stage output terminal NR is 2td. This provides an effect that the frequency becomes three times higher than the oscillation period 6td of the conventional three-stage ring oscillation circuit.
That is, according to the periodic pulse generation circuit of the first embodiment, it is possible to generate a high-frequency periodic pulse signal that could not be achieved by the conventional circuit. Further, since only the inverter circuits 101 to 103, the negative logical product circuits 104 to 106 and the negative logical sum circuit 107 are used, a high-frequency oscillation circuit can be realized on a small area by a simple CMOS (Complementary Metal-Oxide Semiconductor) process. Is possible. Therefore, the periodic pulse generation circuit can realize a high-frequency periodic pulse signal at a low cost and a small circuit area.
(Second Embodiment)
FIG. 3 is a circuit diagram showing a main part of a periodic pulse generating circuit according to the second embodiment of the present invention.

Reference numerals 301, 302, 303,..., 30n denote inverter circuits, and n stages (n is an integer of 3 or more) are connected in a ring shape to constitute a ring oscillation circuit. These correspond to the ring oscillation circuit configuration by the inverter circuits 101 to 103 of the first embodiment.
The oscillation frequency of such a ring oscillation circuit is determined by the drive capability of the inverter circuit constituting the oscillation circuit and the load capacitance connected thereto. If high-frequency oscillation is desired, the drive capacity of the inverter circuit must be increased and the load capacity to be driven must be reduced. In addition to the stray capacitance of the wiring and the input capacitance of the circuit connected to extract the signal, the load capacitance includes the input capacitance of the inverter circuit at the next stage connected to configure the ring oscillation circuit.

  If the drive capability of the inverter circuit is increased, charging and discharging can be performed more rapidly and the oscillation frequency can be increased with respect to the floating capacitance of the wiring and the input capacitance of the signal extraction circuit. However, if the drive capability of the inverter circuit is increased, the input capacity of the inverter circuit is also increased, and there is a limit to obtaining high frequency oscillation by increasing the drive capability. Without the wiring stray capacitance and the signal extraction circuit, the oscillation frequency of the ring oscillation circuit is determined regardless of the drive capability of the inverter circuit that constitutes it. In order to oscillate at a high frequency, it is effective to reduce the stray capacitance of the wiring and the capacitance of the signal extraction circuit.

  Therefore, the buffer circuits 311, 312, 313,..., 31 n for signal extraction connected to the output side of each of the inverter circuits 301 to 30 n are inverters with intentionally low driving capability in order to reduce the input capacity. A circuit was used. The signals taken out in this way are amplified once more by the buffer circuits 321, 322, 323,..., 32n having a large driving capability, and then logical products are obtained by the AND circuits 331, 332,. The logical sum circuit 340 performs synthesis by logical sum processing. Thereby, a high-frequency periodic pulse signal is generated.

In this way, it is possible to configure a ring oscillation circuit that oscillates at a high frequency, and to generate a periodic pulse signal having a high frequency up to the limit of the capability of the semiconductor integrated circuit.
As described above, in the second embodiment, the number of stages of the ring oscillation circuit is an integer n stages of 3 or more. Although n is normally an odd number, if a differential circuit is used, an even-numbered ring oscillation circuit can be constructed. By increasing n, the oscillation frequency of the ring oscillation circuit can be lowered, but the circuit becomes complicated. The frequency of the obtained periodic pulse is the same as in the case of n = 3, and the power consumption of the ring oscillation circuit is also the same. A circuit of n> 3 is an effective means when it is desired to avoid the frequency when the oscillation frequency of the ring oscillation circuit affects other parts of the system as noise.

Thus, in the second embodiment, a high-accuracy periodic pulse signal having a high frequency up to the element limit can be easily generated with a simple small-scale circuit. It can be easily mounted on a semiconductor integrated circuit and can be easily manufactured.
(Third embodiment)
FIG. 4 is a circuit diagram showing a main part of a periodic pulse generating circuit according to the third embodiment of the present invention, and FIG. 5 is a time chart for explaining its operation.

  The periodic pulse generation circuit includes a four-phase differential ring oscillation circuit 411 and an exclusive OR circuit 406. The differential ring oscillation circuit 411 is configured to include two flip-flop circuits 403 and 405 having the same configuration, and the flip-flop circuits 403 and 405 each include two negation logical sums as represented by reference numeral 403. Circuits 401 and 402 are provided. One NOR circuit 401 includes MOS transistors M1 to M3, and the other NOR circuit 402 includes MOS transistors M4 to M6.

  One negative OR circuit 401 outputs a negative logical sum of voltages applied to the gates of the NMOS transistors M2 and M3 to the node Q1. The PMOS transistor M1 functions as a load resistor and generates a voltage drop when a current flows through the transistor M2 or M3, and outputs a signal. The power is supplied to the terminal 408, and the terminal 409 is grounded. The gate of the transistor M1 is connected to the terminal 404, and the current value flowing into the transistor M1 can be controlled by the voltage applied to the terminal 404, whereby the operation speed of the NOR circuit 401 can be controlled. It is like that.

A negative OR circuit 402 is configured with the same connection, and a set / reset type flip-flop circuit 403 is configured by connecting one input, that is, the gate of the transistor M3 and the gate of M5 to the output nodes XQ1 and Q1. . Here, the nodes Q1 and XQ1 are output terminals, S1 is a set terminal, and R1 is a reset terminal.
Another flip-flop circuit 405 having the same configuration as that of the flip-flop circuit 403 is prepared, and a ring oscillation circuit 411 is configured by the two flip-flop circuits. That is, the output terminals Q1 and XQ1 of the flip-flop circuit 403 are respectively connected to the reset terminal R2 and the set terminal S2 of another flip-flop circuit 405, and the output terminals Q2 and XQ2 of the flip-flop circuit 405 are respectively flip-flop circuits. It can be configured by connecting to a set terminal S1 and a reset terminal R1 of 403. As a result, it is possible to obtain four-phase oscillation outputs Q1, Q2, XQ1, and XQ2 whose phases are different by 90 degrees.

  Further, the input terminals of the flip-flop circuits 403 and 405, that is, the set and reset terminals R1, S1, R2 and S2 are only one gate of the NMOS transistor, and this constitutes the inverter circuit described in the first embodiment in CMOS. It is possible to reduce the load to about 1/3 as compared with the case of doing so. This is because in the CMOS inverter circuit, the gates of two transistors, PMOS and NMOS, are connected on the input side, and the PMOS transistor requires about twice as large as the NMOS transistor. As a result, the differential ring oscillation circuit 411 can oscillate at a high frequency.

  Reference numeral 406 denotes an exclusive OR circuit configured by a current mode logic circuit, which includes MOS transistors M13 to M21. The current mode logic circuit uses differential signals as input and output. Therefore, depending on which of the differential pair is considered as a positive terminal, either negative logic or positive logic can be handled, and logical product and logical sum can be realized by the same circuit. Here, the expression “exclusive OR” is used in the following description, but it is assumed that other expressions are possible depending on the interpretation of each terminal.

  The four outputs Q1, XQ1, and Q2, XQ2 of the four-phase differential ring oscillation circuit 411 are differential signals, and are considered to be 90 degrees out of phase with each other. 4, as shown in the waveform of each signal in FIG. 5, as the differential signals at the terminals X and XX, the exclusive OR of the differential signals Q1 and XQ1 and the differential signals Q2 and XQ2 is obtained. The result is output. That is, X = XQ1 · Q2 + Q1 · XQ2 is outputted to the terminal X, and XX = XQ1 · XQ2 + Q1 · Q2 is outputted to the terminal XX. In this way, it is possible to obtain periodic pulse signals X and XX having a frequency twice that of the differential ring oscillation circuit 411.

  The terminal 410 is a terminal used to determine the operating speed of the exclusive OR circuit 406 by determining the operating current according to the voltage applied thereto. Usually, an applied voltage is selected and applied so that the exclusive OR circuit 406 can obtain a sufficient operation speed with appropriate energy efficiency. Further, the amplitude value of the signal output to the differential output pair can be determined by the voltage applied to the terminal 407. The smaller the amplitude value is, the higher the frequency can be made to operate. Therefore, an appropriate voltage value capable of obtaining a sufficient operation speed and an SN ratio is selected and applied to the terminal 407.

The output signal obtained by this application is a differential signal, and the differential signal is usually more convenient for such high frequency operation. Also, since the output periodic pulse signal has a high frequency, if the amplitude is too large, the possibility of interference with surrounding electronic circuits increases, so the amplitude value can be set to a certain level and can be set freely. Is convenient.
In the third embodiment, all the components can be integrated on the semiconductor integrated circuit, and the element area can be reduced. Therefore, the high-speed and high-performance semiconductor integrated circuit is not accompanied by a cost burden. Can be realized.

In particular, the element of the oscillation circuit has only one NMOS transistor and has a small load capacity so that it can oscillate at high speed and uses current mode logic that can operate at high speed. It is possible to operate at a frequency with a high performance limit and with low power consumption.
Therefore, it is possible to generate high-frequency high-precision pulses with a simple circuit. Since the amplitude value of the pulse signal to be output can be adjusted, it is particularly effective when using a high frequency.
(Fourth embodiment)
FIG. 6A is a circuit diagram showing the main part of the first periodic pulse generating circuit according to the fourth embodiment of the present invention, and FIG. 6B shows the main part of the second periodic pulse generating circuit. It is a circuit diagram.

  In the first to third embodiments described above, a ring oscillation circuit is used, and the oscillation frequency of the ring oscillation circuit is determined by the drive capability of the active elements constituting the circuit and the load capacitance connected thereto. In general, when a circuit is built on a semiconductor integrated circuit, the oscillation frequency varies greatly due to manufacturing variations in the semiconductor process. The circuit of the fourth embodiment is configured to match the frequency of the generated periodic pulse signal with the target frequency.

The first periodic pulse generation circuit in FIG. 6A has a configuration according to one method of matching the frequency of a generated signal to a target frequency using a phase locked loop.
In other words, reference numeral 610 denotes the circuit shown in the first to third embodiments, and includes a ring oscillation circuit 601 and a high frequency generation logic circuit 602 that generates a higher frequency signal from the output of the ring oscillation circuit 601. A control terminal 608 controls the oscillation frequency of the ring oscillation circuit 601 and corresponds to the terminal 404 of the third embodiment. Although the terminal corresponding to the control terminal is not shown in the first and second embodiments, a control element (transistor) for controlling the current flowing into the active element constituting the ring oscillation circuit is provided in the current closed loop. This terminal can be easily added by inserting it somewhere. In this way, the ring oscillation circuit 601 used in the periodic pulse generation circuit according to the present embodiment can be considered as a voltage controlled oscillation circuit.

  Therefore, the oscillation frequency can be set to a target frequency by the phase locked loop including the ring oscillation circuit 601. That is, the output of the ring oscillation circuit 601 is frequency-divided by an appropriate frequency dividing ratio by the frequency dividing circuit 603, and the frequency-divided signal is input to the terminal 607 by the phase comparison circuit 604. In comparison, the voltage output from the voltage generation circuit 605 and applied to the terminal 608 is controlled according to the phase comparison result. The voltage generation circuit 605 includes a charge pump and a low-pass filter.

  Note that the input of the frequency dividing circuit 603 may be taken from the output of the ring oscillation circuit 601 or may be taken from the output of the logic circuit 602 as indicated by a broken line. In the former case, the frequency dividing ratio can be reduced. However, in this embodiment, generally, a plurality of signal lines are connected from the ring oscillation circuit 601 to the logic circuit 602, and only one of them is used as the frequency dividing circuit. Since the connection is made, the load of each output line of the ring oscillation circuit 601 varies, and the duty ratio of the ring oscillation circuit 601 is likely to go wrong. In the latter case, the frequency to be frequency-divided by the frequency-dividing circuit 603 is close to the limit of its device performance for the purpose of this embodiment, but it is difficult to divide the frequency, but the above-mentioned difficulties are avoided. Both cases involve some difficulty but can be avoided by currently available techniques.

The second periodic pulse generation circuit shown in FIG. 6B has a configuration based on another method for adjusting the frequency of the generated signal to a target frequency using a phase locked loop.
Reference numeral 620 denotes a circuit shown in the first to third embodiments, and includes a ring oscillation circuit 611 and a high frequency generation logic circuit 612 that generates a higher frequency signal from the output of the ring oscillation circuit 611. Reference numeral 618 denotes a control terminal for controlling the oscillation frequency of the ring oscillation circuit 611, which corresponds to the terminal 404 of the circuit of the third embodiment. In the first and second embodiments, a terminal corresponding to the control terminal is not shown, but can be easily added by the method described above. Reference numeral 613 denotes a voltage controlled oscillation circuit, and this voltage controlled oscillation circuit 613, a frequency dividing circuit 614, a phase comparison circuit 615, a voltage generation circuit 616 including a charge pump and a low pass filter constitute a phase locked loop.

That is, the voltage controlled oscillation circuit 613 generates a voltage so that the phase is fixed to the reference frequency signal input to the terminal 617 and oscillates at the frequency of the frequency division ratio multiplied by the frequency dividing circuit 614 of the frequency of the reference frequency signal. It is controlled by the voltage generated by circuit 616.
Here, if it is assumed that the ring oscillation circuit 611 and the voltage controlled oscillation circuit 613 are the same circuit manufactured on the same semiconductor substrate, it is considered that their characteristics are uniform. When the same voltage is applied to the control terminal of the control oscillation circuit 613 and the control terminal 618 of the ring oscillation circuit 611, their oscillation frequencies coincide. That is, the ring oscillation circuit 611 oscillates at the oscillation frequency of the voltage-controlled oscillation circuit 613 when the phase is locked by the phase-locked loop, and the frequency accuracy of the generated signal of the periodic pulse generation circuit can be improved. .

  In the above description, the ring oscillation circuit 611 and the voltage controlled oscillation circuit 613 are the same circuit. However, the circuit may be different as long as the components (inverter circuit and the like) constituting these circuits are the same. That is, if the device performance is considered to be uniform by manufacturing on the same semiconductor chip and the performance of the two oscillation circuits 613 and 618 can be made similar to each other, it occurs. The frequency of the periodic pulse signal can be set as a target frequency.

  For example, the operation speed of the frequency dividing circuit 614 is lowered by lowering the oscillation frequency by making the voltage controlled oscillation circuit 613 a multistage ring oscillation circuit or by intentionally creating a circuit having a larger load capacity. In addition, the power consumption of the circuit can be reduced. In this way, the second periodic pulse generation circuit shown in FIG. 6B can eliminate the difficulties described with reference to the first periodic pulse generation circuit shown in FIG.

  With the configuration of the first or second periodic pulse generation circuit of the fourth embodiment, it is possible to generate a high-accuracy high-speed periodic pulse signal while suppressing manufacturing variations due to the semiconductor manufacturing process.

  The present invention has a great effect, for example, when it is realized at a low cost and in a small circuit area if the periodic pulse generation circuit is built on a semiconductor integrated circuit to be system-on-chip. The effect is particularly great in applications to communication systems that require high frequencies.

1 is a circuit diagram showing a main part of a periodic pulse generating circuit according to a first embodiment of the present invention. The time chart which shows typically operation | movement of the periodic pulse generation circuit of 1st Embodiment. The circuit diagram which shows the principal part of the periodic pulse generation circuit which concerns on 2nd Embodiment of this invention. The circuit diagram which shows the principal part of the periodic pulse generation circuit which concerns on 3rd Embodiment of this invention. The time chart which shows typically operation | movement of the periodic pulse generation circuit of 2nd Embodiment. The circuit diagram which shows the principal part of the periodic pulse generation circuit which concerns on 4th Embodiment of this invention. The circuit diagram which shows the principal part of the conventional 3 step | paragraph ring oscillation circuit. The time chart which shows typically the operation | movement of the conventional 3 step | paragraph ring oscillation circuit.

Explanation of symbols

  101, 102, 103, 301, 302, 303, 30n inverter circuit, 104, 105, 106, 113, 331, 332, 33n NAND circuit, 107, 340 NAND circuit, 403, 405 flip-flop circuit, 406 Exclusive OR circuit, 411, 601, 611 ring oscillation circuit, 602, 612 high frequency generation logic circuit, 604, 615 phase comparison circuit, 605, 616 voltage generation circuit, 613 voltage control oscillation circuit

Claims (8)

  An oscillation circuit that generates a periodic signal of n phases (n is an integer of 3 or more), n sets of AND circuits that extract a phase shift difference of each phase of the periodic signal, and output signals of the n sets of logic circuits A periodic pulse generation circuit comprising: an OR circuit for taking an OR.   The periodic pulse generation circuit according to claim 1, wherein the oscillation circuit is a ring oscillation circuit.   3. The periodic pulse according to claim 2, wherein the ring oscillation circuit has means for controlling an inflow current, and the oscillation frequency of the ring oscillation circuit can be varied in accordance with an input signal to the means. Generation circuit.   A periodic pulse generation circuit comprising: an oscillation circuit that generates two periodic signals having a phase difference of 90 degrees; and an exclusive OR circuit that performs an exclusive OR of the two signals.   5. The periodic pulse generation according to claim 4, wherein the oscillation circuit includes an inverter circuit configured of a CMOS current mode logic circuit, and the oscillation frequency can be varied by controlling an inflow current of the inverter circuit. circuit.   6. The periodic pulse according to claim 1, wherein any one of the logical product circuit, the logical sum circuit, and the exclusive logical sum circuit is configured by a CMOS current mode logic circuit. Generation circuit.   7. The ring oscillation circuit according to claim 3, wherein the ring oscillation circuit is included in a phase locked loop, and the phase locked loop is controlled to be phase-synchronized with a predetermined reference frequency signal. 8. Periodic pulse generator.   A second ring oscillation circuit configured by an element having characteristics similar to the ring oscillation circuit, and a second ring oscillation circuit including the second ring oscillation circuit and controlled to be phase-synchronized with a signal having a predetermined reference frequency. 7. The inflow current of the second ring oscillation circuit is controlled by phase synchronization control of the second phase locked loop. 8. The periodic pulse generation circuit described.

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