JP2002185317A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a low-jitter PLL circuit. SOLUTION: A reference frequency signal Fref is inputted to one input terminal of a phase comparator (PFD) 1, and the output signal Fvco of a voltage- controlled oscillator(VCO) 3 is inputted to another input terminal of the PFD 1. The output pulse of the PFD 1 is inputted to and integrated in a low-pass filter(LPF) 2. The output of the LPF 2 is inputted to the VCO 3. One output of the VCO 3 is inputted to the PFD 1 as the output signal Fvco, and another output of the VCO 3 is inputted to an N-multiplier 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a PLL (Phase Locked).
(Loop) circuit, and more particularly to an electronic circuit that requires a highly stable clock with low jitter.

[0002]

2. Description of the Related Art FIG. 11 is a block diagram showing an example of a conventional PLL circuit. The reference frequency signal Fref is input to one input of the phase comparator (PFD) 1 and the feedback signal Fout / M is input to the other input.
Is entered.

The phase comparator 1 outputs a signal corresponding to the phase difference between the reference frequency signal Fref and the feedback signal Fout / M.

If the phase of the feedback signal Fout / M lags behind the phase of the reference frequency signal Fref, the phase comparator
1 outputs a high-level pulse, and conversely, the feedback signal Fou
If the phase of t / M is ahead of the phase of the reference frequency signal Fref, the phase comparator 1 outputs a low-level pulse.

[0005] The output signal of the phase comparator 1 is input to a low-pass filter (LPF) 2 where it is integrated and converted to a direct current. When a high-level pulse is input, the output of the low-pass filter 2 is higher than in the previous state, and when a low-level pulse is input, the output of the low-pass filter 2 is lower than in the previous state.

[0006] The voltage controlled oscillator (VCO) 3 to which the output signal of the low-pass filter 2 is input has an oscillation frequency higher than the previous state when the input voltage increases, and the oscillation frequency increases when the input voltage decreases. Lower than before.

The output signal Fout of the voltage controlled oscillator 3 input to the M frequency divider 19 is frequency-divided by M, and the output signal Fout / M is fed back to the phase comparator 1.

The comparison between the two signals by the phase comparator 1 is performed at the frequency of Fref, and a pulse is output until the phase shift is eliminated. As a result, the voltage controlled oscillator 3 oscillates so that Fref and Fout / M become equal.

In this way, the output frequency of the PLL circuit becomes Fout = M × Fref, and M times the reference oscillation frequency is obtained.

[0010]

In the PLL circuit, switching noise of the logic circuit occurs, and as a result, noise of the frequency Fref, which is the operating frequency of the logic circuit, is added to the voltage controlled oscillator 3. Also, when the output pulse of the phase comparator 1 is not sufficiently smoothed by the low-pass filter 2, noise of the frequency Fref is added to the voltage controlled oscillator 3.

For this reason, the conventional PLL circuit has a problem that noise caused by a logic circuit adversely affects jitter.

Accordingly, it is an object of the present invention to solve the above-mentioned problems and to realize a low-jitter PLL circuit.

[0013]

According to the present invention, there is provided a phase comparator for comparing the phases of a reference frequency signal and a feedback signal and outputting an error signal in accordance with the difference, and integrating the error signal output from the phase comparator. A low-pass filter, and a ring-oscillator-type voltage-controlled oscillator composed of N inverter circuits that change the oscillation frequency according to the output of the low-pass filter, and the respective outputs of the N inverter circuits of the voltage-controlled oscillator. A PLL circuit comprising an N multiplier for combining and multiplying the oscillation frequency by N, wherein the feedback signal has the same frequency as the output signal of the voltage controlled oscillator.

The N multiplier inputs N different signals from the voltage controlled oscillator to N NAND circuits, and outputs the N NAND circuits.
It comprises at least one NAND circuit for synthesizing N signals output from the circuit, and outputs a frequency that is N times the oscillation frequency of the voltage controlled oscillator.

Alternatively, the N-multiplier has another configuration, in which N different signals are inputted from the voltage-controlled oscillator to N NOR circuits, and N signals outputted from the N NOR circuits are synthesized. And outputs a frequency which is N times the oscillation frequency of the voltage controlled oscillator.

According to the above configuration, even when noise generated from the logic circuit is applied to the voltage controlled oscillator, the output signal of the voltage controlled oscillator and the jitter of the N-multiplied signal do not increase.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing embodiments of the present invention, the nature of jitter will be described. Figure 10 shows the effect of noise applied to the voltage controlled oscillator on jitter.
The horizontal axis fm is the frequency of the noise, and the vertical axis P (fm) is the degree of influence on the jitter. Fvco indicates the oscillation frequency of the voltage controlled oscillator. FIG. 10 shows that the lower the frequency of the noise, the greater the effect on the jitter. If the frequency of the noise is equal to or an integral multiple of the oscillation frequency of the voltage controlled oscillator, it indicates that the noise at that frequency does not affect the jitter.

Normally, a logic circuit in a PLL circuit operates at a reference frequency, so that noise generated by the logic circuit also has a component of the reference frequency. In the related art, since the M frequency divider is used in the PLL circuit to obtain the multiplication of the reference frequency by M, the logic circuit operates at a frequency M times smaller than the oscillation frequency of the voltage controlled oscillator. For this reason, the noise generated by the logic circuit is also in the range of 0 [Hz] to Fvco [Hz], and greatly affects the jitter as shown in FIG.

FIG. 1 is a block diagram showing an embodiment of the present invention. The reference frequency signal Fref is input to one input terminal of the phase comparator (PFD) 1 and the output signal Fvco of the voltage controlled oscillator (VCO) 3 is input to the other terminal. Phase comparator 1
Are input to a low-pass filter (LPF) 2 and integrated. The control voltage Vc output from the low-pass filter 2 is input to the voltage controlled oscillator 3. One of the outputs of the voltage controlled oscillator 3 is input to the phase comparator 1 as Fvco, and the other signal is input to the N multiplier 4.

With this configuration, the frequency at which the logic circuit operates and the oscillation frequency of the voltage-controlled oscillator 3 become equal, so that noise does not affect jitter.

FIG. 2 shows the voltage controlled oscillator 3 and the N multiplier of FIG.
As an example of 4, a three-stage ring oscillator and a tripler are shown. This three-stage ring oscillator has inverter circuit 5,
It is configured by connecting 6, 7 in a ring shape, and the frequency changes according to the control voltage Vc. The signal input to the inverter circuit 5 is s1, the signal input to the inverter circuit 6 is s2, and the signal input to the inverter circuit 7 is s3. S1 and S2 are input to the NAND circuit 8, and the output is t1. Similarly, the signals s2 and s3 are input to the NAND circuit 9 and the output is t2, and the signals s3 and s1 are input to the NAND circuit 10 and the output is t3. The outputs t1, t2, and t3 of the NAND circuits 8, 9, and 10 are input to a three-input NAND circuit 11. The output of the NAND circuit 11 has three times the frequency of the signal Fvco of the voltage controlled oscillator 3.

FIG. 4 is a timing chart of the voltage controlled oscillator 3 and the tripler. The signals s1, s2, and s3 are signals input to the inverter circuits 5, 6, and 7, respectively, and their phases are delayed by p / 3 and inverted by passing through each inverter circuit. The signals s1, s2, and s3 are calculated by the NAND circuits 8, 9, and 10, and output as signals t1, t2, and t3. Further signal
Input t1, t2, t3 to NAND circuit 11 to output 3 × Fvco
Is obtained.

At this time, in addition to using the normal circuit configuration as the NAND circuits 8, 9, and 10, the configuration shown in FIG.
By using the configuration shown in FIG. 7, the timing of switching can be made uniform, the timing skew between signals can be eliminated, and a more accurate signal can be obtained. Figure 6
Are p-channel MOS transistors P1, P2 and n-channel MOS transistors N1 to N, where A and B are inputs and X is an output.
FIG. 7 shows a NAND circuit including N4. FIG. 7 shows p-channel MOS transistors P3 to P in which A, B, and C are inputs and X is an output.
NAND including 5 and n-channel MOS transistors N5 to N13
The circuit is shown.

Although an example of the case where N = 3 has been described above, the configuration shown in FIG. 6 can be used for a general N circuit for inputting a signal of an inverter circuit constituting a ring oscillator. For a NAND circuit that combines the outputs of the NAND circuits, it is necessary to reduce the number of inputs to N for general N.

Also, generally, the output of the inverter circuit 7 is input to the buffer inverter circuit 12, and the signal Fvco fed back to the phase comparator 1 is obtained as the output. The dummy buffer inverter circuit 12 is connected, and the dummy buffer inverter circuit 13 is connected to the output of the inverter circuit 6 to make the load of each node of the ring oscillator uniform, so that a highly accurate signal with less jitter can be obtained. can get.

FIG. 3 shows the voltage controlled oscillator 3 and the N multiplier of FIG.
4 shows another example of the configuration of 4 (N = 3). The same parts as those in the circuit of FIG. 2 are denoted by the same reference numerals. The difference from FIG. 2 is the configuration of the N multiplier 4.
Use R circuit.

The signal input to the inverter circuit 5 is s1, the signal input to the inverter circuit 6 is s2, and the signal input to the inverter circuit 7 is s3. NOR circuit for s1 and s2
15 and the output is t4. Similarly, the signals s2 and s3
Input to the NOR circuit 16, the output is t5, and the signals s3 and s1 are N
The signal is input to the OR circuit 17, and the output is t6. NOR circuit 15, 1
The outputs t4, t5, t6 of 6, 17 are input to a three-input NOR circuit 18. The output of the NOR circuit 18 is the signal Fvco 3 of the voltage controlled oscillator 3
Double the frequency.

FIG. 5 shows a timing chart of the voltage controlled oscillator 3 and the tripler. The signals s1, s2, and s3 are signals input to the inverter circuits 5, 6, and 7, respectively, and their phases are delayed by p / 3 and inverted by passing through each inverter circuit. The signals s1, s2, and s3 are calculated by NOR circuits 15, 16, and 17 and output as signals t4, t5, and t6. Further, by inputting the signals t4, t5, t6 to the NAND circuit 18, the output 3 × Fvc
o is obtained.

At this time, the configuration shown in FIG. 8 is used in addition to the normal circuit configuration as the NOR circuits 15, 16, and 17, and the configuration shown in FIG. By using this, the switching timing can be made uniform, the timing skew between signals can be eliminated, and a more accurate signal can be obtained. Figure
8 is a p-channel MOS transistor P6 to P9 and an n-channel MOS transistor N1 in which A and B are inputs and X is an output.
FIG. 9 shows a p-channel MOS transistor P in which A, B, and C are inputs and X is an output.
5 shows a NOR circuit including 10 to P18 and n-channel MOS transistors N16 to N18.

Although an example of the case where N = 3 has been described above, the configuration of FIG. 8 can also be used for a general NOR circuit that inputs a signal of an inverter circuit constituting a ring oscillator. For a NOR circuit that combines the outputs of the NOR circuits, it is necessary to reduce the number of inputs to N for general N.

Voltage controlled oscillator using ring oscillator
3 and the configuration of the output buffer are the same as in FIG.

[0032]

As described above, according to the PLL circuit of the present invention, the oscillation frequency of the voltage controlled oscillator and the frequency of the reference frequency signal become equal, so that the noise generated by the logic circuit does not increase the jitter.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a PLL circuit of the present invention.

FIG. 2 is a diagram showing a multiplier using a voltage controlled oscillator and a NAND circuit.

FIG. 3 is a diagram showing a multiplier using a voltage controlled oscillator and a NOR circuit.

FIG. 4 is a timing chart of a multiplier using a voltage controlled oscillator and a NAND circuit.

FIG. 5 is a timing chart of a multiplier using a voltage controlled oscillator and a NOR circuit.

FIG. 6 is a diagram showing a two-input NAND circuit.

FIG. 7 is a diagram showing a three-input NAND circuit.

FIG. 8 is a diagram showing a three-input NOR circuit.

FIG. 9 is a diagram showing a three-input NOR circuit.

FIG. 10 is a diagram showing the degree of influence of noise on jitter.

FIG. 11 is a block diagram showing a conventional PLL circuit.

[Explanation of symbols]

 1: Phase comparator (PFD) 2: Low-pass filter (LPF) 3: Voltage controlled oscillator (VCO) 4: N multiplier 5-7, 12-14: Inverter 8-10: 2-input NAND circuit 11: 3 Input NAND circuit 15-18: 2-input NOR circuit 18: 3-input NOR circuit 19: M frequency divider P1-P18: p-channel MOS transistor N1-N18: n-channel MOS transistor

Claims (3)

[Claims] A phase comparator for comparing the phases of a reference frequency signal and a feedback signal and outputting an error signal according to the difference; a low-pass filter for integrating the error signal output from the phase comparator; The output of the low-pass filter changes the oscillation frequency, and the ring oscillator type voltage-controlled oscillator composed of N inverter circuits, and the respective outputs of the N inverter circuits of the voltage-controlled oscillator are combined to multiply the oscillation frequency by N. A PLL circuit comprising: an N-frequency multiplier; and wherein the feedback signal has the same frequency as an output signal of the voltage-controlled oscillator. 2. The N multiplier inputs N different signals from the voltage controlled oscillator to N NAND circuits, and outputs the N NAND circuits.
2. The PLL circuit according to claim 1, comprising at least one NAND circuit that combines N signals output from the circuit. 3. The N multiplier inputs at least N different signals from the voltage controlled oscillator to N NOR circuits, and synthesizes at least one of the N signals output from the N NOR circuits.
2. The circuit according to claim 1, wherein the circuit comprises a NOR circuit.
PLL circuit.