JP2541313B2 - Dual PLL device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is used in a frequency synthesizer and includes a PLL.
The present invention relates to a paired dual PLL device.

[Prior Art] Conventionally, in a dual PLL device of this type, as shown in FIG. 3, a voltage controlled oscillator (VCO) is used.
d Oscillater) The divided output b of the output frequency divider 1 is input to one input end of the phase frequency comparator 2, and the reference clock c of the reference clock generator 9 is input to the other input end of the phase frequency comparator 2. To be done. The output of the phase frequency comparator 2 is input to the loop filter 3, and the output of the loop filter 3 is VCO4.
Is input to The VCO 4 outputs the VCO oscillation output a, and the VCO output frequency divider 1, the phase frequency comparator 2, the loop filter 3 and the VCO 4 constitute a first PLL. The second PLL is also composed of a VCO output frequency divider 5, a phase frequency comparator 6, a loop filter 7 and a VCO 8. Note that d is a frequency division output, and e is a VCO oscillation output. The reference clock c, which is the output of the reference clock generator 9, is commonly input to the phase frequency comparators 2 and 6.

[Problems to be Solved by the Invention] In the conventional dual PLL device described above, the same reference clock c is input from the common reference clock generator 9 to the reference clock inputs of the two phase frequency comparators 2 and 6. Therefore, the logic circuits of the phase frequency comparators 2 and 6 operate at the same timing.

In the PLL, when the loop is locked, that is, when the phase difference between the two input signals of the phase frequency comparators 2 and 6 is almost zero, the operation of the phase frequency comparators 2 and 6 is logical level (digital ), Not the analog amount.

On the other hand, in recent years, in high-speed logic circuits, malfunction of the circuit due to noise during switching operation has been taken up as a problem, but the above-mentioned phase frequency comparators 2 and 6 are no exception, and logic level operation itself is necessary. Affect analog behavior. In other words, the phase frequency comparator can be considered as a circuit in which feedback is applied from the input to the output, which consists of a flip-flop (FF) and a gate circuit, and the phases of the two comparison inputs of the phase frequency comparators 2 and 6 are substantially the same. Match each other, PLL
Phase frequency comparator 2,6
Then, the total delay amount of the feedback circuit controls the analog amount of the output. For this reason, when the gates are operated simultaneously by the comparison input signal, the power supply potential and the ground potential fluctuate due to a large rush current, and the threshold value of the gate circuit fluctuates. In this state, this fluctuation component is no longer included in the delay time. This deteriorates the side rope characteristic according to the phase jitter and the cycle of the reference clock. Dual PL
In the L device, if the reference clocks of the two phase frequency comparators are the same, inrush currents are generated at the same timing, so the mutual interference error increases and the phase jitter and side rope characteristics deteriorate further. is there.

The present invention has been made in view of such problems, and it is possible to eliminate the interference between the phase frequency comparators, and to achieve the phase jitter characteristic and the side rope characteristic with a single PL.
An object of the present invention is to provide a dual PLL circuit that can have the same characteristics as in the case of L.

[Means for Solving the Problems] A dual PLL device according to the present invention has a common reference clock generator and first and second PLLs. First PLL
Is a first phase frequency comparator to which the reference clock from the reference clock generator is input, and a first loop filter to which the output of the first phase frequency comparator is input,
The voltage-controlled oscillator receives the output of the first loop filter. The second PLL includes a delay circuit to which the reference clock from the reference clock generator is input, a second phase frequency comparator to which the output of the delay circuit is input, and a second phase frequency comparison. And a second voltage controlled oscillator to which the output of the second loop filter is input. Then, the output of the reference clock generator is supplied to the second phase frequency comparator of the second PLL through the delay circuit, and the output of the first phase frequency comparator of the first PLL is delayed. The feature is that it is directly supplied without passing through a circuit.

[Operation] In the present invention, since the delay circuit is provided in the preceding stage of the second phase comparator, it is possible to prevent the two phase frequency comparators from operating simultaneously. This makes it possible to eliminate mutual interference between the phase frequency comparators with a very simple configuration in which only a delay circuit is added.

[Embodiment] Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a dual PLL according to the first embodiment of the present invention. In FIG. 1, the same parts as those in FIG. 4 are designated by the same reference numerals. VCO output divider 1 is VCO4
The oscillation output a is input, and the frequency division output b is output. The phase frequency comparator 2 has two comparison signal inputs, one of which is obtained from the divided output b and the other of which is obtained from the reference clock c of the reference clock generator 9, and the phase error output is output to the loop filter 3. To do. The output of the loop filter 3 is given to VCO4 as a tuning voltage for the oscillation frequency of VCO4.
In this way, the VCO output frequency divider 1, the phase frequency comparator 2, the loop filter 3 and the VCO 4 constitute a first PLL.

Further, the VCO output frequency divider 5 receives the oscillation output e of the VCO 8 and outputs the frequency division output d. The phase frequency comparator 6 has two comparison signal inputs, one of which is obtained from the frequency division output d,
It is obtained from the delay circuit output f of the other delay circuit 10 and outputs the phase error output to the loop filter 8. The output of the loop filter 7 is given to VCO8 as a tuning voltage of the oscillation frequency of VCO8. In this way, the VCO output frequency divider 5, the phase frequency comparator 6, the loop filter 7, the VCO 8 and the delay circuit 10 constitute a second PLL.

The reference clock generator 9 outputs the reference clock c commonly to the reference side comparison signal input section of the phase frequency comparator 2 and the delay circuit 10.

Next, the operation of the dual PLL thus configured will be described. The reference clock generator 9 has a reference clock c.
Is directly input to the first phase frequency comparator 2 and
The signal is input to the phase frequency comparator 6 after being delayed by the delay circuit 10. Therefore, the phase frequency comparators 2 and 6 are
The divided outputs b and d of the CO output dividers 1 and 5 and the reference clock are compared at mutually different timings.

The analog operation of the outputs of the phase frequency comparators 2 and 6 poses a problem in the vicinity where the phases of the two comparison signals match. In addition, in the operation of the phase frequency comparators 2 and 6 at that time, a large amount of inrush current flows because all the gates operate simultaneously, and the ground potential and the power supply potential fluctuate. In the dual PLL device, when this phenomenon occurs at the same time for the two phase frequency comparators 2 and 6, mutual interference causes further deterioration. FIG. 5 is a diagram showing a VCO oscillation output frequency spectrum of a conventional dual PLL device. As shown in FIG. 5, in the oscillation output, the sidebands of the side rope are conspicuous and the phase jitter becomes large.

On the other hand, in this embodiment, as shown in FIG. 1, by providing the delay circuit 10 in the preceding stage of the reference clock input section of one phase frequency comparator 6, two phase frequency comparators 2, 6 are The simultaneous operation is prevented. As a result, deterioration due to mutual interference can be eliminated. FIG. 4 is a diagram showing a VCO oscillation frequency spectrum in the dual PLL device of this embodiment. It can be seen that the oscillation output shown in FIG. 3 has a lower sideband level than the oscillation output shown in FIG. In the case of this embodiment,
The phase jitter is also improved.

FIG. 2 is a block diagram showing a second embodiment of the present invention. In this embodiment, an inverter circuit 11 is connected instead of the delay circuit 10 in the first embodiment shown in FIG. Also in this embodiment, the second phase frequency comparator 6
The reference clock input to the first phase frequency comparator 2 is delayed by the inverter circuit 11 as compared with the reference clock input to the first phase frequency comparator 2, and the same effect as that of the first embodiment is obtained.

As described above, according to the present invention, in the dual PLL device, when the reference clocks of the two phase frequency comparators are obtained from the same reference clock generator, the reference clock input of one phase frequency comparator is input. Since the output of the reference clock generator is delayed by providing the delay circuit in the preceding stage and then input to the one phase frequency comparator, the two phase frequency comparisons are made by a simple configuration only by adding the delay circuit. It is possible to improve the phase jitter and side rope characteristics, which increase due to the mutual interference of the devices, to the same level as the single PLL.

The present invention has an extremely excellent effect that mutual interference can be suppressed particularly when the dual PLL device is made into one chip.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a dual PLL device according to the first embodiment of the present invention, FIG. 2 is a circuit diagram showing a dual PLL device according to the second embodiment of the present invention, and FIG. FIG. 4 is a frequency spectrum diagram of VCO oscillation output showing the effect of FIG. 4, FIG. 4 is a block diagram showing a conventional dual PL device, and FIG. 5 is a diagram showing a frequency spectrum of VCO oscillation output in the conventional dual PLL device. 1,5; VCO output divider, 2,6; phase frequency comparator, 3,7; loop filter, 4,8; VCO, 9; reference clock generator, 10; delay circuit, 11; inverter circuit, a ; VCO4 oscillation output, b; VCO frequency divider 1 frequency division output, c; Reference clock generator 9 output for reference clock, d; VCO frequency divider 5 frequency division output, e; VCO8 oscillation output, f: Delay circuit output of delay circuit 10 (or inverter circuit 11)

Claims (1)

(57) [Claims] 1. A common reference clock generator, a first phase frequency comparator to which a reference clock from the reference clock generator is input, and a first phase frequency comparator to which an output of the first phase frequency comparator is input. Of the first loop filter and a voltage controlled oscillator to which the output of the first loop filter is input, a delay circuit to which the reference clock from the reference clock generator is input, and a delay circuit of the delay circuit. A second phase frequency comparator to which the output is input, a second loop filter to which the output of the second phase frequency comparator is input, and a second voltage to which the output of the second loop filter is input A second PLL composed of a controlled oscillator, the output of the reference clock generator being the second of the second PLL.
To the phase frequency comparator of the above through the delay circuit,
A dual PLL characterized in that it is directly supplied to the first phase frequency comparator of the first PLL without passing through the delay circuit.
apparatus.