JP2011034470A - Semiconductor integrated circuit and clock control method for the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of a conventional semiconductor integrated circuits that cannot reduce the peak current effectively. <P>SOLUTION: A semiconductor integrated circuit includes a clock generation circuit, a module 7 that operates based on a clock generated by the clock generation circuit, and a module 8 that operates based on the clock generated by the clock generation circuit for data transfer with the module 7. The clocks supplied to the module 7 and module 8 are out of phase according to the number of delay elements inserted in a clock path between the module 7 and the clock generation circuit and the number of delay elements inserted in a clock path between the module 8 and the clock generation circuit. The circuit configuration can reduce the peak current effectively. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit and a clock control method thereof, and more particularly to a semiconductor integrated circuit suitable for reducing a peak current and a clock control method thereof.

  In the conventional LSI (Large Scale Integration) design, the phases of clocks supplied to a plurality of modules are generally adjusted so as to coincide with each other. That is, the phases of clocks supplied to a plurality of FFs (flip-flops) provided in these modules are adjusted so as to match each other. For this reason, much of the power consumed by the LSI is consumed immediately after the clock edge. Therefore, the peak value of the power supply current (hereinafter simply referred to as peak current) is considerably larger than the average current. As a result, a voltage drop due to the resistance of the power supply wiring inside the LSI may occur, which may cause a malfunction of the circuit and a decrease in the operation speed. In addition, when the peak current is large, EMI (Electromagnetic Interference) noise also increases, and there is a concern about the influence on the outside of the LSI.

  A solution to such a problem is disclosed in Patent Document 1. The semiconductor device described in Patent Document 1 includes a clock supply unit that supplies a plurality of clocks, and a plurality of modules that are arranged on a substrate and operate in synchronization with the plurality of clocks. The clock supply means matches the phases of the clocks when data is transferred between modules to be transferred, and provides a phase difference between the clocks when data is not transferred. Thereby, the malfunction is suppressed and the peak current is suppressed.

  Here, in the technique described in Patent Document 1, when data transfer between modules to be data transferred is not performed, a phase difference is provided between the clocks. However, when transferring data, the phases of the clocks are matched. Therefore, there is a problem that the peak current becomes large during data transfer.

  Another solution is disclosed in Patent Document 2. An ASIC (Application Specific Integrated Circuit) described in Patent Document 2 includes a plurality of blocks that are driven by at least the same clock in a circuit constituting a one-chip ASIC. Then, the delay of the clock from the clock input terminal of the ASIC to the clock input terminal of each block is adjusted by changing the dimensions (gate width, gate length) of the clock buffer inserted therebetween. As a result, the propagation delay of the clock supplied from the clock input terminal of the ASIC to each block is made different. Further, based on the result, block layout and wiring are performed. This prevents excessive current concentration due to the clock. That is, the peak current is suppressed.

JP 2008-102797 A JP 2006-165099 A

  As described above, in the technique described in Patent Document 2, the clock delay is adjusted by changing the dimension of the clock buffer. However, the change in the dimension of the clock buffer has a problem that it is difficult to know how much delay is added to the clock and it is difficult to adjust the delay with high accuracy.

  A semiconductor integrated circuit according to the present invention operates based on a clock generation circuit, a first module that operates based on a clock generated by the clock generation circuit, and a clock generated by the clock generation circuit, A second module for transferring data to and from the first module, the number of delay elements inserted on a clock path between the first module and the clock generation circuit, and the second module The phases of clocks supplied to the first and second modules are different based on the number of delay elements inserted on the clock path between the two modules and the clock generation circuit.

In addition, a clock control method for a semiconductor integrated circuit according to the present invention includes a clock generation circuit, a first module that operates based on a clock generated by the clock generation circuit, and a clock generated by the clock generation circuit. A semiconductor integrated circuit clock control method comprising: a second module that operates based on the second module for transferring data to and from the first module;
The number of delay elements inserted on the clock path between the first module and the clock generation circuit, and the delay element inserted on the clock path between the second module and the clock generation circuit And the phase of the clock supplied to the first and second modules is adjusted to be different from each other.

  The peak current can be effectively suppressed by the circuit configuration and the clock control method as described above.

  According to the present invention, it is possible to provide a semiconductor integrated circuit capable of effectively reducing a peak current and a clock control method thereof.

It is a flowchart which shows the clock control method concerning Embodiment 1 of this invention. It is a block diagram of a semiconductor integrated circuit before clock control. It is a block diagram of the semiconductor integrated circuit using the clock control method of a prior art. 1 is a block diagram of a semiconductor integrated circuit using a clock control method according to a first embodiment of the present invention. 1 is a block diagram of a semiconductor integrated circuit using a clock control method according to a first embodiment of the present invention. 1 is a block diagram of a semiconductor integrated circuit using a clock control method according to a first embodiment of the present invention. It is a figure which shows a clock waveform. It is a figure which shows a clock waveform.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. For clarity of explanation, duplicate explanation is omitted as necessary.

Embodiment 1
Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a flowchart of a clock control method for a semiconductor integrated circuit according to the first embodiment of the present invention. 2 to 6 are block diagrams of a semiconductor integrated circuit using the clock control method according to the first embodiment of the present invention. In the present embodiment, the circuits shown in FIGS. 2 to 6 will be described with reference to the flowchart shown in FIG.

  The circuit shown in FIG. 2 includes a clock generation circuit (not shown), modules 7 and 8, and combinational logic circuits 51 to 53. The modules 7 and 8 operate based on the clock generated from the clock generation circuit. Data transfer is performed between the module 7 and the module 8.

  The module 7 includes flip-flops (hereinafter simply referred to as FF) 1, 3, and 5. The module 8 includes FFs 2, 4, and 6. In the example of the circuit illustrated in FIG. 2, the FF 1 transmits data to the FF 2 via the combinational logic circuit 51. The FF 3 transmits data to the FF 4 via the combinational logic circuit 52. The FF 6 transmits data to the FF 5 via the combinational logic circuit 53. Each of the FF1 to FF6 operates based on the clock generated from the clock generation circuit.

  Note that the circuit shown in FIG. 2 is a circuit before CTS (clock tree synthesis) is executed. That is, the circuit shown in FIG. 2 is a circuit before a delay element such as a clock buffer is inserted into the clock supplied to the module 7 and the module 8. In other words, the circuit shown in FIG. 2 is a circuit before control so that data transfer between the module 7 and the module 8 is performed correctly.

  The circuit shown in FIG. 3 is a diagram after performing CTS on the modules 7 and 8 of the circuit shown in FIG. 2 (S100 in FIG. 1). The circuit shown in FIG. 3 further includes buffers 9, 10, and 11 as compared with the circuit shown in FIG. The buffer 10 is inserted on a clock path between a clock generation circuit (not shown) and the module 7. The buffer 11 is inserted on a clock path between the clock generation circuit and the module 8. The buffer 9 is inserted on a common clock path between the clock generation circuit and the modules 7 and 8. With such a circuit configuration, the phases of the clocks supplied to the module 7 and the module 8 are adjusted so as to substantially match as shown in FIG. The buffers 9 to 11 are clock buffers inserted on the clock path, and are delay elements that add a predetermined delay to the clock.

  The circuit shown in FIG. 4 is an example in which clock buffers (delay elements) 12 and 13 are further inserted on the clock path between the module 8 and the clock generation circuit in the circuit shown in FIG. 3 (S101 in FIG. 1). ). In the circuit shown in FIG. 4, for example, the number of clock buffers (12, 13) based on the frequency of the clock (clock supplied to the module 8) generated by the clock generation circuit is inserted on the clock path. As a result, as shown in FIG. 8, the clock supplied to the module 7 and the clock supplied to the module 8 are adjusted so as to have different phases.

  That is, the module is based on the number of buffers inserted on the clock path between the module 7 and the clock generation circuit and the number of buffers inserted on the clock path between the module 8 and the clock generation circuit. The phase of the clock supplied to 7 and 8 is adjusted to be different. As described above, the semiconductor integrated circuit according to the present embodiment can suppress the peak current by adjusting the clocks supplied to the modules to have different phases.

  In the circuit shown in FIG. 4, after the clock buffers 12 and 13 are inserted, it is determined whether or not a constraint condition for correctly performing data transfer between the module 7 and the module 8 is satisfied (FIG. 1). S102). This constraint condition is a condition that allows the receiving side FF to receive the data transmitted by the transmitting side FF in synchronization with the clock in synchronization with the next clock. This constraint condition includes so-called setup constraints, hold constraints, and the like. In the following description, the above-described constraint conditions are simply referred to as “constraint conditions” unless otherwise specified.

  If any of the data transfers between the FFs does not satisfy the constraint condition (NO in S102 in FIG. 1), the constraint condition is compared with the actual data transfer result to satisfy the constraint condition. Necessary delay information (constraint violation delay information; biolated delay difference) is calculated (S103 in FIG. 1). Based on the comparison result, the phase of the clock supplied to the FF that violated the constraint is adjusted (S104 in FIG. 1). For example, the clock phase is adjusted by inserting a clock buffer (intra-module delay element) for the clock supplied to the FF that violates the constraint.

  On the other hand, when all of the data transfers between the FFs satisfy the constraint conditions (YES in S102 of FIG. 1), the clock control of the semiconductor integrated circuit ends.

  The circuit shown in FIG. 5 is an example in which a clock buffer (intra-module delay element) 14 is inserted with respect to the clock supplied to FF1 of the circuit shown in FIG. 4 (S103, S104 in FIG. 1). That is, the circuit shown in FIG. 5 adjusts the phase of the clock supplied to FF1 so that the constraint condition is satisfied in the data transfer between FF1 and FF2 that do not satisfy the constraint condition. With such a circuit configuration, the phase of the clock supplied to the modules 7 and 8 is adjusted to be different based on the number of delay elements inserted on the clock path, and the clock between the FFs that does not satisfy the constraint condition is adjusted. Only the phase can be adjusted. As a result, accurate data transfer is possible and peak current can be suppressed.

  As described above, the semiconductor integrated circuit and the clock control method thereof according to the embodiment of the present invention, the number of delay elements inserted on the clock path between the module 7 and the clock generation circuit, the module 8 and the clock generation The phase of the clock supplied to each module differs based on the number of delay elements inserted on the clock path to the circuit. Such a circuit configuration can effectively suppress the peak current.

  In the technology described in Patent Document 2, the clock supplied to each module is adjusted to have a different phase by changing the dimension of the clock buffer inserted with respect to the clock supplied to each module. Was. Therefore, it is difficult to know how much delay is added to the clock, and there is a problem that it is difficult to adjust the delay with high accuracy. On the other hand, in the present embodiment, the clocks supplied to the respective modules are adjusted based on the number of clock buffers inserted with respect to the clocks supplied to the respective modules so as to have different phases. That is, in the present embodiment, unlike the prior art, the delay added to the clock is adjusted according to the number of clock buffers, so that the delay amount given to the clock can be easily adjusted.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, in the above embodiment, the case where the clock buffer 14 is inserted on the clock path of the FF 1 provided in the module 7 has been described as an example, but the present invention is not limited to this. For example, an intra-module delay element such as a clock buffer can be inserted on the FF clock path provided in the module 8 in order to satisfy the constraint conditions.

  Also, as shown in FIG. 6, the common clocks supplied to FF4 and FF6 are such that both the data transfer between FF3 and FF4 and the data transfer between FF6 and FF5 satisfy the constraint conditions. It is also possible to insert a clock buffer (intra-module delay element) 15 on the clock path.

  In the above-described embodiment, the case where the clock buffers 12 and 13 are inserted to adjust the phases of the clocks supplied to the modules 7 and 8 is described as an example. However, the present invention is not limited to this. For example, based on the number of delay elements inserted on the clock path between each module and the clock generation circuit, the phase of the clock supplied to each module is adjusted to be different, and the data between the modules is also adjusted. It is also possible to adjust the transfer to meet the constraint conditions.

  In addition, each delay element inserted on the clock path can be appropriately changed to a circuit configuration in which the transistor sizes are substantially the same. This further facilitates adjustment of the delay amount given to the clock.

DESCRIPTION OF SYMBOLS 1 Flip-flop 2 Flip-flop 3 Flip-flop 4 Flip-flop 5 Flip-flop 6 Flip-flop 7 Module 8 Module 9 Clock buffer 10 Clock buffer 11 Clock buffer 12 Clock buffer 13 Clock buffer 14 Clock buffer 15 Clock buffer 51 Combination logic circuit 52 Combination logic Circuit 53 Combinational logic circuit

Claims (6)

A clock generation circuit;
A first module that operates based on a clock generated by the clock generation circuit;
A second module that operates based on a clock generated by the clock generation circuit and performs data transfer with the first module;
The number of delay elements inserted on the clock path between the first module and the clock generation circuit, and the delay element inserted on the clock path between the second module and the clock generation circuit And a phase of a clock supplied to the first and second modules based on the number of the semiconductor integrated circuits. The first and second modules comprise a plurality of flip-flops,
The semiconductor integrated circuit according to claim 1, further comprising an in-module delay element that adjusts a phase of a clock supplied to a predetermined flip-flop among the plurality of flip-flops. Each of the delay elements is
3. The semiconductor integrated circuit according to claim 1, wherein the transistor sizes are substantially the same. Data generated between the clock generation circuit, the first module that operates based on the clock generated by the clock generation circuit, and the clock that is generated based on the clock generated by the clock generation circuit A second module for performing transfer, and a clock control method for a semiconductor integrated circuit comprising:
The number of delay elements inserted on the clock path between the first module and the clock generation circuit, and the delay element inserted on the clock path between the second module and the clock generation circuit And a clock control method for a semiconductor integrated circuit, wherein a phase of a clock supplied to the first and second modules is adjusted to be different based on the number of the first and second modules.   5. The clock of a semiconductor integrated circuit according to claim 4, wherein a phase of a clock supplied to a predetermined flip-flop among the plurality of flip-flops provided in the first and second modules is adjusted by an in-module delay element. Control method.   6. The clock control method for a semiconductor integrated circuit according to claim 4, wherein the transistor sizes of the delay elements are substantially the same.

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