JP2003228548A - Data transfer system and semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a development period of a data transfer system. <P>SOLUTION: A phase adjustment circuit (12) generates a second clock signal (CKIO'), whose phase is delayed than a first clock signal (CKIO), by delaying the first clock signal (CKIO) for prescribed time based on information on delay time set up by a setting means of the delay time. The development period of a data processing device (8) is shortened by allowing phase difference between the first clock signal and the second clock signal to be changeable by changing setting contents of the setting means of the delay time, and by dispensing with reflecting information on phase design in a total system including a peripheral circuit to design of hardware of an external device. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer technique, for example, a technique effectively applied to a microcomputer as an example of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a data processing apparatus equipped with a microcomputer, a memory and an external device capable of taking in data stored in the memory are provided as peripheral circuits of the microcomputer.
In addition to the central processing unit (CPU), the microcomputer includes a DMAC (Direct Memory Access Controller) for controlling DMA (Direct Memory Access) transfer. DM as an example of DMA transfer
There is A single address data transfer, which is done as follows.

First, a DMA request signal is asserted from an external device to the microcomputer.
When this request signal is accepted by the microcomputer, a DMA acknowledge signal is asserted to the external device, and DMA transfer from the memory to the external device is performed under the control of the DMAC.

As an example of the document describing the DMA transfer, there is JP-A-2001-209609.

[0005]

In the DMA single address data transfer, the data transferred from the memory to the external device is delayed, and the setup time becomes shorter as the operating frequency of the microcomputer becomes higher. Therefore, the data transmitted from the memory may not be captured by the external device. For this reason, conventionally, the phase design is performed in a total system including peripheral circuits for each data processing device, and the information is reflected in the hardware design of the external device.

However, it has been found by the inventor of the present application that it takes a long time to deal with the above-mentioned data delay by the hardware design, so that the development period of the data processing device may be lengthened. Further, in the method of reflecting the phase design information for each data processing device in the design of the external device, if part of the device mounted in the data processing device is changed, the phase design in the data processing device must be redone. Sometimes.

An object of the present invention is to provide a technique for shortening the development period of a data transfer system.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, the first clock generator for generating the first clock signal, the delay time setting means capable of setting the delay time information, and the delay time information set in the delay time setting means. A phase adjustment circuit for generating a second clock signal having a phase delayed from that of the first clock signal by delaying the first clock signal by a predetermined time, and a first clock signal operated by the first clock signal.
A second device that enables data to be exchanged between the device and the first device; and the phase adjustment circuit as an operation clock signal of the second device in data transfer from the first device to the second device. And a data transfer control unit using the second clock signal obtained by the above-mentioned method, to form a data transfer system.

According to the above means, the phase adjusting circuit delays the first clock signal for a predetermined time based on the delay time information set in the delay time setting means,
A second clock signal whose phase is later than that of the first clock signal is generated. By changing the setting content of the delay time setting means, the phase difference between the first clock signal and the second clock signal can be changed. In the method of designing the phase in the total system including peripheral circuits for each data processing device and reflecting the information in the hardware design of the external device, it takes time to deal with the data delay in the hardware design. Although the system development period may become long, the phase difference between the first clock signal and the second clock signal can be changed by changing the setting contents of the delay time setting means as described above. Therefore, it is not necessary to deal with the data delay in the hardware design, which shortens the development period of the data transfer system.

Further, by delaying the first clock signal for generating a first clock signal and the first clock signal for a predetermined time, the second clock signal whose phase is delayed from the first clock signal is generated. A phase adjusting circuit for generating the first clock signal, a first device operated by the first clock signal, a second device capable of exchanging data with the first device, and the first device to the first device. When a data transfer system is configured to include a data transfer control unit that uses the second clock signal generated by the phase adjustment circuit as an operation clock signal of the second device in data transfer to two devices, the phase The adjustment circuit includes a plurality of delay stages having different delay times for the first clock signal, a register in which delay information can be set, From the plurality of delay stages based on the delay information set in serial register, configured to include a selection circuit for selecting a corresponding delay stages.

[0013] According to the above means, the data transfer control section generates the second signal generated by the phase adjusting circuit as the operation clock signal of the second device in the data transfer from the first device to the second device. Use a clock signal. At this time, it is possible to change the phase difference between the first clock signal and the second clock signal by changing the setting contents of the register included in the phase adjustment circuit. Therefore, it is not necessary to deal with the data delay in the hardware design, which shortens the development period of the data transfer system.

The data transfer control section may be a direct memory access controller. In that case, the direct memory access controller, the first clock generation unit, the phase adjustment circuit, and the like can be formed on one semiconductor substrate. In that case, a first terminal capable of externally outputting the first clock signal and a second terminal capable of externally outputting the second clock signal.
And a terminal can be provided.

[0015]

FIG. 1 shows a data processing device which is an example of a data transfer system according to the present invention. The data processing device 8 shown in FIG. 1 is not particularly limited, but includes a plurality of devices such as a microcomputer 9, a memory 14, and an external device 15 mounted on a printed circuit board. A plurality of devices such as the microcomputer 9, the memory 14, and the external device 15 are coupled to each other via an address bus 16 for transmitting an address signal and a data bus 17 for transferring data so that they can exchange data with each other. ing.

The microcomputer 9 is not particularly limited, but includes a central processing unit (CPU) 10, a clock generating circuit (CPTG) 11, a phase adjusting circuit 12, a DMAC (direct memory access controller) 13, and other peripherals. The circuit 7 is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. The other peripheral circuits 7 include a timer for measuring time, a serial communication interface that enables serial communication, and the like.
The CPU 1 executes arithmetic processing according to a preset program and controls operation of various peripheral circuits and devices arranged inside and outside the microcomputer 9. The clock generation circuit 11 uses the clock signal CK having a predetermined frequency.
Generate IO. The clock signal CKIO is supplied to various peripheral circuits and devices inside and outside the microcomputer 9. The phase adjusting circuit 12 delays the clock signal CKIO transmitted from the clock generating circuit 11 to generate a phase adjusted clock signal CKIO ′. This clock signal CKIO 'is used by the external device 15
Be transmitted to. Although not particularly limited, the memory 14 is D
The RAM (Dynamic Random Access Memory) and the external device 15 are SDRAM (Synchronous Dynamic Random Access Memory). Here, the memory 14 is an example of the first device of the present invention, and the external device 15 is an example of the second device of the present invention.

FIG. 4 shows a configuration example of the phase adjusting circuit 12.

As shown in FIG. 4, the phase adjusting circuit 1 is provided.
Reference numeral 2 denotes an input buffer 121 for receiving the clock signal CKIO transmitted from the clock generation circuit 11, and a plurality of delay stages 122-1 to 122-1 for delaying the clock signal CKIO captured via the input buffer 121.
122-n and the plurality of delay stages 122-1 to 122-
A register 124 for holding n selection information, and a selection circuit for selectively transmitting the output signals of the plurality of delay stages 122-1 to 122-n to a subsequent circuit based on the information held in the register 124. 123 and. Here, the register 124 is an example of the delay time setting means in the present invention.

The plurality of delay stages 122-1 to 122-n
Are different in the number of stages of delay circuits (DL) that delay the signals so that the clock signals have different delay times. The larger the number of stages of the delay circuit (DL), the longer the delay time there. The register 124 is set by the CPU 10 when the data processing device 8 is reset and the initialization program is executed by the CPU 10.

Next, the DMA single address data transfer performed from the memory 14 to the external device 15 in the data processing device 8 configured as described above will be described.

First, the DMA request signal DREQ is asserted from the external device 15 to the microcomputer 9. When this request is accepted by the microcomputer 9, the DMA acknowledge signal is asserted to the external device 15. At almost the same time that the DMA acknowledge signal is asserted, the microcomputer 9 outputs an address signal for reading data to the memory 14 to the address bus 16. Memory 14
Stores the stored data from the external terminal Q to the data bus 17 according to the address signal transmitted via the address bus 16.
Output to. The data output in this case is performed in synchronization with the clock signal CKIO transmitted from the clock generation circuit 11.

The external device 15 takes in the data transmitted via the data bus 17 from the external terminal D. Data acquisition in the external device 15 is performed in synchronization with the clock signal CKIO ′ transmitted from the phase adjustment circuit 12. The clock signal CKIO 'is the clock signal C
The phase is delayed more than KIO.

Next, the advantages of using the clock signal CKIO 'whose phase is delayed from that of the clock signal CKIO in the DMA single address data transfer will be described below.

FIG. 2 shows the memory 14 and the external device 1.
5 shows the operation timings of the main parts when both are operated in synchronization with the clock signal CKIO.

The data output from the memory 14 is delayed and transmitted to the external device 15 due to a signal delay in the data transmission path from the external terminal Q of the memory 14 to the external terminal D of the external device 15. When both the memory 14 and the external device 15 are operated in synchronization with the clock signal CKIO, the external device 15 takes in data at the rising timing 20 of the clock signal CKIO.
Therefore, when the frequency of the clock signal CKIO is high, the setup time is short as indicated by 201, so that correct data cannot be fetched from the external terminal D.

On the other hand, as shown in FIG. 3, for the data output from the external terminal Q, the clock signal CK is used.
When the data is taken in in synchronization with IO and the data is taken in by the external device 15, the data is taken in by the external device 15 when the data is taken in by the clock signal CKIO ′ transmitted from the phase adjusting circuit 12. Since it is performed at the rising timing 302 of the clock signal CKIO ′ whose phase is delayed from that of the clock signal CKIO, the setup time can be secured as indicated by 301 even when the frequency of the clock signal CKIO is high. Can capture data.

According to the above example, the following operational effects can be obtained.

(1) Data output from the external terminal Q is performed in synchronization with the clock signal CKIO, and data capture in the external device 15 is performed in synchronization with the clock signal CKIO 'transmitted from the phase adjusting circuit 12. Since this is performed, even when the frequency of the clock signal CKIO is high, the setup time can be secured as indicated by 301, so that correct data can be fetched.

(2) The phase adjustment circuit 12 includes a plurality of delay stages 122-1 to 122-n having different delay amounts, a register 124 in which delay information can be set, and the register 1
Since it is configured to include a selection circuit 123 for selecting a corresponding delay stage from the plurality of delay stages 122-1 to 122-n based on the delay information set in 24, the storage content of the register 124 is changed. By changing it, the delay time of the clock signal CKIO ′ can be changed. The contents stored in the register 124 may be changed by modifying the initialization program executed by the CPU 10. According to the conventional technology, for each data processing device, the phase design is performed in the total system including the peripheral circuit, and it is reflected in the hardware design of the external device, but in this example, as described above, Since it suffices to change the storage contents of the register 124 by modifying the initialization program executed by the CPU 10, it is possible to easily deal with a partial change of the device mounted in the data processing device. Therefore, the development period of the data processing device can be shortened. Further, by controlling the DMAC 13, it is possible to improve the versatility of the data transfer system that transfers the DMA single address data from the memory 14 to the external device 15.

Next, another configuration example of the present invention will be described.

FIG. 5 shows a structural example of the main part of the microcomputer 9. In FIG. 5, the peripheral circuit 7, the CPU 10, the DMAC 13, etc. are omitted.

A selector 51 is provided in the preceding stage of the clock generation circuit 11. This selector 51 has a first terminal 5
A clock signal fetched from outside the microcomputer 9 via 6, a pulse signal generated by the crystal oscillator 55, and an output signal from the phase adjustment circuit 12 are selectively transmitted to the clock generation circuit 11. Here, the clock generation circuit 11 multiplies the input signal to generate a clock signal of a predetermined frequency. Clock generation circuit 11
The output signal from the tri-state buffer 53 in the subsequent stage
Also, external output is possible via the first terminal 56. Further, a selector 52 is provided in the preceding stage of the phase adjustment circuit 12. The selector 52 selectively transmits the signal fetched through the second terminal 57 and the output signal of the clock generation circuit 11 to the phase adjustment circuit 12. The configuration of the phase adjustment circuit 12 is the same as that shown in FIG. The output signal from the phase adjustment circuit 12 can be externally output via the tri-state buffer 54 and the second terminal 57 in the subsequent stage.

In the above configuration, the selector 51 selects the output signal of the crystal oscillator 55, and the selector 52
The output signal of the clock generation circuit 11 is selected by
Further, in a state where the corresponding tri-state buffers 53 and 54 are made conductive by the mode signals MD1 and MD2, respectively, the clock signal CKIO is externally output via the first terminal 56 as in the case of the example shown in FIG. Is
The clock signal CKIO ′ is externally output via the second terminal 57. Therefore, as in the case of the above example, data transfer can be performed using the clock signals CKIO and CKIO ′, and the same effect as in the case of the above example can be obtained.

Further, the output signal of the phase adjusting circuit 12 is selected by the selector 51, and the second signal is selected by the selector 52.
The clock signal input via the terminal 57 is selected,
Tri-state buffer 53 according to mode signal MD1
Is made conductive and the tri-state buffer 54 is made non-conductive by the mode signal MD2.
After the phase of the clock signal input via the terminal 57 is adjusted by the phase adjustment circuit 12, it is transmitted to the clock generation circuit 11 via the selector 51 and multiplied there, and then the tri-state buffer 53 and the first terminal. It is externally output via 56. This mode is synchronized with the fixed clock signal in a system in which, for example, a digital television signal processing circuit is arranged outside the microcomputer 9 and the frequency of the clock signal used in the processing circuit is fixed. This is convenient when the clock signal CKIO is generated. That is, the clock signal used in the processing circuit of the digital television signal is input to the phase adjustment circuit 12 via the second terminal, the phase is adjusted here, and then input to the clock generation circuit 1 to be multiplied by the clock signal. A signal CKIO is obtained, which is output inside the microcomputer 9 or externally via the first terminal.

Then, the signal input via the first terminal 56 is input to the clock generation circuit 11 by the selector 51, and the clock generation circuit 11 is input by the selector 52.
Is transmitted to the phase adjustment circuit 12, the tri-state buffer 53 is rendered non-conductive by the mode signal MD1, and the tri-state buffer 54 is rendered conductive by the mode signal MD2. The clock signal input via the clock generation circuit 11
In the tri-state buffer 54 and the output buffer 54 after the phase is adjusted by the phase adjusting circuit 12.
Can be output externally via. In this case, the frequency multiplied by the clock generation circuit 11 is supplied to the memory 14 or the like as CKIO, and the phase adjusted by the phase adjustment 12 is supplied to the external device 15 as CKIO ′. The same effect can be obtained.

Although the invention made by the present inventor has been specifically described above, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

In the above description, the case where the invention made by the present inventor is mainly applied to the data processing apparatus which is the field of application which is the background of the invention has been described, but the present invention is not limited to it and various data can be obtained. It can be applied to the transfer system.

The present invention can be applied under the condition that data is transferred at least between different devices.

[0039]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, by changing the setting contents of the delay time setting means, the phase difference between the first clock signal and the second clock signal can be changed, and the phase design in a total system including peripheral circuits for each system. Since it is unnecessary to reflect the information in the hardware design of the external device, the development period of the data transfer system can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram of a configuration example of a data processing device which is an example of a data transfer system according to the present invention.

FIG. 2 is an operation timing chart of a main part when both the memory and the external device are operated based on a clock signal CKIO in the data processing device.

FIG. 3 is an operation timing chart of a main part when the memory and the external device are operated at different timings in the data processing device.

FIG. 4 is a block diagram of a configuration example of a main part of the data processing device.

FIG. 5 is a block diagram of another configuration example of a main part of the data processing device.

[Explanation of symbols]

7 peripheral circuits 8 Data processing device 9 Microcomputer 10 CPU 11 Clock generation circuit 12 Phase adjustment circuit 13 DMAC 14 memory 15 External device 16 address bus 17 data bus 122-1 to 122-n delay stage 123 selection circuit 124 registers

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Atsushi Kishihara             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within (72) Yoshimi Ishida, inventor             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within (72) Inventor Eiji Kiriyama             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within F-term (reference) 5B077 GG15 GG36 MM01 MM02                 5B079 AA06 CC02 CC14 CC16 DD06                       DD13 DD17

Claims (4)

[Claims] 1. A first for generating a first clock signal
A clock generator, delay time setting means capable of setting delay time information, and delaying the first clock signal by a predetermined time based on the delay time information set in the delay time setting means, thereby the first clock A phase adjustment circuit for generating a second clock signal whose phase is delayed from the signal, a first device operated by the first clock signal, and data exchange between the first device are possible. A second device; and a data transfer control unit that uses the second clock signal obtained by the phase adjustment circuit as an operation clock signal of the second device in data transfer from the first device to the second device. A data transfer system including: 2. A first for generating a first clock signal
A clock generation unit, a phase adjustment circuit for delaying the first clock signal by a predetermined time to generate a second clock signal having a phase delayed from the first clock signal, and operated by the first clock signal. And a second device that enables data to be exchanged between the first device and an operating clock signal of the second device in data transfer from the first device to the second device. A data transfer control unit that uses the second clock signal generated by the phase adjustment circuit, wherein the phase adjustment circuit includes a plurality of delay stages having different delay times for the first clock signal, and delay information. A register that can be set, and from the plurality of delay stages based on the delay information set in the register,
A data transfer system comprising: a selection circuit for selecting a corresponding delay stage. 3. A first for generating a first clock signal
A clock generation unit, a phase adjustment circuit for delaying the first clock signal by a predetermined time to generate a second clock signal having a phase delayed from that of the first clock signal, and operated by the first clock signal. A direct memory access controller that uses the second clock signal generated by the phase adjusting circuit as an operation clock signal of the second device in the direct memory access transfer from the first device to the second device. The phase adjustment circuit is formed on one semiconductor substrate, and based on the delay information set in the register, a plurality of delay stages having different delay times of the clock signal, a register in which delay information can be set, A selection circuit for selecting a corresponding delay stage from the plurality of delay stages. The semiconductor integrated circuit characterized by comprising. 4. The semiconductor integrated circuit according to claim 3, comprising a first terminal capable of outputting the first clock signal to the outside and a second terminal capable of outputting the second clock signal to the outside.