JP2003141058A - Communication control lsi and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow the retransfer of data according to a retry request. SOLUTION: This communication control LSI comprises a DMA controller 13 allowing a direct memory access; a FIFO buffer 12 capable of holding received data in a first-in first-out form, a retry buffer 14 capable of holding the output data from the FIFO buffer and a data selection part 15 for selectively supplying the output data from the FIFO buffer and the output data from the retry buffer. Even if the pointer of the FIFO buffer is already updated, the corresponding data is read from the retry buffer, whereby the retransfer of data can be performed according to the retry request.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit,
Furthermore, the present invention relates to a communication control LSI for controlling communication in a network.

[0002]

2. Description of the Related Art A communication control LSI is an example of a semiconductor integrated circuit, and has a chain block DMA (direct memory) in order to efficiently transfer data to and from a system memory.
A DMA format called memory access) is supported. The chain block DMA is used as a means for continuously transferring a plurality of data buffers on the memory, and this chain block DMA is simply referred to as “D” in the following description.
MA ”. Each data buffer is associated with a data group of more than ten bytes called a descriptor. The descriptor is composed of the next descriptor start address, the corresponding buffer address, the data length, and the status.

Such a communication LSI is applied to a relay device such as a router together with a system memory and a transceiver. In this case, the communication control LSI, the system memory, the MPU (micro processing unit), etc., are connected to the PCI (peripheral comp).
It is possible to exchange data with each other via an present interconnect bus. Communication control LS
I, system memory, MPU, etc. are coupled to the PCI bus via glue logic called a PCI bridge.

When data is received in serial form from the communication line via the transceiver, the data is converted into parallel form in the communication control LSI. This data format conversion is performed by a FIFO (First In First Out) buffer. Then, the data converted into the parallel format by this FIFO is PCI by the communication control LSI.
DMA to system memory after bus usage right is acquired
(Direct memory access) control transfers data to the system memory. When the data stored in the system memory is transmitted, it is transmitted to the communication control LSI via the PCI bus, converted from the parallel format to the serial format, and then transmitted to the communication line.

As an example of the document describing the communication control technique, there is Japanese Patent Laid-Open No. 5-158865.

[0006]

When the data received from the communication line is transferred to the system memory under the control of the communication control LSI, a PC is caused due to a data collision or the like.
It is conceivable that the I-bridge may make a retry request to the communication control LSI by a retry request. When this retransfer request is made, the communication control LSI needs to retransfer the data relating to the request. However,
In the FIFO buffer used for converting the data format, the pointer is updated when the data is read. Therefore, after the data is read from the FIFO buffer and is DMA-transferred, the DMA transfer is started. Since the data is deleted from the FIFO buffer, P
It has been found by the inventor of the present application that even if the communication control LSI receives a retry request from the CI bridge, the data cannot be retransmitted in response to the retry request.

The DMA controller also includes a state control unit that determines the next internal state according to the current internal state, and a bus control unit that controls the external bus according to the state control code from this state control unit. In the external bus control unit, the state recognized by the state control unit and the state given by the above state control and recognized by the bus control unit are deviated by one cycle in the operation cycle in the state control unit. is there. That is, the new state of the state control unit indicates a state one bus cycle ahead of the actual external bus cycle.

By the way, actually, in the external bus cycle, the bus arbitration circuit may be forced to abandon the bus condition. Since this state control unit has already generated the state of the next bus cycle, the next time the bus cycle is acquired, the state control unit generates the bus cycle according to the already generated state code. For example, when the operating channel is disabled, the DMA controller should normally generate the channel with the next highest priority, but the DMA controller should disable the channel that has been disabled according to the pre-read status code. It causes a bus cycle. It has been found by the present inventor that this may cause the operation of the state control unit in the DMA controller to be broken.

An object of the present invention is to provide a state control technique capable of promptly transiting from a current state to another state.

Another object of the present invention is to provide a communication control LSI capable of retransmitting data in response to a retry request.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

[1] A DMA controller that enables direct memory access, a first buffer that can hold received data in a first-in first-out format, a second buffer that can hold output data from the first buffer, and the first buffer. 1
When the communication control LSI is configured with a data selection unit for selectively supplying the output data from the buffer and the output data from the second buffer to the DMA controller, when the communication control LSI is configured, A state control unit that determines the internal state of the bus, and a bus control unit that controls the external bus according to the state code given from the state control unit,
The DM including a buffer control unit capable of controlling transmission of output data of the second buffer to the bus control unit via the data selection unit in response to a retry request from the outside.
Configure the A controller. At this time, the state recognized by the state control unit and the state recognized by the bus control unit are overlapped in a range shorter than one cycle in the operation cycle of the state control unit. The first buffer may be a FIFO buffer and the second buffer may be a retry buffer.

According to the above means, the data selecting section selectively supplies the output data from the first buffer and the output data from the second buffer to the DMA controller. Even if the pointer of the first buffer is updated when a re-transfer request (also referred to as “retry request”) is made due to a retry request due to data collision or the like, the corresponding data is read from the second buffer. Therefore, the data can be retransmitted in response to the retry request. Further, the bus control unit overlaps the state recognized by the state control unit and the state recognized by the bus control unit within a range shorter than one cycle in the operation cycle of the state control unit. Therefore, even if the bus right of the communication control LSI is forcibly deprived by the bus arbitration circuit, it can be fed back to the status code generated by the status control unit, which should not occur. The look-ahead of the code can be avoided, thereby obtaining the desired bus cycle.

[2] Communication control LS is provided with a DMA controller that enables direct memory access and a buffer that can hold received data in accordance with pointer instructions.
When I is configured, the DMA controller includes a state control unit that determines the next internal state according to the current internal state, and a bus control unit that controls the external bus according to the state code given from the state control unit. , And a buffer control unit capable of updating the pointer of the buffer before starting the DMA transfer, provided that there is no retry request from the outside. At this time, the state recognized by the state control unit,
The state recognized by the bus control unit is overlapped in a range shorter than one cycle in the operation cycle of the state control unit.

According to the above means, the buffer control unit updates the pointer of the buffer before starting the DMA transfer, on condition that there is no retry request from the outside. If there is no retry request, the pointer of the buffer is not updated, so that the data held in the buffer can be used to retransfer the data.

[3] Communication control LS including a DMA controller that enables direct memory access and a buffer that can hold received data in accordance with pointer instructions
When I is configured, the DMA controller includes a state control unit that determines the next internal state according to the current internal state, and a bus control unit that controls the external bus according to the state code given from the state control unit. , And a buffer control unit capable of retracting the pointer in response to a retry request from the outside. At this time, the state recognized by the state control unit and the state recognized by the bus control unit are overlapped in a range shorter than one cycle in the operation cycle of the state control unit.

According to the above means, the buffer control unit retracts the pointer in response to a retry request from the outside. When the data corresponding to the retry request remains in the buffer, the retreat of the pointer enables the retransfer of the corresponding data.

[4] A communication control LSI having a DMA controller that enables direct memory access, wherein the DMA controller determines a next internal state according to the current internal state, and the above state. And a bus control unit for controlling the external bus according to the status code given from the control unit. At this time, the state recognized by the state control unit and the state recognized by the bus control unit are overlapped in a range shorter than one cycle in the operation cycle of the state control unit.

According to the above means, even if the bus right of the communication control LSI is forcibly deprived by the bus arbitration circuit, it can be fed back to the status code generated by the status control unit. Prefetching of status codes that should not occur can be avoided, so that the desired bus cycle can be obtained.

[5] A DMA controller that enables direct memory access, a first buffer that can hold data in a first-in first-out format, a second buffer that can hold output data from the first buffer, and the first buffer. A communication control LSI comprising: a data selection unit for selectively supplying output data from a buffer and output data from the second buffer to the DMA controller, wherein the DMA controller is the first In response to a transfer request signal from the buffer, transfer control of the storage data of the first buffer to the bus control unit via the data selection unit, and via the data selection unit for a retry request from the outside. And a buffer control unit for controlling transfer of data stored in the second buffer to the bus control unit.

According to the above means, when the retransfer request is made by the retry request, the corresponding data can be read from the second buffer even if the pointer of the first buffer is updated. The data can be retransmitted according to the above.

[6] A DMA controller that enables direct memory access and a buffer that can hold received data in accordance with a pointer instruction are provided, and the DMA controller is DMA provided that there is no retry request from the outside. A buffer control unit that enables retransmission of received data in response to a retry request by updating the pointer of the buffer before the transfer is started.

According to the above means, the pointer of the buffer is not updated when there is no retry request.
Data can be retransferred by using the data held in the buffer.

[7] A DMA controller capable of direct memory access and a buffer capable of holding received data in accordance with an instruction from the pointer, and the DMA controller is a buffer control capable of moving the pointer backward in response to a retry request. Including parts.

According to the above means, the pointer can be moved backward. Therefore, when the data corresponding to the retry request remains in the buffer, the pointer is moved backward so that the corresponding data is retransferred. It will be possible.

[8] A semiconductor integrated circuit according to another aspect of the present invention is a semiconductor integrated circuit capable of holding input data in a first-in first-out format.
1 buffer, a second buffer capable of holding output data from the first buffer, selection means for selecting the output data of the first buffer or the output data of the second buffer, the data selected by the selection means And a DMA controller capable of inputting and controlling DMA transfer. The DMA controller includes a bus controller for data transfer, a buffer controller for accessing the first and second buffers,
A state control unit that performs state transition control for the bus control unit and the buffer control unit is provided. The time from the input of information for the control state transition by the state control unit to the reflection of the input in a new control state is shorter than the state transition control cycle of the state control unit. If the time is equal to or longer than the state transition control cycle of the state control unit, even if there is an information input for transitioning the control state in the middle of the cycle, a substantially useless control state determined by the previous input is Will occur. With the above means, it is possible to suppress the occurrence of such a wasteful control state. Further, the state control unit causes the selection unit to select the output data of the second buffer in response to a retry request for data transfer control. As a result, even when a FIFO format buffer is used, data can be retransmitted in response to a retry request.

[0028]

[9] In a semiconductor integrated circuit according to another aspect, as a measure against a retry request, the read pointer of the buffer is changed to a value indicating the retry target data in response to the retry request of data transfer control.

[0029]

FIG. 2 shows a main part of a communication control device including a communication control LSI according to the present invention.

The communication control device shown in FIG. 2 is not particularly limited, but MPU (micro processing unit) 41, local memory 42, system memory 4
3, communication control LSI, PCI bridges 44, 45, 4
6 and a bus arbitration circuit 47.

The MPU 41, the local memory 42, and the bus arbitration circuit 47 are connected via the local bus 403 so that signals can be exchanged with each other. The local bus 403 is coupled to the PCI bus 401 via the PCI bridge 45. Communication control LSI 40
Is coupled to a local bus 402, which is connected via a PCI bridge 44 to the PCI bus 40.
Combined with 1. The system memory 43 is coupled to a local bus 404, which is a PCI bus.
It is coupled to PCI bus 401 via bridge 46.

The PCI bridges 44 to 46 interface various signals exchanged between the corresponding local buses 402 to 404 and the PCI bus 401 so as to conform to the standards of the respective buses.

Like the MPU 41, the communication control LSI 40 has a function as a bus master, acquires the right to use the PCI bus 401, and DMAs data (direct memory) between an internal FIFO buffer and a system memory described later. Access) Transfer is possible.

The bus arbitration circuit 47 arbitrates the competition between the MPU 41 and the communication control LSI 40 for the bus right of the PCI bus 401. PCI bus 4 by MPU41
If 01 is used, P from the communication control LSI 40
The request to use the CI bus 401 is rejected. On the contrary, if the communication control LSI 40 uses the PCI bus 401, the MPU 41 cannot use the PCI bus 401.

When a data error occurs in the DMA transfer, a retry request signal RETRY * (* may mean low active) for instructing the retransfer of the data relating to the error is asserted by the PCI bridge 44. . When the retry request signal RETRY * is asserted, the communication control LSI 40 retransfers the corresponding data according to the retry request signal.

Further, the system memory 43 is coupled to the local bus 404, and the local bus 404 is coupled to the PCI bus 401 via the PCI bridge 46. The data received by the communication control LSI 40 is DMA-transferred from the communication control LSI 40 to the system memory 43.

FIG. 1 shows a configuration example of the communication control LSI 40.

Although not particularly limited, the communication control LSI 40 shown in FIG. 1 is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

A protocol processing unit 10 is provided, and this protocol processing unit 10 receives the received data 10 in serial format.
1 is taken in and a predetermined protocol process is performed. In this protocol processing, the protocol processing unit 10 uses the serial FIFO storage data 103 and this serial FIFO
A FIFO write signal 102 for writing the stored data 103 into the FIFO buffer 12 is output.

A serial / parallel conversion unit 11 is provided, and this serial / parallel conversion unit 11 converts the serial FIFO storage data 103 transmitted from the protocol processing unit 10 into parallel FIFO storage data 104. This parallel FIFO storage data 104 is a FIFO
It is stored in the O buffer 12.

The FIFO buffer 12 receives the parallel FIFO transmitted from the serial / parallel converter 11.
O stored data 104 is transferred to the FI from the protocol processing unit 10.
It is fetched based on the FO write signal 102. When the data stored in the FIFO buffer 12 reaches a predetermined amount by writing to the FIFO buffer 12 in this way, the FIFO buffer 12 asserts the transfer request signal 107. In response to this, the DMA controller 13 causes the FIFO read signal 1
08 is asserted. By asserting the FIFO read signal 108, the FIFO buffer 12 and the RE
Data is read from the TRY (retry) buffer 14.

The retry buffer 14 is arranged in the subsequent stage of the FIFO buffer 12, and the FIFO output data 105 output from the FIFO buffer 12 is held in the retry buffer 14. This held data is transmitted to the data selection unit 15 as the retry buffer output data 106.

The data selection unit 15 selectively selects the FIFO output data 105 and the retry buffer output data 106 based on the data selection signal 109. The selected data is transmitted as the data selection signal 110 to the subsequent DMA controller 13.

The DMA controller 13 includes a state control unit 131, a buffer control unit 132, and a bus control unit 133, although not particularly limited thereto. The state control unit 131 is a so-called state machine, and performs state transition control that determines the next internal state according to the current internal state. The status code output from the status control unit 131 is transmitted to the buffer control unit 132 and the bus control unit 133. The transfer request signal 107 is transmitted from the FIFO buffer 12 to the buffer control unit 132. In addition, the buffer control unit 132
The FIFO read signal 108 for instructing the data read is transmitted from the FIFO buffer 12 to the retry buffer 14. Further, the buffer control unit 132
Therefore, the data selection signal 110 for data selection is transmitted to the data selection unit 15. A bus request signal BUSREQ is output from the bus control unit 133, and a bus acknowledge signal BUSACK corresponding to the bus request signal BUSREQ is input. further,
A data bus DBUS is coupled to the bus control unit 133,
Data can be input / output through the data bus DBUS. The bus request signal BUSREQ and the bus acknowledge signal BUSACK are transmitted via the control bus. The control bus and the data bus DBUS are included in the local bus 402 (see FIG. 2).
reference). Further, various signals fetched through the external terminals of the present LSI are transmitted to the state control unit 131. These various signals include the bus release signal BU
SREL *, retry signal RETRY *, and wait signal WAIT * are included.

FIG. 7 shows state transitions in the state control unit 131. When the predetermined conditions are satisfied, the transition from the transfer state to the idle state and the transition from the idle state to the transfer state are enabled, and the transition from the transfer state to the wait state and the transition from the wait state to the transfer state are possible. Enabled, transition from transfer state to bus release state is possible, and transition from bus release state to idle is possible.

FIG. 8 shows the detailed state transition in the transfer state. A transition from the idle state to the chain pointer read state (CP) is possible, and a transition from the chain pointer read state (CP) to the buffer pointer read state (BP) is possible. Then, the transition from the buffer pointer read state (BP) to the status read state (STR) is possible, and the transition from the status read state (STR) to the analysis state (ANA) is possible. Further, it is possible to transit from the analysis state (ANA) to the chain pointer read state (CP) or the status read state (STR) via polling (POL). Furthermore, the transition from the analysis state (ANA) to the data transfer state (DATA) is possible, and the data transfer state (DATA) to the status write state (ST
W) is allowed. Then, the transition from the status write state (STW) to the idle state is enabled.

A clock generator (CPG) 16 is provided and generates an internal clock signal CLK1 based on the input system clock signal CLK. The internal clock signal CLK1 is supplied to each unit in the communication control LSI 40.

FIG. 3 shows the operation timing of the main part of the communication control LSI 40.

One state in the state control unit 131 is
It is two clock times, and is operated in synchronization with the clock signal CK1 generated by the clock generation unit 16. Assuming that the state in the state control unit 131 changes in the order of “A”, “B”, and “C”, the generation timing of the state is synchronized with the rising edge of every two clocks of the internal clock signal CLK1. The state recognized by the bus control unit 133 overlaps the operation cycle of the state control unit 131 within a range shorter than one bus cycle. In other words, the time from the input of information for the control state transition by the state control unit 131 to the reflection of the input in the new control state is based on the state transition control cycle of the state control unit 131 (two cycles of CLK1). Is also shortened. Specifically, the state recognized by the bus control unit 133 is overlapped with the state of the state control unit 131 by a period corresponding to one clock of the internal clock signal CLK1. As a result, when the operation cycle in the state control unit 131 is synchronized with the rising edge of every two clocks of the internal clock signal CLK1, the operation cycle in the bus control unit 133 is synchronized with the clock signal one clock later.

When the state on the local bus 402 is a specific state, and the external terminal signals such as the retry signal RETRY *, the wait signal WAIT *, and the bus release signal BUSREL * are asserted, the state control unit 131.
Then, the state transition is performed accordingly. At this time, the state control unit 131 needs to store the current state (state immediately before the transition). Consider, for example, a case where the state of the local bus 402 is “B” and the state transits to the state “C” according to the change of the external terminal signal. In this case, the state control unit 131 determines the next state to transition to based on the current external state “B” and the state of the external terminal signal at the rising edge of the internal clock signal CLK1. Since the state code in the state control unit 131 and the state code in the bus control unit 133 overlap each other for a period corresponding to one clock in the internal clock signal CLK1, the current state “B” of the local bus is monitored. By doing so, the internal state “B” immediately before the transition to the state “C” can be known. Therefore, the transition from the state "B" to the state "C" is completed promptly.

Now, a comparison will be made with the case where the timing of the local bus 402 is controlled at a timing delayed by one bus cycle from the state control logic.

As shown in FIG. 13, the state controller 13
If the timing of the status code in the bus control unit 133 is delayed by one cycle compared to the timing of generating the status code in 1, the external terminal signal is asserted to the high level to change the status from “B” to the status. Even if the transition to “C” is instructed, the state of “state” is set after the external terminal signal is asserted until the state code in the bus control unit 133 is actually changed from state “B” to state “C”. B "
Is inserted for 2 cycles. On the other hand, the state control unit 1
The state code generation timing in 31 is delayed by a period corresponding to one clock in the internal clock signal CLK1, so that the state in the local bus 402 is longer than that in the state control unit 131. When delayed by a period corresponding to one clock in CLK1, the state transitions to the state "C" in the next cycle when the external terminal signal is asserted to the high level, as shown in FIG. , State transition is completed promptly.

Further, when the timing of the local bus 402 is controlled at a timing delayed by one bus cycle from the state control logic, the operation of the state transition unit 131 in the DMA controller 13 will fail.
If the state of the local bus 402 is delayed by a period corresponding to one clock of the internal clock signal CLK1 as compared with the internal state of the state control unit 131, such inconvenience does not occur. This will be described with reference to FIGS. 14 and 15.

For example, as shown in FIG. 14, the external bus control unit delays the state code generated by the state control unit and delays the external bus (local bus) by one bus cycle behind the state control logic. When the timing is controlled, the state in the state control unit is one bus cycle ahead of the actual external bus cycle. However, the external bus cycle may actually be forced to abandon the bus condition by the external bus arbitration logic, and this state control unit has already generated the status code of the next bus cycle. When the cycle is acquired, the bus cycle is generated according to the already generated status code. If the operating channel is disabled, the DMA controller should normally generate the next highest priority channel, but the bus of the disabled channel according to the prefetched status code. It causes a cycle. Due to this, the bus cycle (D) that should not be executed is executed, and the operation of the state control unit of the DMA controller is unlocked. On the other hand, when the state of the local bus 402 is delayed by a period corresponding to one clock of the internal clock signal CLK1 as compared with the internal state of the state control unit 131, as shown in FIG. The bus right of the communication control LSI is assigned to the bus arbitration circuit 4.
Even if it is forcibly stripped by 7, it can be fed back to the status code generated by the status control unit 131, and it is possible to avoid prefetching the status code (D) that should not occur originally. Because you can
A desired bus cycle can be obtained by the bus control unit 131.

FIG. 4 shows the timing of the retry operation when the configuration shown in FIG. 1 is adopted.

The state control unit 131 starts the retry process at the next rise of the clock signal CLK1 when the state control cycle in the bus control unit 133 is set to the transfer state and the retry request signal RETRY * is at the low level. The state control unit 131 at the start of this retry process
First, the transition to the idle state is made, and then the bus request signal BU during the low level of the retry request signal RETRY *.
Set SREQ * to high level. The bus arbitration circuit 47
Bus acknowledge BUSACK * for communication control LSI 40
To a high level to deprive the communication control LSI of the bus right. When the state control unit 131 detects that RETRY * has been set to the high level, the state control unit 131 sets BUSREQ * to the low level again and requests the bus right to the bus arbitration circuit 47. During this time, the state control unit 131 maintains the idle state. A bus acknowledge signal B is output by the bus arbitration circuit 47.
When USACK sets BUSACK * to a low level and the communication control LSI acquires the bus right again, the state control LSI enters the retransfer state, and the transfer that was being executed when the retry was accepted is executed again. The state control unit 131 is performing a retry process until the idle state side transfer state, and the process returns to the normal transfer state process from the next tense state.

FIG. 5 shows the timing of the bus release operation.

When the bus control unit 133 is in the transfer state and the release signal BUSREL * is at the low level, the state control unit 131 starts the bus release process at the next rise of the clock signal CLK1. At the start of the bus release process, the state control unit 131 first transits to the idle state, and then the bus right request signal BUSREQ * is set to the high level while the retry signal RETRY * is at the low level. The bus arbitration circuit 47 deprives the bus right when the communication control LSI 40 negates the acknowledge signal BUSACK * to a high level. The state control unit 131
When it detects that the release signal BUSREL * is at the high level, it sets the bus right request signal BUSREQ * to the low level again to request the bus right to the bus arbitration circuit 47. During this time, the state control unit 131 maintains the idle state. The state control unit 131 uses the bus right request signal BUSR.
When EQ * is set to low level, the release process ends,
Return to normal processing. However, even after returning to the normal processing, the idle state is held until the bus right is acquired again.

According to the above example, the following operational effects can be obtained.

(1) The state control cycle in the bus control unit 133 is delayed from the state control cycle in the state control unit 131 by a period corresponding to one clock in the internal clock signal CLK1. Since the recognized state and the state recognized by the bus control unit 133 overlap in a range shorter than one cycle of the operation cycle of the state control unit 131, the state recognized by the state control unit 131 , The state recognized by the bus control unit 133 is 1 in the operation cycle of the state control unit 131.
Since the overlap is made in a range shorter than the cycle, the state transition is completed in the next cycle when the external terminal signal is asserted to the high level, so that the state transition is completed promptly (FIG. 3). reference).

(2) When the state on the local bus 402 is delayed by a period corresponding to one clock in the internal clock signal CLK1 as compared with the internal state in the state control unit 131, as shown in FIG. In addition, even if the bus right of the communication control LSI is forcibly deprived by the bus arbitration circuit 47, it can be fed back to the status code generated by the status control unit 131, and the status code that should not occur. Since it is possible to avoid prefetching, the bus control unit 131
A desired bus cycle can be obtained.

(3) Since the output data from the FIFO buffer 12 and the output data from the retry buffer 14 can be selectively supplied to the bus control unit 133, a retry request signal is generated due to a data collision or the like. When a retransfer request is made, the FIFO buffer 12
Even if the pointer of is already updated, the corresponding data can be read from the second buffer.
Data can be retransmitted in response to a retry request.

(4) Since the communication control LSI 40 has a retry function and can retransfer the corresponding data in response to a retry request from the outside, for example, the PC bridge 44 shown in FIG. Since there is no need to provide a retry function in the PC bridge 44, the PC bridge 44 can be simplified.

Next, another configuration example of the communication control LSI 40 will be described.

FIG. 9 shows the operation timing of the main part in another configuration example of the communication control LSI 40.

In this example, one state of the state control unit 131 corresponds to one clock time. State control unit 131
Operates in synchronization with the rising edge and the falling edge of the waveform of the clock signal CLK1. That is, the state control cycle activated by the state control unit 131 is synchronized with the rising edge of the waveform of the clock signal CLK1,
The state control cycle in the bus control unit 133 is synchronized with the falling edge of the clock signal CLK1. Even in this case, it is possible to obtain the same effect as that of the above example.

FIG. 10 shows another operation timing of the main part in the communication control LSI.

In this example, in the clock generator 16,
Two clock signals CL as non-overlap signals
K1 and CLK2 are generated. The state control cycle activated by the state control unit 131 is the clock signal CLK.
1 is synchronized with the rising edge of the waveform, and the bus control unit 13
The state control cycle at 3 is synchronized with the rising edge of the clock signal CLK2. Even in this case, it is possible to obtain the same effect as that of the above example.

FIG. 11 shows still another configuration example of the communication control LSI 40.

The communication control LSI 40 shown in FIG. 11 is largely different from that shown in FIG. 1 in the way of implementing the retry function. In the configuration shown in FIG. 1, the FIFO buffer 12 outputs the FIFO output data 105 by the FIFO read signal 108 and updates the pointer, but in this example, the FIFO pointer update signal 208 and the FI pointer are updated.
It is controlled individually by using the FO data output signal 209.

The buffer control unit 132 updates the pointer of the FIFO buffer 12 after confirming that there is no retry request and before the actual DMA transfer is started. If there is a retry request, the pointer is not updated, so the data related to the retry exists in the FIFO buffer. Therefore, in this example, even if the retry buffer 14 as shown in FIG.
The retry function can be realized by outputting the FIFO output data 105 corresponding to the retry request from the buffer 12.

FIG. 12 shows another configuration example of the communication control LSI 40.

The communication LSI 40 shown in FIG. 12 is shown in FIG.
1 is substantially different from that shown in FIG.
The point is that the pointer backward signal 309 from 32 enables the pointer of the FIFO buffer 12 to be backward (subtracted). At the time of a retry request, the pointer of the FIFO buffer 12 is subtracted under the control of the buffer control unit 132, so that the data which has already been transferred can be output again as the FIFO output data 105. As a result, the retry function is realized.

Although the invention made by the present inventor has been specifically described above, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

In the above description, the case where the invention made by the present inventor is mainly applied to the communication control LSI supporting the chain block DMA which is the field of use which is the background of the invention has been described, but the present invention is not limited thereto. However, it can be applied to various semiconductor integrated circuits.

The present invention can be applied under the condition that at least data communication is performed.

[0077]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, when a retransfer request is made by the retry request signal due to data collision or the like, even if the pointer of the first buffer is updated, the corresponding data can be read from the second buffer. Therefore, the data can be retransmitted in response to the retry request. Further, in the bus control unit, the state recognized by the state control unit and the state recognized by the bus control unit are overlapped in a range shorter than one cycle in the operation cycle of the state control unit. , Even if the bus right of the communication control LSI is forcibly deprived by the bus arbitration circuit,
It is possible to feed back that to the status code generated by the status control unit, and it is possible to avoid prefetching a status code that should not occur,
A desired bus cycle can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a configuration example of a communication control LSI according to the present invention.

FIG. 2 is a block diagram of a configuration example of a communication control device including the communication control LSI.

FIG. 3 is an operation timing chart of a main part of the communication control LSI.

FIG. 4 is an operation timing chart of a main part of the communication control LSI.

FIG. 5 is an operation timing chart of a main part of the communication control LSI.

FIG. 6 is an operation timing chart of a main part of the communication control LSI.

FIG. 7 is a state transition diagram of a state control unit in the communication control LSI.

FIG. 8 is a detailed state transition diagram of a main part in the state transition shown in FIG.

FIG. 9 is another operation timing chart of the main part of the communication control LSI.

FIG. 10 is another operation timing chart of the main part of the communication control LSI.

FIG. 11 is a block diagram of another configuration example of the communication control LSI according to the present invention.

FIG. 12 is a block diagram of another configuration example of the communication control LSI according to the present invention.

FIG. 13 is an operation timing chart of a main part of the communication control LSI.

FIG. 14 is an operation timing chart of a main part of the communication control LSI.

FIG. 15 is an operation timing chart of a main part of the communication control LSI.

[Explanation of symbols]

10 Protocol processing unit 11 Serial / parallel converter 12 FIFO buffer 13 DMA controller 14 Retry buffer 15 Data selection section 16 Clock generator 41 MPU 42 local memory 44, 45, 46 PCI bridge 47 bus arbitration circuit 48 Communication control device 131 State control unit 132 buffer control unit 133 Bus control unit

Continued front page    (72) Inventor Keiji Ichige             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Hisashi Suzuki             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Masahiko Iwamoto             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group F term (reference) 5B061 DD07 DD09 DD11 QQ01 RR03

Claims (10)

[Claims] 1. A DMA controller that enables direct memory access, a first buffer that can hold received data in a first-in first-out format, a second buffer that can hold output data from the first buffer, and the first buffer. A data selection unit for selectively supplying the output data from the buffer and the output data from the second buffer to the DMA controller, wherein the DMA controller sets the next internal state according to the current internal state. A state control unit for determining, a bus control unit for controlling an external bus according to a state code given by the state control unit, and output data of the second buffer for the data selection unit in response to a retry request from the outside. And a buffer control unit capable of transmission control to the bus control unit via On purpose, and the state of the bus control unit recognizes the communication control LSI, characterized in that it is overlapped by the range shorter than one cycle on the operation cycle of the state control unit. 2. A DMA controller that enables direct memory access, and a buffer that can hold received data according to an instruction of a pointer, wherein the DMA controller determines a next internal state according to a current internal state. The controller, the bus controller that controls the external bus according to the status code given by the status controller, and the condition that there is no retry request from the outside, the pointer of the buffer can be updated before starting the DMA transfer. The state recognized by the state control unit and the state recognized by the bus control unit, including a buffer control unit, are over a range shorter than one cycle in the operation cycle of the state control unit. A communication control LSI characterized by being wrapped. 3. A DMA controller that enables direct memory access, and a buffer that can hold received data according to an instruction of a pointer, wherein the DMA controller determines a next internal state according to a current internal state. The state control includes a control unit, a bus control unit that controls an external bus according to a state code given from the state control unit, and a buffer control unit that can retract the pointer in response to a retry request from the outside. The communication control characterized in that the state recognized by the section and the state recognized by the bus control section are overlapped in a range shorter than one cycle in the operation cycle of the state control section. LSI. 4. A communication control LSI having a DMA controller that enables direct memory access, wherein the DMA controller determines a next internal state according to a current internal state, and the state control section. A bus control unit that controls an external bus according to a state code given by the state control unit, and a state recognized by the state control unit and a state recognized by the bus control unit are A communication control LSI characterized by being overlapped in a range shorter than one cycle in an operation cycle. 5. A DMA controller that enables direct memory access, a first buffer that can hold data in a first-in first-out format, a second buffer that can hold output data from the first buffer, and the first buffer. Control L including a data selection unit for selectively supplying the output data from the second buffer and the output data from the second buffer to the DMA controller.
In the case of SI, the DMA controller transfers the storage data of the first buffer to the bus control unit via the data selection unit in response to a transfer request signal from the first buffer, In response to a retry request, a communication control LSI including a buffer control unit for controlling transfer of stored data in the second buffer to the bus control unit via the data selection unit. 6. A DMA controller which enables direct memory access, and a buffer capable of holding received data according to an instruction of a pointer, wherein the DMA controller is DMA provided that there is no retry request from the outside. A communication control LSI, comprising: a buffer control unit capable of retransmitting received data in response to a retry request by updating the pointer of the buffer before starting transfer. 7. A DMA controller that enables direct memory access, and a buffer that can hold received data according to an instruction from a pointer, wherein the DMA controller is a buffer control that can move the pointer backward in response to a retry request. A communication control LSI including a part. 8. A first buffer capable of holding input data in a first-in first-out format, a second buffer capable of holding output data from the first buffer, output data of the first buffer or output data of the second buffer. And a DMA controller capable of controlling the DMA transfer by inputting the data selected by the selecting means. The DMA controller includes a bus control unit for data transfer, the first and the second controller. 2) a buffer control unit for accessing the buffer, and a state control unit for performing state transition control for the bus control unit and the buffer control unit. From the information input for the control state transition by the state control unit to its input Is reflected in the new control state in a shorter time than the state transition control cycle of the state control section, and the state control section A semiconductor integrated circuit, characterized in that the selection means is caused to select the output data of the second buffer in response to a retry request for transmission control. 9. A buffer capable of holding input data in a first-in first-out format, and a DMA controller capable of inputting data output from said buffer and controlling DMA transfer.
The DMA controller includes a bus control unit for data transfer, a buffer control unit for accessing the buffer, and a state control unit for performing state transition control on the bus control unit and the buffer control unit. , The time from the input of information for the control state transition by the state control unit until the input is reflected in a new control state is shorter than the state transition control cycle of the state control unit, and the state control unit A semiconductor integrated circuit characterized in that a read pointer of the buffer is changed to a value indicating a retry target data in response to a transfer control retry request. 10. A buffer capable of holding input data in a first-in first-out format and a DMA controller capable of controlling DMA transfer by inputting data output from said buffer, said DMA controller being for data transfer. A bus control unit, a buffer control unit for accessing the first and second buffers, and a state control unit that performs state transition control for the bus control unit and the buffer control unit. A semiconductor integrated circuit, wherein the time from the input of information for a transition to the reflection of the input in a new control state is shorter than the state transition control cycle of the state control section.