JP3709355B2 - Clock synchronization system and method - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to a technology for synchronizing LSI clocks on a card between LSIs on each card, and in particular, synchronizes LSI clocks mounted on a card used in a multiprocessor system between LSIs on each card. It is related to the technology.
[0002]
[Prior art]
In a multiprocessor system composed of a plurality of processor cards, the same clock is supplied to the LSIs from the outside in order to synchronize the LSIs of the processor cards. Therefore, when the current clock frequency is changed, the changed clock must be supplied to the LSI. Therefore, in addition to a pin for inputting the current clock, each LSI is previously provided with a pin for inputting the changed clock.
[0003]
[Problems to be solved by the invention]
However, if it is predicted that the clock frequency will be changed as described above and pins are provided in the LSI, there is a problem that the number of pins of the LSI increases.
[0004]
Therefore, the problem to be solved by the present invention is that the frequency of the clock used in each LSI can be arbitrarily changed without providing an extra pin in the LSI of each card. An object of the present invention is to provide a technique capable of synchronizing LSIs.
[0005]
[Means for Solving the Problems]
The object is a system that includes a first substrate and a second substrate, and synchronizes a clock phase in a circuit on the first substrate with a clock phase in a circuit on the second substrate. ,
The first substrate is
First clock generation means for generating a clock in which the period of an external clock input from the outside is n-fold;
Transmission means for transmitting predetermined data in accordance with the clock generated by the first clock generation means,
The second substrate is
Second clock generating means for generating a clock in which the period of an external clock input from the outside is set to n times the period;
Receiving means for receiving data in accordance with the clock generated by the second clock generating means;
If the receiving means cannot receive the predetermined data within a predetermined time after the transmitting means transmits the predetermined data, the receiving means receives the predetermined data within the predetermined time. And a delay means for delaying the rising edge of the clock generated by the second clock generation means by one period of the external clock .
[0006]
In particular, the transmission means of the first substrate is
A counter that starts counting according to the clock generated by the first clock generation means;
When the count value of the counter reaches a predetermined value, the predetermined data is transmitted.
[0007]
The receiving means of the second substrate is
A counter that starts counting according to the clock generated by the second clock generation means;
Data is received when the count value of the counter reaches a predetermined value.
[0009]
The problem is a board used in a clock synchronization system that synchronizes the phase of a clock in a circuit on the board between the boards,
Clock generating means for generating a clock in which the period of an external clock input from the outside is n-fold;
Transmitting / receiving means for transmitting / receiving predetermined data in accordance with the clock generated by the clock generating means;
Generating the clock so that the receiving means receives the predetermined data within the predetermined time if the transmitting / receiving means cannot receive the predetermined data within a predetermined time after the predetermined data is transmitted; The clock rise generated by the means is solved by a substrate having delay means for delaying the external clock by one period .
[0010]
In particular, the transmission / reception means includes:
A counter that starts counting according to the clock generated by the clock generation means;
When the count value of the counter reaches a predetermined value, the predetermined data is transmitted / received.
[0012]
The problem is a clock synchronization method for synchronizing the phase of a clock in a circuit on a board between the boards in each board of a multiprocessor system including a plurality of boards on which a processor is mounted,
A step of generating a clock in which each substrate has a period of n times the external clock input from the outside;
A predetermined substrate among the plurality of substrates is set as a reference substrate, and the reference substrate transmits predetermined data in accordance with a clock generated by itself;
When a board other than the reference board cannot receive the predetermined data at a predetermined time after the predetermined data is transmitted, the rising edge of the clock generated by itself is delayed by one cycle of the external clock. And a step of receiving predetermined data within the predetermined time . This is solved by the clock synchronization method.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described.
[0014]
FIG. 1 is a block diagram for explaining an embodiment of the present invention. FIG. 2 is a time chart for explaining the embodiment of the present invention. FIG. 3 is a block diagram of the diagnosis control unit. FIG. 4 is a time chart for explaining a definator signal generated by each CPU card. FIG. 5 is a block diagram of the phase counter of the inter-cell control unit. FIG. 6 is a time chart for explaining a refiner signal generated by the inter-cell control unit. FIG. 7 is a flowchart for explaining the operation of the embodiment of the present invention. FIG. 8 is a flowchart for explaining the operation of the embodiment of the present invention. 9 to 11 are time charts for explaining the operation of the embodiment of the present invention.
[0015]
As shown in FIG. 1, the multiprocessor system includes CPU cards 1 to 4 on which a plurality of processors and a main memory are mounted, and a cable 100 that connects the CPU cards 1 to 4.
[0016]
In the multiprocessor system of the present invention, when the transfer rate (minimum delay 2 clocks, maximum delay 4 clocks) of the cable 100 is satisfied, the data transmitted from the CPU card is 4 clocks as shown in FIG. It is received by another CPU card after (clock inside the inter-cell control unit described later). The CPU card on the transmission side holds the transmitted data for two clocks so that the data can be reliably sent and received between the CPU cards. On the other hand, when the transfer rate of the cable 100 is not satisfied, the data transmitted from the CPU card is received by another card as indefinite data.
[0017]
The CPU cards 1 to 4 are CPUs 11 to 26, diagnostic control units 111 to 114 that perform diagnostic control and startup operations for the CPU cards 1 to 4, and cells that control data transmission and reception between the CPU cards 1 to 4. The control units 121 to 124 include processor control units 131 to 134 that perform arbitration control of the CPUs 11 to 26 and cache coherency control.
[0018]
Next, the configuration of the diagnosis control units 111 to 114 will be described in detail.
[0019]
The diagnosis control units 111 to 114 operate with a clock synchronized between the CPU cards 1 to 4 (hereinafter, this clock is referred to as a system clock), and as shown in FIG. And definer generation counters 1112 to 1142.
[0020]
The frequency of the system clock is 1/3 of the internal clock in the inter-cell controllers 121-124.
[0021]
The definer switching registers 1111 to 1141 can arbitrarily change the register values, and change the generation timing of the definer signal generated by the definer generation counters 1112 to 1142. Here, the definator signal refers to a clock in which the period of the clock inside the LSI (for example, diagnostic control unit, inter-cell control unit) in the CPU card is set to n times.
[0022]
The refiner generation counters 1112 to 1142 increment the count value according to the system clock.
[0023]
Then, when the count value reaches a certain value, the definer generation counters 1112 to 1142 generate a refiner signal that is synchronized with the system clock and has a system clock cycle of n times. For example, if the number of CPU cards (number of cells) is four and the definator switching register 1111 is set to “0”, the definer generation counter 1112 counts the same number of cells as shown in FIG. (0, 1, 2, 3), and when the count value of the definer generation counter 1112 coincides with the value (0) set in the definer switching register 1111, a definer signal that becomes “Hi” is generated. In this way, the diagnosis control units 111 to 114 generate a refiner signal in which the system clock period is four times as long.
[0024]
Then, the diagnosis control units 111 to 114 transmit the generated refiner signal to the inter-cell control units 121 to 124.
[0025]
Since the definator signals of the diagnosis control units 111 to 114 are generated by the definator generation counters 1112 to 1142, if the count values of the definator generation counters 1112 to 1142 do not match, the definer of the diagnosis control units 111 to 114 The signal is not synchronized between the diagnosis control units 111 to 114.
[0026]
Further, the diagnosis control units 111 to 114 receive data transmitted at a predetermined timing in order to synchronize the refiner signals generated by the diagnosis control units 111 to 114 with each other, and the definator signal is received from the received data. It is determined whether or not the phases are synchronized between the diagnosis control units 111 to 114.
When the phase of the definator signal is synchronized between the diagnosis control units 111 to 114, the diagnosis control units 111 to 114 maintain the values of the definer switching registers 1111 to 1141, and finish the synchronize operation of the definer signal. .
[0027]
On the other hand, when the phase of the definator signal is not synchronized between the diagnosis control units 111 to 114, the diagnosis control units 111 to 114 determine whether or not the values of the definator switching registers 1111 to 1141 have been updated a predetermined number of times. .
[0028]
When the values of the definator switching registers 1111 to 1141 are updated a predetermined number of times, the diagnosis control units 111 to 114 cannot synchronize the phases of the refiner signals generated by the diagnosis control units 111 to 114 with each other. And the synchronize operation of the definer signal is terminated.
[0029]
On the other hand, when the values of the definator switching registers 1111 to 1141 have not been updated a predetermined number of times, the diagnosis control units 111 to 114 update the values of the definer switching registers 1111 to 1141 and the phase of the definer signal (rise of the definer signal) Is shifted by one cycle of the system clock, and the fact that the values of the definer switching registers 1111 to 1141 are updated once is stored.
[0030]
In the embodiment of the present invention, data is transmitted and received between the CPU cards 1 to 4 within 4 clocks (system clocks). Therefore, the diagnosis control units 111 to 114 have the definer switching register 1111 at the maximum. By updating the value of ˜1141 three times, the phases of the own refiner signal can be synchronized among the CPUs 1 to 4.
[0031]
Next, the configuration of the inter-cell controllers 121 to 124 will be described in detail.
[0032]
The inter-cell controllers 121 to 124 include phase counters 1211 to 1241 for generating a refiner signal in which the cycle of its own internal clock is set to k times.
[0033]
It should be noted that normal data transmission / reception is performed between the CPU cards 1 to 4 only when the phase of the refiner signal is synchronized between the inter-cell controllers 121 to 124.
[0034]
As shown in FIG. 5, the phase counters 1211 to 1241 correspond to the counters 1212 to 1242 that are incremented by carry from the definer generation counters 1112 to 1142 and the clock ratio (1: k), and are incremented by the internal clock. Counters 1213 to 1243, and these counters are reset by a signal obtained by differentiating the refiner signals from the diagnosis control units 111 to 114. For example, when the count value of the definer generation counter 1112 is counted as “0, 1, 2, 3” and the clock ratio of the inter-cell control unit 121 is 1: 2, the counter 1212 and the counter 1213 are first diagnosed. The count value is reset to “0” with a signal obtained by differentiating the refiner signals from the control units 111 to 114. The count value of the counter 1212 is first “1” when the count value of the definator generation counter 1112 is “1”, and next becomes “2” when the count value of the definator generation counter 1112 is “2”. Further, when the count value of the definer generation counter 1112 is “3”, it becomes “3”. On the other hand, the count value of the counter 1213 is counted in synchronization with the internal clock of the inter-cell control unit 111 and becomes “0, 1, 2”. Here, the relationship between the count value of the counter 1212 and the count value of the counter 1213 is that the internal clock of the inter-cell control unit 111 has a frequency three times that of the system clock. In addition, the count value of the counter 1213 becomes “0, 1, 2”, and then the count value of the counter 1212 becomes “0, 1, 2” while the count value of the counter 1212 is “1”. While the value is 2, the count value of the count 1213 is “0, 1, 2”, and finally the count value of the counter 1212 is 3, while the count value of the count 1213 is “0, 1, 2”. There is such a relationship. Then, the values counted by the counter 1212 and the counter 1213 are combined and output as the count values “00, 01, 02, 10, 11, 12, 20, 21, 21, 22, 30, 31, 32” of the phase counter 1211. .
[0035]
Furthermore, the inter-cell controllers 121 to 124 sample arbitrary values of the phase counters 1211 to 1214 to generate a refiner signal. For example, when generating a refiner signal in which the cycle of the internal clock of the inter-cell controllers 121 to 124 is doubled, as shown in FIG. 6, the values of the phase counters 1112 to 1142 are “00, 02, 11, When 20, 22, 31 ", a refiner signal that becomes" Hi "is generated.
[0036]
Thus, the definer signal generated by the inter-cell controllers 121-124 is generated in accordance with the definer signal generated by the diagnostic controllers 111-114, so that the definer signal generated by the diagnostic controllers 111-114 is the diagnostic controller. If synchronization is performed between 111 to 111, the refiner signal generated by the inter-cell control units 121 to 124 is also synchronized between the inter-cell control units 121 to 124.
[0037]
Further, the inter-cell controllers 121 to 124 set data “1” at a predetermined timing in order to synchronize the refiner signals generated by the diagnostic controllers 111 to 114 between the diagnostic controllers 111 to 114. Send the set data.
[0038]
Further, the inter-cell controllers 121 to 124 receive data at a predetermined timing, and hold this data until the next predetermined timing. For example, as illustrated in FIG. 7, when data is transmitted from the CPU card 1 and the transmitted data is received by the CPU card 2, the inter-cell control unit 121 of the CPU card 1 indicates that the value of the phase counter 1211 is “ When “30” (timing 1 and 13), data “1” is set in the I / O buffer. When the value of the phase counter 1211 is “00” (timing 4 and 16), data “0” is set to I / O. Set in the buffer and send the set data. Then, the inter-cell control unit 122 of the CPU card 2 receives data when the value of the phase counter 1221 is “01”, and receives the received data until the value of the phase counter 1221 further becomes “01”. Hold in O buffer. Further, the diagnosis control unit 112 refers to the data in the I / O buffer to determine whether or not the data is “1”. If the data is not “1”, the diagnostic control unit 112 updates the value of the definer switching register 1121. Shifts the phase of its own refiner signal by one cycle of the system clock.
[0039]
Next, the operation in the above configuration will be described.
[0040]
First, the diagnosis control units 111 to 114 of the CPU cards 1 to 4 synchronize the phases of their own refiner signals between the diagnosis control units 111 to 114, so that data “1” is sent from the CPU card 1 at a predetermined timing. Send.
[0041]
The inter-cell controllers 122 to 124 of the CPU cards 2 to 4 hold the data transmitted from the CPU card 1 in the I / O buffer.
[0042]
Then, the diagnosis control units 112 to 114 for the data refer to the data held in the I / O buffer, and determine whether or not the referred data is “1” (Step 101).
[0043]
When the received data is “1” (in the case of YES), it indicates that the phase of the definator signal is synchronized between the diagnosis control units 111 to 114, so that the diagnosis control unit 112 to 114 The synchronization process is terminated (Step 102).
[0044]
On the other hand, when the received data is “0” (in the case of NO), it indicates that the phase of the definer signal is not synchronized between the diagnosis control units 111 to 114. It is determined whether or not the values of 1121 to 1141 have been updated three times (Step 103).
[0045]
When the value of the definator switching register 1121 to 1141 is updated three times (in the case of YES), it indicates that the phase of the definer signal cannot be synchronized between the diagnosis control units 111 to 114. 112-114 complete | finish the synchronizing process of a refiner signal (Step 104).
[0046]
On the other hand, when the values of the definator switching registers 1121 to 1141 have not been updated three times (in the case of NO), the diagnosis control units 112 to 114 update the values of the definer switching registers 1111 to 1141 and change the phase of the definer signal for one cycle. Shift (Step 105).
[0047]
Then, after shifting the phase of the definator signal by one cycle, the diagnosis control units 112 to 114 store that the values of the definator switching registers 1121 to 1141 have been changed once (Step 106), and then continue to Step 101 to Step 106. repeat.
[0048]
Next, in order to specifically describe the definer signal synchronization processing, a case where the phase of the definator signal of the diagnosis control unit 111 and the phase of the definer signal of the diagnosis control unit 112 are synchronized will be described.
[0049]
In the following description, as shown in FIG. 9, it is assumed that the phase difference between the phase of the definator signal of the diagnosis control unit 111 and the phase of the definer signal of the diagnosis control unit 112 is equivalent to three periods of the system clock. .
[0050]
First, as shown in FIG. 9, the inter-cell control unit 121 of the CPU card 1 becomes “Hi” when the count value of the phase counter 1211 is “00, 30” (timing 1, 4, 13, 16). Generate a refiner signal. Using this generated refiner signal as a trigger, the inter-cell control unit 121 sets the data “1” in the I / O buffer when the count value of the phase counter 1211 is “30”, and the count value of the phase counter 1211 is “ When “00”, data “0” is set in the I / O buffer. Then, the inter-cell control unit 121 transmits the set data.
[0051]
On the other hand, the inter-cell control unit 122 of the CPU card 2 generates a refiner signal that becomes “Hi” when the count value of the phase counter 1221 is “01” (timing 8 and 20). Using this generated refiner signal as a trigger, the inter-cell controller 1221 receives data transmitted from the CPU card 1 when the value of the phase counter 1211 is “01”, and holds the received data in the I / O buffer. To do.
[0052]
Then, the diagnosis control unit 112 of the CPU card 2 refers to the data held in the I / O buffer and determines whether or not this data is “1”.
[0053]
Further, since the data held in the I / O buffer is “0”, the diagnosis control unit 112 increments the value of the definator switching register 1121 and changes the phase of its own definator signal to one cycle of the system clock. Shift by minutes.
[0054]
As a result, the phase difference between the phase of the definator signal of the diagnosis control unit 111 and the phase of the definer signal of the diagnosis control unit 112 becomes two periods of the system clock.
[0055]
Subsequently, as shown in FIG. 10, the inter-cell control unit 122 receives data (when the count value of the phase counter 1221 is “01”) triggered by the definer signal, and receives the received data as an I / O buffer. Hold with.
[0056]
Then, the diagnosis control unit 112 refers to the data held in the I / O buffer, and determines whether or not this data is “1”.
[0057]
Further, since the data held in the I / O buffer is “0”, the diagnosis control unit 112 increments the value of the definator switching register 1121 and changes the phase of its own definator signal to one cycle of the system clock. Shift by minutes.
[0058]
As a result, the phase difference between the phase of the definator signal of the diagnosis control unit 111 and the phase of the definator signal of the diagnosis control unit 112 becomes one cycle of the system clock.
[0059]
Again, as shown in FIG. 11, the inter-cell control unit 122 receives data with the refiner signal as a trigger (when the count value of the phase counter 1221 is “01”), and receives the received data as an I / O buffer. Hold with.
[0060]
Then, the diagnosis control unit 112 refers to the data held in the I / O buffer, and determines whether or not this data is “1”.
[0061]
Further, since the data held in the I / O buffer is “0”, the diagnosis control unit 112 increments the value of the definator switching register 1121 and changes the phase of its own definator signal to one cycle of the system clock. Shift by minutes.
[0062]
Thereby, the phase of the definator signal of the diagnosis control unit 111 and the phase of the definer signal of the diagnosis control unit 112 are synchronized.
[0063]
Finally, in order to determine that the phase of the refiner signal is synchronized between the diagnosis control units 111 and 112, the inter-cell control unit 122 uses the definer signal as a trigger (the count value of the phase counter 1221 is “01”). Data) is received, and the received data is held in the I / O buffer.
[0064]
Then, the diagnosis control unit 112 refers to the data held in the I / O buffer, and determines whether or not this data is “1”.
[0065]
Further, as shown in FIG. 7, the diagnosis control unit 112 has the value of the data held in the I / O buffer as “1”, so the phase of the refiner signal of the inter-cell control unit 121 and the inter-cell control unit 122. It is determined that the phase of the refiner signal is synchronized, and the synchronization process of the refiner signal is terminated.
[0066]
In this way, an n-times cycle clock (definer signal) is generated by the LSI of each CPU card without supplying an n-cycle clock (1 / n frequency clock) synchronized between the CPU cards from the outside. The phase of the generated refiner signal can be synchronized between the LSIs.
[0067]
In addition, since the definer signals of the inter-cell controllers 121 to 124 are generated based on the internal clock, even if the definer signal frequency is changed, the definer signal having the changed frequency can be generated.
[0068]
In the embodiment of the present invention, the case where the count values of the definator generation counters 1112 to 1142 and the phase counters 1211 to 1241 are incremented has been described. However, the present invention is not limited to this case. For example, the count values of the refiner generation counters 1112 to 1142 and the phase counters 1211 to 1241 may be decremented.
[0069]
【The invention's effect】
According to the present invention, since the existing interface is used to synchronize the phase of the n-fold clock generated by the LSI of the card between the LSIs, the number of LSI pins can be reduced. Excellent effect.
[0070]
In addition, according to the present invention, an n-times clock in the LSI is generated based on the internal clock, so that it is necessary to supply a new clock to the LSI even if the clock frequency is changed in the future. There is an excellent effect that there is no.
[Brief description of the drawings]
FIG. 1 is a block diagram for explaining an embodiment of the present invention.
FIG. 2 is a time chart for explaining an embodiment of the present invention.
FIG. 3 is a block diagram of a diagnosis control unit.
FIG. 4 is a time chart for explaining a refiner signal generated by each CPU card.
FIG. 5 is a block diagram of a phase counter of the inter-cell control unit.
FIG. 6 is a time chart for explaining a refiner signal generated by an inter-cell control unit;
FIG. 7 is a flowchart for explaining the operation of the exemplary embodiment of the present invention.
FIG. 8 is a flowchart for explaining the operation of the exemplary embodiment of the present invention.
FIG. 9 is a time chart for explaining the operation of the exemplary embodiment of the present invention.
FIG. 10 is a time chart for explaining the operation of the exemplary embodiment of the present invention.
FIG. 11 is a time chart for explaining the operation of the exemplary embodiment of the present invention.
[Explanation of symbols]
1 CPU Card 111 Diagnosis Control Unit 1111 Definer Switching Register 1112 Definer Generation Counter 121 Inter-cell Control Unit 1211 Phase Counter

Claims (6)

A system having a first board and a second board, and synchronizing a clock phase in a circuit on the first board and a clock phase in a circuit on the second board,
The first substrate is
First clock generation means for generating a clock in which the period of an external clock input from the outside is n-fold;
Transmission means for transmitting predetermined data in accordance with the clock generated by the first clock generation means,
The second substrate is
Second clock generating means for generating a clock in which the period of an external clock input from the outside is set to n times the period;
Receiving means for receiving data in accordance with the clock generated by the second clock generating means;
When the receiving means cannot receive the predetermined data within a predetermined time after the transmitting means transmits the predetermined data, the receiving means receives the predetermined data within the predetermined time. And a delay means for delaying the rising edge of the clock generated by the two clock generation means by one period of the external clock . The transmission means of the first substrate is
The counter has a counter that starts counting according to the clock generated by the first clock generation means, and is configured to transmit the predetermined data when the count value of the counter reaches a predetermined value. The clock synchronization system of claim 1.   The receiving means of the second board has a counter that starts counting according to the clock generated by the second clock generating means, and is configured to receive data when the count value of the counter reaches a predetermined value. The clock synchronization system according to claim 1, wherein: A board used in a clock synchronization system that synchronizes the phase of a clock in a circuit on a board between each board,
  Clock generating means for generating a clock in which the period of an external clock input from the outside is set to n times;
  Transmitting / receiving means for transmitting / receiving predetermined data in accordance with the clock generated by the clock generating means;
  Generating the clock so that the receiving means receives the predetermined data within the predetermined time if the transmitting / receiving means cannot receive the predetermined data within a predetermined time after the predetermined data is transmitted; And a delay means for delaying the rising edge of the clock generated by the means by one period of the external clock. The transmission / reception means includes
  A counter that starts counting according to the clock generated by the clock generation means;
  5. The substrate according to claim 4, wherein the predetermined data is transmitted / received when a count value of the counter reaches a predetermined value. A clock synchronization method for synchronizing the phase of a clock in a circuit on a board between each board in each board of a multiprocessor system composed of a plurality of boards equipped with a processor,
  A step of generating a clock in which each board has a cycle of an external clock input from the outside, multiplied by n times;
  A step of setting a predetermined substrate of the plurality of substrates as a reference substrate, and the reference substrate transmitting predetermined data in accordance with a clock generated by the device;
  A board other than the reference board is sent a predetermined time after the predetermined data is transmitted. If the predetermined data cannot be received, delaying the rising edge of the self-generated clock by one period of the external clock and receiving the predetermined data within the predetermined time;
A clock synchronization method comprising:

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