JP2006013596A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance throughput while suppressing the occurrence of data error during transmission of data between CPUs. <P>SOLUTION: CPUs are connected through a simultaneous bidirectional I/O circuits 1 and 2, clock signal ϕ0 generated from a PLL circuit 3 is input to the transmission clock terminal TXclock1 of the simultaneous bidirectional I/O circuit 1, clock signal ϕ0 generated from the PLL circuit 3 is input through a clock line CL1 and a buffer 4 to the transmission clock terminal TXclock2 and reception clock terminal RXclock2 of the simultaneous bidirectional I/O circuit 2, and clock signal ϕ0 generated from the PLL circuit 3 is input through the clock line CL1, the buffers 4 and 5 and a clock line CL2 to the reception clock terminal RXclock1 of the simultaneous bidirectional I/O circuit 1 and fed back to the PLL circuit 3. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit, and is particularly suitable for application to a method using a simultaneous bidirectional input / output interface for interconnection between CPUs (Central Processing Units).

2. Description of the Related Art In semiconductor integrated devices, ALU (Arithmetic and Logical Unit) and multi-bit buses are used to improve processing capability. In addition, as the amount of data handled in graphic processing increases, the bandwidth of the bus necessary for data processing increases year by year.
Further, for example, in Patent Document 1, in order to reduce the area occupied by a bus, a plurality of CPUs are connected to an n-bit bus, and when one CPU is accessing a memory, the other CPU is in a standby state. Thus, a method for preventing data collision is disclosed.

Further, for example, Patent Document 2 discloses a method of using a bidirectional data bus in the multiprocessor system while arbitrating in order to deal with the restriction on the number of bus lines.
For example, Patent Document 3 discloses a method of reducing the occupied area of a bus by performing serial / parallel conversion in a chip when data communication is performed between processors.

Further, for example, Patent Document 4 discloses a method of connecting CPUs via a serial interface or a parallel interface and exchanging data between CPUs by handshake.
Further, for example, in Patent Document 5, in order to reduce the occupied area of the data bus while suppressing a decrease in throughput, data transmission / reception can be made the same by using a simultaneous bidirectional input / output circuit. A method is disclosed that allows simultaneous execution on the bus.
Japanese Patent Laid-Open No. 2-300955 JP 2003-296267 A JP 2003-198356 A JP 58-64528 A JP-A-8-316815

However, in the methods disclosed in Patent Documents 1 to 4, a data bus is shared among a plurality of CPUs in order to reduce the occupied area of the bus. For this reason, when any one CPU is performing a data transmission operation, the other CPUs must stop the transmission operation, and there is a problem in that the throughput when data is exchanged between the CPUs is reduced.
Further, in the method disclosed in Patent Document 5, even if data is transferred from both CPUs at an arbitrary timing, the data needs to be transmitted to the CPU of the other party. Both CPUs are required to limit the necessary setup time and hold time. For this reason, when using a simultaneous bidirectional input / output circuit, it is necessary to secure a timing margin that is several times the number of CPUs connected compared to using a bus that transfers data only in a single direction. There is a problem that the transfer operation frequency of the CPU has to be lowered.

FIG. 7 is a diagram showing the setup time and hold time during data transfer.
In FIG. 7, in order to ensure that data can be taken in at the rising edge of the clock, the clock frequency needs to satisfy the restrictions of the setup time Tsu and the hold time Th. In other words, it is necessary to determine the data potential at a time sufficiently earlier than the time when the clock potential changes and to secure the time necessary for the data to be taken into the internal latch after the clock rises. is there. For example, in the example of FIG. 7, since the setup time Tsu and the hold time Th are satisfied at the rising edge of the first clock, the data “0” can be captured, but at the rising edge of the second clock, the setup time Tsu. Since the hold time Th is not satisfied, the data “0” may not be captured.

In the method disclosed in Patent Document 5, independent and separate clocks are used to operate both CPUs. For this reason, there is a problem in that the probability of occurrence of data errors increases with the least common multiple of the clock periods as the period, which causes a decrease in overall throughput.
Furthermore, the method disclosed in Patent Document 5 has a problem that the probability of timing error increases due to the delay time due to the wiring length between CPUs.

Further, in the method disclosed in Patent Document 5, transmission is performed by attracting the potential of the data between the buffers of the data bus connected to both CPUs, so that the rise and fall times of the data become long, There was a problem that the probability of an error with respect to the setup time was increased.
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit capable of improving throughput while suppressing occurrence of data errors during data transmission between CPUs.

In order to solve the above-described problem, according to a semiconductor integrated circuit according to an aspect of the present invention, a plurality of CPUs mounted on the same chip and a simultaneous bidirectional input / output interface that interconnects the CPUs are provided. It is characterized by providing.
As a result, data can be transmitted and received between CPUs mounted on the same chip simultaneously on the same bus, and the area occupied by the data bus can be reduced while suppressing a decrease in throughput.

The semiconductor integrated circuit according to one aspect of the present invention includes a simultaneous bidirectional input / output interface driven by a single clock and a plurality of CPUs connected via the simultaneous bidirectional input / output interface. It is characterized by providing.
As a result, it is possible to match the timing at which data is transmitted and received on the same bus between both CPUs. This makes it possible to satisfy the setup time and hold time requirements necessary to reliably capture data in both CPUs, and improve throughput while suppressing the occurrence of data errors during data transmission between CPUs. It becomes possible.

  In the semiconductor integrated circuit according to one aspect of the present invention, the simultaneous bidirectional input / output interface includes a first simultaneous bidirectional input / output circuit disposed on the first CPU side and a first simultaneous bidirectional input / output circuit disposed on the second CPU side. 2 simultaneous bidirectional input / output circuits and transmission data captured by the first simultaneous bidirectional input / output circuit are transmitted to the second simultaneous bidirectional input / output circuit and captured by the second simultaneous bidirectional input / output circuit. A transmission line transmitted to the first simultaneous bidirectional input / output circuit and a delay time of a signal transmitted via the bus line to the first and second simultaneous bidirectional input / output circuits. And phase compensation means for shifting the phases of the input clocks from each other.

As a result, even when there is a signal propagation delay due to the wiring length between CPUs, it is possible to match the timing at which data is transmitted and received on the same bus between both CPUs. Throughput can be improved while suppressing the occurrence of data errors.
Further, according to the semiconductor integrated circuit of one embodiment of the present invention, the first simultaneous bidirectional input / output circuit disposed on the first CPU side and driven by the first clock is disposed on the second CPU side, and the first CPU A second simultaneous bidirectional input / output circuit driven by a second clock having a phase different from that of the clock by a predetermined amount; and the second simultaneous bidirectional input / output circuit for transmitting transmission data captured by the first simultaneous bidirectional input / output circuit. And a bus line for transmitting the transmission data taken into the second simultaneous bidirectional input / output circuit to the first simultaneous bidirectional input / output circuit.

  This makes it possible to shift the phase of the clock input to the first and second simultaneous bidirectional input / output circuits in accordance with the timing at which signals are transmitted and received in the first and second simultaneous bidirectional input / output circuits. . For this reason, even when there is a signal propagation delay due to the wiring length of the bus line between the first and second simultaneous bidirectional input / output circuits, the first simultaneous bidirectional input / output circuit to the second simultaneous bidirectional input / output circuit. It is possible to make the timing for sending a signal coincide with the timing for receiving the signal sent from the second simultaneous bidirectional input / output circuit by the first simultaneous bidirectional input / output circuit. As a result, the first and second simultaneous bidirectional input / output circuits can satisfy the requirements of the setup time and hold time necessary for reliably capturing data, and the first and second simultaneous bidirectional input / output circuits. Data can be transmitted and received between circuits simultaneously on the same bus, and throughput can be improved while suppressing the occurrence of data errors during data transmission between CPUs.

  According to the semiconductor integrated circuit of one aspect of the present invention, the clock signal generating unit that generates the clock signal and the rising edge or the falling edge of the clock generated by the clock signal generating unit A first simultaneous bidirectional input / output circuit that captures transmission data in synchronization and outputs reception data in synchronization with either the rising edge or falling edge of the clock generated by the clock signal generation means; The first simultaneous bidirectional input / output circuit captures transmission data in synchronization with an edge different from the rising edge or falling edge of the clock when reception data is output from the first simultaneous bidirectional input / output circuit. Clock rising edge or falling edge when transmit data is captured A second simultaneous bidirectional input / output circuit that outputs received data in synchronization with an edge different from the first and second simultaneous bidirectional input / output circuits. And a bus line for transmitting the transmission data taken into the second simultaneous bidirectional input / output circuit to the first simultaneous bidirectional input / output circuit.

  As a result, it is possible to shift the timing at which transmission data is taken into the first simultaneous bidirectional input / output circuit and the timing at which reception data is output from the second simultaneous bidirectional input / output circuit. It is possible to shift the timing at which transmission data is taken into the direction input / output circuit and the timing at which reception data is output from the first simultaneous bidirectional input / output circuit. For this reason, it is possible to output the reception data from the second simultaneous bidirectional input / output circuit after the transmission data taken into the first simultaneous bidirectional input / output circuit is transmitted to the second simultaneous bidirectional input / output circuit. In addition, it is possible to output the received data from the first simultaneous bidirectional input / output circuit after the transmission data taken into the second simultaneous bidirectional input / output circuit is transmitted to the first simultaneous bidirectional input / output circuit. Even when data transmission / reception between CPUs is performed simultaneously on the same bus, it is possible to improve throughput while suppressing the occurrence of data errors during data transmission.

  Further, according to the semiconductor integrated circuit of one aspect of the present invention, the clock signal generating unit that generates the clock signal based on the comparison result between the reference signal and the feedback signal, and the clock generated by the clock signal generating unit A first simultaneous bidirectional input / output circuit to which a signal is input; and a second simultaneous bidirectional input / output circuit to which a clock signal input to the first simultaneous bidirectional input / output circuit is input via a first clock line; , A second clock line for feeding back a clock signal input to the second simultaneous bidirectional input / output circuit to the clock signal generating means, and transmission data captured by the first simultaneous bidirectional input / output circuit to the second A bus line for transmitting to the first simultaneous bidirectional input / output circuit and for transmitting transmission data taken into the second simultaneous bidirectional input / output circuit to the simultaneous bidirectional input / output circuit; And wherein the Rukoto.

  Accordingly, it is possible to cause the clock signal generation unit to generate a clock signal in consideration of the delay time of the signal transmitted through the simultaneous bidirectional input / output interface. Therefore, even when there is a signal propagation delay due to the wiring length between the first and second simultaneous bidirectional input / output circuits, the timing at which data is transmitted and received by the first and second simultaneous bidirectional input / output circuits It becomes possible to match the phase of the clock signal, and it is possible to improve the throughput while suppressing the occurrence of data errors during data transmission between CPUs.

  Further, according to the semiconductor integrated circuit of one aspect of the present invention, the clock signal generating unit that generates the clock signal based on the comparison result between the reference signal and the feedback signal, and the clock generated by the clock signal generating unit A first simultaneous bidirectional input / output circuit to which a signal is input as a transmission clock, and a clock signal input to the first simultaneous bidirectional input / output circuit are transmitted as a transmission clock and a reception clock via a first clock line. The second simultaneous bidirectional input / output circuit to be inputted and the clock signal inputted to the second simultaneous bidirectional input / output circuit are fed back to the clock signal generating means and received by the first simultaneous bidirectional input / output circuit. A second clock line that is input as a clock for use in transmission, and transmission data captured by the first simultaneous bidirectional input / output circuit. As well as transmission, characterized in that it comprises a bus line for transmitting the transmission data taken into the second simultaneous bidirectional input-output circuit in the first simultaneous bidirectional input-output circuit.

  As a result, the first and second simultaneous bidirectional input / output circuits can be driven by a single clock, and the signal propagation delay is caused by the wiring length between the first and second simultaneous bidirectional input / output circuits. Correspondingly, the phase of the clock input to the first and second simultaneous bidirectional input / output times can be shifted. Therefore, even when there is a signal propagation delay due to the wiring length between the first and second simultaneous bidirectional input / output circuits, a signal is sent from the first simultaneous bidirectional input / output circuit to the second simultaneous bidirectional input / output circuit. The timing of sending and the timing of receiving the signal sent from the second simultaneous bidirectional input / output circuit by the first simultaneous bidirectional input / output circuit can be made coincident with each other and transmitted by the simultaneous bidirectional input / output interface. It is possible to cause the clock signal generation means to generate a clock signal in consideration of the delay time of the signal. As a result, the first and second simultaneous bidirectional input / output circuits can satisfy the requirements of the setup time and hold time necessary for reliably capturing data, and the first and second simultaneous bidirectional input / output circuits. Data can be transmitted and received between circuits simultaneously on the same bus, and throughput can be improved while suppressing the occurrence of data errors during data transmission between CPUs.

  Further, according to the semiconductor integrated circuit of one aspect of the present invention, the first simultaneous bidirectional input / output circuit is synchronized with either the rising edge or the falling edge of the clock signal input from the clock signal generation. The second simultaneous bidirectional input / output outputs the received data in synchronization with either the rising edge or the falling edge of the clock signal input via the second clock line. The circuit includes a rising edge or a rising edge of a clock when reception data is output from the first simultaneous bidirectional input / output circuit among rising edges or falling edges of a clock signal input via the first clock line. The transmission data is captured in synchronization with an edge different from the falling edge, and the first clock is received. Of the rising edge or falling edge of the clock signal input via the clock line, the edge different from the rising edge or falling edge of the clock when the transmission data is taken into the first simultaneous bidirectional input / output circuit. The received data is output synchronously.

  This makes it possible to shift the timing at which transmission data is captured in the first and second simultaneous bidirectional input / output circuits from the timing at which reception data is output, and the transmission captured in the first simultaneous bidirectional input / output circuit. After the data is transmitted to the second simultaneous bidirectional input / output circuit, the received data can be output from the second simultaneous bidirectional input / output circuit. For this reason, even when data transmission / reception is simultaneously performed between the first and second simultaneous bidirectional input / output circuits on the same bus, throughput is improved while suppressing occurrence of data errors during data transmission. It becomes possible.

  Further, according to the semiconductor integrated circuit of one aspect of the present invention, the clock signal generating unit that generates the first and second clock signals having different phases based on the comparison result between the reference signal and the feedback signal, The first simultaneous bidirectional input / output circuit to which the first clock signal generated by the clock signal generation means is input as a transmission clock, and the first clock signal input to the first simultaneous bidirectional input / output circuit is the first A second simultaneous bidirectional input / output circuit that is input as a reception clock via one clock line, and the second simultaneous bidirectional input / output using the second clock signal generated by the clock signal generation means as a transmission clock. A second clock line that is input to the circuit and a third clock that feeds back the first clock signal that is input to the second simultaneous bidirectional input / output circuit to the clock signal generating means. A line, a fourth clock line for inputting the second clock signal input to the second simultaneous bidirectional input / output circuit as a reception clock to the first simultaneous bidirectional input / output circuit, and the first simultaneous bidirectional input Transmission data captured by the output circuit is transmitted to the second simultaneous bidirectional input / output circuit, and transmission data captured by the second simultaneous bidirectional input / output circuit is transmitted to the first simultaneous bidirectional input / output circuit. And a bus line.

  This makes it possible to shift the phase of the clock input to the first and second simultaneous bidirectional input / output circuits in accordance with the timing at which signals are transmitted and received in the first and second simultaneous bidirectional input / output circuits. In addition, it is possible to cause the clock signal generation means to generate a clock signal in consideration of the delay time of the signal transmitted through the simultaneous bidirectional input / output interface. Therefore, even when there is a signal propagation delay due to the wiring length between the first and second simultaneous bidirectional input / output circuits, a signal is sent from the first simultaneous bidirectional input / output circuit to the second simultaneous bidirectional input / output circuit. It is possible to match the timing of sending with the timing of receiving the signal sent from the second simultaneous bidirectional input / output circuit by the first simultaneous bidirectional input / output circuit. As a result, the first and second simultaneous bidirectional input / output circuits can satisfy the requirements of the setup time and hold time necessary for reliably capturing data, and the first and second simultaneous bidirectional input / output circuits. Data can be transmitted and received between circuits simultaneously on the same bus, and throughput can be improved while suppressing the occurrence of data errors during data transmission between CPUs.

  Further, according to the semiconductor integrated circuit of one aspect of the present invention, the first simultaneous bidirectional input / output circuit is either the rising edge or the falling edge of the first clock signal input from the clock signal generation. The transmission data is captured in synchronization with the second clock signal, and the reception data is output in synchronization with either the rising edge or the falling edge of the second clock signal input via the fourth clock line. The bidirectional input / output circuit is configured to output the received data from the first simultaneous bidirectional input / output circuit among the rising edge or falling edge of the second clock signal input via the second clock line. The transmission data is captured in synchronization with the edge that is different from the rising edge or falling edge of the clock. Of the rising edge or falling edge of the first clock signal input via the first clock line, the rising edge or falling edge of the clock when the transmission data is taken into the first simultaneous bidirectional input / output circuit The reception data is output in synchronization with the edge different from the above.

  This makes it possible to shift the timing at which transmission data is captured in the first and second simultaneous bidirectional input / output circuits from the timing at which reception data is output, and the transmission captured in the first simultaneous bidirectional input / output circuit. After the data is transmitted to the second simultaneous bidirectional input / output circuit, the received data can be output from the second simultaneous bidirectional input / output circuit. For this reason, even when data transmission / reception is simultaneously performed between the first and second simultaneous bidirectional input / output circuits on the same bus, throughput is improved while suppressing occurrence of data errors during data transmission. It becomes possible.

Hereinafter, a semiconductor integrated circuit according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a schematic configuration of a semiconductor integrated circuit according to the first embodiment of the present invention.
In FIG. 1, a simultaneous bidirectional input / output circuit 1 is disposed on the first CPU side, and a simultaneous bidirectional input / output circuit 2 is disposed on the second CPU side. The simultaneous bidirectional input / output circuit 1, the simultaneous bidirectional input / output circuit 2 and the bus line IF1 are connected. The first CPU and the second CPU can be mounted on the same chip. Here, N data buses or address buses can be provided on the bus line IF1. The simultaneous bidirectional input / output circuit 1 and the simultaneous bidirectional input / output circuit 2 can simultaneously transmit and receive data on the bus line IF1.

  That is, the potential on the bus line IF1 is a ternary value of “0”, “0.5”, or “1” depending on the transmission / reception timing between the simultaneous bidirectional input / output circuit 1 and the simultaneous bidirectional input / output circuit 2. Can take the level. The transmission data transmitted from the simultaneous bidirectional input / output circuits 1 and 2 can take a binary level of “0” or “1”. In the simultaneous bidirectional input / output circuits 1 and 2 on the transmission side, it is known whether the level of transmission data currently being transmitted is “0” or “1”. Therefore, the level of the transmission data currently transmitted by the other party is determined by comparing the level of the transmission data currently transmitted on the bus line IF1 with the current level on the bus line IF1. Can do.

  That is, when the level of the transmission data currently transmitted on the bus line IF1 is “0” and the potential on the bus line IF1 is “0”, the level of the transmission data currently transmitted by the other party is “ It can be determined that it is 0 ″. Also, if the level of the transmission data currently transmitted on the bus line IF1 is “0” and the potential on the bus line IF1 is “0.5”, the level of the transmission data currently transmitted by the other party Can be determined to be “1”. Also, if the level of the transmission data currently transmitted on the bus line IF1 is “1” and the potential on the bus line IF1 is “0.5”, the level of the transmission data currently transmitted by the other party Can be determined to be “0”. Also, if the level of the transmission data currently being transmitted on the bus line IF1 is “1” and the potential on the bus line IF1 is “1”, the level of the transmission data currently transmitted by the other party is “1”. It can be determined that it is 1 ″.

  Here, the simultaneous bidirectional input / output circuit 1 is provided with a transmission clock terminal TXclock1 for instructing a timing for capturing the transmission data TXData1, and a reception clock terminal for instructing a timing for outputting the reception data RXData1. RXclock1 is provided. The simultaneous bidirectional input / output circuit 2 is provided with a transmission clock terminal TXclock2 for instructing a timing for capturing the transmission data TXData2, and a reception clock terminal RXclock2 for instructing a timing for outputting the reception data RXData2. Is provided.

  The transmission data TXData1 can be output from the first CPU to the simultaneous bidirectional input / output circuit 1, and the reception data RXData1 can be output from the simultaneous bidirectional input / output circuit 1 to the first CPU. The transmission data TXData2 can be output from the second CPU to the simultaneous bidirectional input / output circuit 2, and the reception data RXData2 can be output from the simultaneous bidirectional input / output circuit 2 to the second CPU.

  In addition, the semiconductor integrated circuit of FIG. 1 includes a PLL (Phase Lock Loop) circuit 3 that generates a clock signal φ0 based on a comparison result between the reference signal EXTclock and the feedback signal. Here, the clock signal φ 0 generated by the PLL circuit 3 is input to the transmission clock terminal TXclock 1 of the simultaneous bidirectional input / output circuit 1. The clock signal φ0 generated by the PLL circuit 3 is input to the transmission clock terminal TXclock2 and the reception clock terminal RXclock2 of the simultaneous bidirectional input / output circuit 2 via the clock line CL1 and the buffer 4. The clock signal φ0 generated by the PLL circuit 3 is input to the reception clock terminal RXclock1 of the simultaneous bidirectional input / output circuit 1 via the clock line CL1, the buffers 4, 5 and the clock line CL2, It is fed back to the PLL circuit 3.

  The signal propagation delay by the clock line CL1 and the buffer 4 is made to correspond to the time required for transmitting the signal from the simultaneous bidirectional input / output circuit 1 to the simultaneous bidirectional input / output circuit 2 via the bus line IF1. Can do. Further, the propagation delay of the signal by the clock line CL2 and the buffer 5 is made to correspond to the time required for transmitting the signal from the simultaneous bidirectional input / output circuit 2 to the simultaneous bidirectional input / output circuit 1 via the bus line IF1. Can do.

  The transmission data TXData1 input to the simultaneous bidirectional input / output circuit 1 is taken into the simultaneous bidirectional input / output circuit 1 in synchronization with the clock signal φ0 input to the transmission clock terminal TXclock1 (K1). The transmission data TXData1 taken into the simultaneous bidirectional input / output circuit 1 is transmitted to the simultaneous bidirectional input / output circuit 2 via the bus line IF1.

  Also, the transmission data TXData2 input to the simultaneous bidirectional input / output circuit 2 is synchronized with the clock signal φ0 input to the transmission clock terminal TXclock2 via the clock line CL1 and the buffer 4, and the simultaneous bidirectional input / output circuit. 2 (K2). The transmission data TXData2 captured by the simultaneous bidirectional input / output circuit 2 is transmitted to the simultaneous bidirectional input / output circuit 1 through the bus line IF1.

Here, in the simultaneous bidirectional input / output interface, transmission of the transmission data TXData1 from the simultaneous bidirectional input / output circuit 1 to the simultaneous bidirectional input / output circuit 2 and the simultaneous bidirectional input / output circuit 2 to the simultaneous bidirectional input / output circuit 1 are performed. The transmission of the transmission data TXData2 can be performed simultaneously on the same bus line IF1.
The simultaneous bidirectional input / output circuit 1 is currently transmitting by the counterpart simultaneous bidirectional input / output circuit 2 based on the level of the transmission data TXData1 that it is currently transmitting and the signal level on the data bus. The level of the transmission data TXData2 can be determined. The simultaneous bidirectional input / output circuit 1 outputs the reception data RXData1 in synchronization with the clock signal φ0 input to the reception clock terminal RXclock1 via the clock line CL1, the buffers 4, 5 and the clock line CL2 ( K3).

  In addition, the simultaneous bidirectional input / output circuit 2 transmits the current simultaneous transmission / reception input / output circuit 1 that the other party's simultaneous bidirectional input / output circuit 1 currently transmits based on the level of the transmission data TXData2 currently transmitted by itself and the signal level on the bus line IF1. The level of transmission data TXData1 that is present can be determined. The simultaneous bidirectional input / output circuit 2 outputs the reception data RXData2 in synchronization with the clock signal φ0 input to the reception clock terminal RXclock2 via the clock line CL1 and the buffer 4 (K2).

As a result, the simultaneous bidirectional input / output circuit 1 and the simultaneous bidirectional input / output circuit 2 can be driven by a single clock signal φ0, and the simultaneous bidirectional input / output circuit 1 and the simultaneous bidirectional input / output circuit can be driven. The phase of clocks input to the simultaneous bidirectional input / output circuit 1 and the simultaneous bidirectional input / output circuit 2 can be shifted in correspondence with the signal propagation delay due to the wiring length between the two.
For this reason, even when there is a signal propagation delay due to the wiring length between the simultaneous bidirectional input / output circuit 1 and the simultaneous bidirectional input / output circuit 2, the simultaneous bidirectional input / output circuit 1 to the simultaneous bidirectional input / output circuit 1 It is possible to match the timing for sending the transmission data TXData2 to the timing for receiving the transmission data TXData1 sent from the simultaneous bidirectional input / output circuit 1 by the simultaneous bidirectional input / output circuit 2. As a result, the simultaneous bidirectional input / output circuit 1 and the simultaneous bidirectional input / output circuit 2 can satisfy the specifications of the setup time and hold time necessary for reliably capturing data, and the simultaneous bidirectional input / output circuit. 1 and simultaneous bidirectional I / O circuit 2 can transmit and receive data on the same bus at the same time, suppressing the occurrence of data errors during data transmission between simultaneous bidirectional I / O circuits 1 and 2 However, the throughput can be improved.

  Further, the simultaneous bidirectional input / output circuit 1 can capture the transmission data TXData1 in synchronization with the rising edge of the clock signal φ0 input to the transmission clock terminal TXclock1. The simultaneous bidirectional input / output circuit 2 can output the reception data RXData2 in synchronization with the falling edge of the clock signal φ0 input to the reception clock terminal RXclock2 via the clock line CL1 and the buffer 4. .

  The simultaneous bidirectional input / output circuit 2 can capture the transmission data TXData2 in synchronization with the rising edge of the clock signal φ0 input to the transmission clock terminal TXclock2 via the clock line CL1 and the buffer 4. Further, the simultaneous bidirectional input / output circuit 1 receives the reception data RXData1 in synchronization with the falling edge of the clock signal φ0 input to the reception clock terminal RXclock2 via the clock line CL1, the buffers 4, 5 and the clock line CL2. Can be output.

  As a result, the timing at which the transmission data TXData1 is taken into the simultaneous bidirectional input / output circuit 1 and the timing at which the reception data RXData2 is output from the simultaneous bidirectional input / output circuit 2 can be shifted, and the transmission data TXData2 is It is possible to shift the timing at which the simultaneous bidirectional input / output circuit 2 is fetched from the timing at which the reception data RXData1 is output from the simultaneous bidirectional input / output circuit 1. For this reason, after the transmission data TXData1 taken in the simultaneous bidirectional input / output circuit 1 is transmitted to the simultaneous bidirectional input / output circuit 2, the reception data RXData2 can be output from the simultaneous bidirectional input / output circuit 2. At the same time, after the transmission data TXData2 taken in the simultaneous bidirectional input / output circuit 2 is transmitted to the simultaneous bidirectional input / output circuit 1, it is possible to output the reception data RXData1 from the simultaneous bidirectional input / output circuit 1. Even when data transmission / reception is simultaneously performed between the bidirectional input / output circuit 1 and the simultaneous bidirectional input / output circuit 2 on the same bus line IF1, the generation of data errors at the time of data transmission is suppressed and throughput is suppressed. Can be improved.

  Further, by driving both simultaneous bidirectional input / output circuits 1 and 2 based on the clock signal φ0 generated by the PLL circuit 3, it is not necessary to use independent and independent clocks. For this reason, it is possible to prevent an increase in the probability of occurrence of data errors with the least common multiple of the clock periods as a period, and it is possible to suppress a decrease in overall throughput.

  The simultaneous bidirectional input / output circuit 1 captures transmission data TXData1 in synchronization with the falling edge of the clock signal φ0 input to the transmission clock terminal TXclock1, and the simultaneous bidirectional input / output circuit 2 The reception data RXData2 may be output in synchronization with the rising edge of the clock signal φ0 input to the reception clock terminal RXclock2 via CL1 and the buffer 4.

  The simultaneous bidirectional input / output circuit 2 takes in the transmission data TXData2 in synchronization with the falling edge of the clock signal φ0 input to the transmission clock terminal TXclock2 via the clock line CL1 and the buffer 4, and simultaneously The direction input / output circuit 1 outputs reception data RXData1 in synchronization with the rising edge of the clock signal φ0 input to the reception clock terminal RXclock2 via the clock line CL1, the buffers 4, 5 and the clock line CL2. May be.

In the above-described embodiment, the method of using the PLL circuit 3 to generate the clock signal φ0 has been described. However, in addition to the PLL circuit 3, a frequency multiplier circuit such as a DLL (Delay Lock Loop) circuit is used. May be.
FIG. 2 is a timing chart showing a data transfer method of the semiconductor integrated circuit of FIG. Note that the hatched portion indicates a region where an error may occur due to limitations on the setup time and hold time.

  In FIG. 2, the clock signal φ0 generated by the PLL circuit 3 is transmitted to the transmission clock terminal TXclock1 with almost no propagation delay, and the clock signal φ0 having the waveform (K1) is input to the transmission clock terminal TXclock1. Is done. Then, in synchronization with the rising edge of the clock signal φ0 input to the transmission clock terminal TXclock1, the transmission data TXData1 input to the simultaneous bidirectional input / output circuit 1 is taken into the simultaneous bidirectional input / output circuit 1. The transmission data TXData1 taken into the simultaneous bidirectional input / output circuit 1 is transmitted to the simultaneous bidirectional input / output circuit 2 via the bus line IF1.

  The clock signal φ0 generated by the PLL circuit 3 is transmitted to the transmission clock terminal TXclock2 via the clock line CL1 and the buffer 4, and the clock signal φ0 having the waveform (K2) is input to the transmission clock terminal TXclock2. Is done. Then, in synchronization with the rising edge of the clock signal φ0 input to the transmission clock terminal TXclock2, the transmission data TXData2 input to the simultaneous bidirectional input / output circuit 2 is taken into the simultaneous bidirectional input / output circuit 2. The transmission data TXData2 captured by the simultaneous bidirectional input / output circuit 2 is transmitted to the simultaneous bidirectional input / output circuit 1 through the bus line IF1.

Here, the propagation delay of the signal by the clock line CL1 and the buffer 4 is the propagation delay when the transmission data TXData1 is transmitted from the simultaneous bidirectional input / output circuit 1 to the simultaneous bidirectional input / output circuit 2 via the bus line IF1. Can be matched.
Thereby, it is possible to prevent the transmission timing of the transmission data TXData1 transmitted from the first CPU and the reception timing received by the second CPU as the reception data RXData2 from being affected by the propagation delay of both. Therefore, a timing error due to the setup time and hold time defined by the clock signal φ0 input to the transmission clock terminal TXclock1 and the setup time and hold time defined by the clock signal φ0 input to the reception clock terminal RXclock2 It is possible to avoid the risk of occurrence of

  The clock signal φ0 generated by the PLL circuit 3 is transmitted to the reception clock terminal RXclock2 via the clock line CL1 and the buffer 4, and the clock signal φ0 having the waveform (K2) is input to the reception clock terminal RXclock2. Is done. The reception data RXData2 is output from the simultaneous bidirectional input / output circuit 2 in synchronization with the falling edge of the clock signal φ0 input to the reception clock terminal RXclock2.

  The clock signal φ0 generated by the PLL circuit 3 is transmitted to the reception clock terminal RXclock1 via the clock line CL1, the buffers 4, 5 and the clock line CL2, and the clock signal φ0 having the waveform (K3) is received. Is input to the clock terminal RXclock1. The reception data RXData1 is output from the simultaneous bidirectional input / output circuit 1 in synchronization with the falling edge of the clock signal φ0 input to the reception clock terminal RXclock1.

  Here, in synchronization with the rising and falling edges of the clock signal φ0, the simultaneous bidirectional input / output circuit 1 alternately receives the transmission data TXData1 and the simultaneous bidirectional input / output circuit 2 outputs the reception data RXData2 alternately. By doing so, it is possible to shift the timing at which the transmission data TXData1 is taken into the simultaneous bidirectional input / output circuit 1 and the timing at which the reception data RXData2 is output from the simultaneous bidirectional input / output circuit 2. Therefore, it is possible to output the reception data RXData2 from the simultaneous bidirectional input / output circuit 2 after the transmission data TXData1 taken into the simultaneous bidirectional input / output circuit 1 is transmitted to the simultaneous bidirectional input / output circuit 2. Occurrence of data errors during data transmission can be suppressed.

  Further, the transmission data is transmitted from the simultaneous bidirectional input / output circuit 2 to the simultaneous bidirectional input / output circuit 1 by transmitting the clock signal φ0 to the reception clock terminal RXclock1 via the clock line CL1, the buffers 4, 5 and the clock line CL2. It is possible to delay the clock signal φ0 input to the reception clock terminal RXclock1 by a delay when TXData2 is transmitted. Therefore, it is possible to prevent the rising of the clock signal φ0 input to the receiving clock terminal RXclock1 from being accelerated by the time required for transmitting data between the simultaneous bidirectional input / output circuits 1 and 2, It becomes possible to satisfy the specifications of the setup time and hold time necessary for reliably capturing data in both CPUs.

FIG. 3 is a block diagram showing a configuration of a semiconductor integrated circuit according to the second embodiment of the present invention.
In FIG. 3, a simultaneous bidirectional input / output circuit 11 is disposed on the first CPU side, and a simultaneous bidirectional input / output circuit 12 is disposed on the second CPU side. The simultaneous bidirectional input / output circuit 11 and the simultaneous bidirectional input / output circuit 12 are connected via a bus line IF2.
Here, the simultaneous bidirectional input / output circuit 11 is provided with a transmission clock terminal TXclock 11 for instructing a timing for capturing the transmission data TXData 11 and a reception clock terminal for instructing a timing for outputting the reception data RXData 11. RXclock 11 is provided. Further, the simultaneous bidirectional input / output circuit 12 is provided with a transmission clock terminal TXclock 12 for instructing a timing for taking in the transmission data TXData12 and a reception clock terminal RXclock12 for instructing a timing for outputting the reception data RXData12. Is provided.

  A PLL circuit 13 is provided that generates clock signals φ1 and φ2 having different phases based on the comparison result between the reference signal EXTclock and the feedback signal. Here, the clock signal φ 1 generated by the PLL circuit 13 is input to the transmission clock terminal TXclock 11 of the simultaneous bidirectional input / output circuit 11. The clock signal φ1 generated by the PLL circuit 13 is input to the transmission clock terminal RXclock 12 of the simultaneous bidirectional input / output circuit 12 via the clock line CL11 and the buffer 14. The clock signal φ1 generated by the PLL circuit 13 is fed back to the PLL circuit 13 via the clock line CL11, the buffers 14 and 16, and the clock line CL13.

  The clock signal φ2 generated by the PLL circuit 13 is input to the transmission clock terminal TXclock12 of the simultaneous bidirectional input / output circuit 12 via the clock line CL12 and the buffer 15. The clock signal φ2 generated by the PLL circuit 13 is input to the transmission clock terminal RXclock11 of the simultaneous bidirectional input / output circuit 11 through the clock line CL12, the buffers 15, 17 and the clock line CL14.

  The signal propagation delay by the clock line CL11 and the buffer 14 is made to correspond to the time necessary for transmitting the signal from the simultaneous bidirectional input / output circuit 11 to the simultaneous bidirectional input / output circuit 12 via the bus line IF2. Can do. Further, the propagation delay of the signal by the clock line CL12 and the buffer 15 is made to correspond to the time required for transmitting the signal from the simultaneous bidirectional input / output circuit 11 to the simultaneous bidirectional input / output circuit 12 via the bus line IF2. Can do.

  Further, the propagation delay of the signal by the clock line CL13 and the buffer 16 is made to correspond to the time required for transmitting the signal from the simultaneous bidirectional input / output circuit 12 to the simultaneous bidirectional input / output circuit 11 via the bus line IF2. Can do. Further, the propagation delay of the signal by the clock line CL14 and the buffer 17 is made to correspond to the time required for transmitting the signal from the simultaneous bidirectional input / output circuit 12 to the simultaneous bidirectional input / output circuit 11 via the bus line IF2. Can do.

  The transmission data TXData 11 input to the simultaneous bidirectional input / output circuit 11 is taken into the simultaneous bidirectional input / output circuit 11 in synchronization with the clock signal φ1 input to the transmission clock terminal TXclock 11 (K11). The transmission data TXData 11 taken into the simultaneous bidirectional input / output circuit 11 is transmitted to the simultaneous bidirectional input / output circuit 12 through the bus line IF2.

  Also, the transmission data TXData12 input to the simultaneous bidirectional input / output circuit 12 is synchronized with the clock signal φ2 input to the transmission clock terminal TXclock12 via the clock line CL14 and the buffer 15, and the simultaneous bidirectional input / output circuit. 12 (K15). The transmission data TXData 12 taken into the simultaneous bidirectional input / output circuit 12 is transmitted to the simultaneous bidirectional input / output circuit 11 via the bus line IF2.

  Then, the simultaneous bidirectional input / output circuit 11 transmits the current simultaneous bidirectional input / output circuit 12 based on the level of the transmission data TXData 11 currently transmitted by itself and the signal level on the bus line IF2. It is possible to determine the level of the transmission data TXData12 that is being transmitted. The simultaneous bidirectional input / output circuit 11 outputs the reception data RXData11 in synchronization with the clock signal φ2 input to the reception clock terminal RXclock11 via the clock line CL14, the buffers 15, 17 and the clock line CL14 ( K16).

  Also, the simultaneous bidirectional input / output circuit 12 is currently transmitted by the counterpart simultaneous bidirectional input / output circuit 11 based on the level of the transmission data TXData 12 currently transmitted by itself and the signal level on the bus line IF2. The level of the transmitted data TXData11 can be determined. The simultaneous bidirectional input / output circuit 12 outputs the reception data RXData12 in synchronization with the clock signal φ1 input to the reception clock terminal RXclock12 via the clock line CL11 and the buffer 14 (K12).

The clock signal φ1 generated by the PLL circuit 13 is fed back to the PLL circuit 13 through the clock line CL11, the buffers 14 and 16, and the clock line CL13 (K13).
As a result, the phase difference between φ1 and φ2 is maintained as it is regardless of the length of the bus line IF2 and can be input to the simultaneous bidirectional input / output circuits 11 and 12, respectively.

  For this reason, even when there is a signal propagation delay due to the wiring length between the simultaneous bidirectional input / output circuits 11, 12, the timing of sending a signal from the simultaneous bidirectional input / output circuit 12 to the simultaneous bidirectional input / output circuit 11, It is possible to match the timing at which the signal sent from the bidirectional input / output circuit 11 is received by the simultaneous bidirectional input / output circuit 12. As a result, data can be transmitted between the simultaneous bidirectional input / output circuits 11 and 12 while satisfying the requirements of the setup time and hold time necessary for reliably capturing the data in the simultaneous bidirectional input / output circuits 11 and 12. Can be simultaneously transmitted on the same bus line IF2, and the throughput can be improved while suppressing the occurrence of a data error during data transmission between the simultaneous bidirectional input / output circuits 11 and 12. .

  The simultaneous bidirectional input / output circuit 11 can capture the transmission data TXData11 in synchronization with the rising edge of the clock signal φ1 input to the transmission clock terminal TXclock11. The simultaneous bidirectional input / output circuit 12 can output the reception data RXData12 in synchronization with the falling edge of the clock signal φ1 input to the reception clock terminal RXclock12 via the clock line CL11 and the buffer 14. .

  The simultaneous bidirectional input / output circuit 12 can capture the transmission data TXData12 in synchronization with the rising edge of the clock signal φ2 input to the transmission clock terminal TXclock12 via the clock line CL12 and the buffer 15. The simultaneous bidirectional input / output circuit 11 receives the received data RXData11 in synchronization with the falling edge of the clock signal φ2 input to the receiving clock terminal RXclock12 via the clock line CL12, the buffers 15, 17 and the clock line CL14. Can be output.

  This makes it possible to shift the timing at which the transmission data TXData 11 is taken into the simultaneous bidirectional input / output circuit 11 and the timing at which the reception data RXData 12 is output from the simultaneous bidirectional input / output circuit 12, The timing at which the transmission data TXData 12 is taken into the output circuit 12 and the timing at which the reception data RXData 11 is output from the simultaneous bidirectional input / output circuit 11 can be shifted.

  For this reason, it is possible to output the reception data RXData 12 from the simultaneous bidirectional input / output circuit 12 after the transmission data TXData 11 taken into the simultaneous bidirectional input / output circuit 11 is transmitted to the simultaneous bidirectional input / output circuit 12. At the same time, after the transmission data TXData12 taken in the simultaneous bidirectional input / output circuit 12 is transmitted to the simultaneous bidirectional input / output circuit 11, the reception bidirectional data RXData11 can be output from the simultaneous bidirectional input / output circuit 11. Even when data transmission / reception is simultaneously performed between the bidirectional input / output circuit 11 and the simultaneous bidirectional input / output circuit 12 on the same bus line IF2, throughput can be reduced while suppressing occurrence of data errors during data transmission. Can be improved.

In the above-described embodiment, the method of using the PLL circuit 13 to generate the clock signals φ1 and φ2 having different phases has been described. However, in addition to the PLL circuit 13, a frequency multiplication circuit such as a DLL circuit is used. It may be.
FIG. 4 is a timing chart showing a data transfer method of the semiconductor integrated circuit of FIG. Note that the hatched portion indicates a region where an error may occur due to limitations on the setup time and hold time.

  In FIG. 4, the clock signal φ1 generated by the PLL circuit 13 is transmitted to the transmission clock terminal TXclock11 with almost no propagation delay, and the clock signal φ1 having the waveform (K11) is input to the transmission clock terminal TXclock1. Is done. The transmission data TXData 11 input to the simultaneous bidirectional input / output circuit 11 is taken into the simultaneous bidirectional input / output circuit 11 in synchronization with the rising edge of the clock signal φ 1 input to the transmission clock terminal TXclock 11. The transmission data TXData 11 taken into the simultaneous bidirectional input / output circuit 11 is transmitted to the simultaneous bidirectional input / output circuit 12 through the bus line IF2.

  The clock signal φ2 generated by the PLL circuit 13 is transmitted to the transmission clock terminal TXclock12 via the clock line CL12 and the buffer 15, and the clock signal φ2 having the waveform (K15) is input to the transmission clock terminal TXclock12. Is done. The transmission data TXData12 input to the simultaneous bidirectional input / output circuit 12 is taken into the simultaneous bidirectional input / output circuit 12 in synchronization with the rising edge of the clock signal φ2 input to the transmission clock terminal TXclock12. The transmission data TXData 12 taken into the simultaneous bidirectional input / output circuit 12 is transmitted to the simultaneous bidirectional input / output circuit 11 via the bus line IF2.

  Here, the phase difference between the clock signals φ1 and φ2 is set corresponding to the propagation delay when the transmission data TXData11 is transmitted from the simultaneous bidirectional input / output circuit 11 to the simultaneous bidirectional input / output circuit 12 via the bus line IF2. Can be set. Thereby, the timing when the simultaneous bidirectional input / output circuit 12 receives the transmission data TXData 11 transmitted from the simultaneous bidirectional input / output circuit 11 and the timing when the simultaneous bidirectional input / output circuit 12 takes in the transmission data TXData 12 are set. Therefore, the setup time and hold time can be satisfied.

  The clock signal φ2 generated by the PLL circuit 13 is transmitted to the reception clock terminal RXclock12 via the clock line CL12 and the buffer 15, and the clock signal φ2 having the waveform (K15) is input to the reception clock terminal RXclock12. Is done. The reception data RXData12 is output from the simultaneous bidirectional input / output circuit 12 in synchronization with the falling edge of the clock signal φ2 input to the reception clock terminal RXclock12.

  The clock signal φ2 generated by the PLL circuit 13 is transmitted to the reception clock terminal RXclock11 via the clock line CL12, the buffers 15, 17 and the clock line CL14, and the clock signal φ2 having the waveform (K16) is received. Is input to the clock terminal RXclock11. The reception data RXData 11 is output from the simultaneous bidirectional input / output circuit 11 in synchronization with the falling edge of the clock signal φ 2 input to the reception clock terminal RXclock 11.

  Here, in synchronization with the rising edge and the falling edge of the clock signal φ1, the simultaneous bidirectional input / output circuit 11 alternately takes in the transmission data TXData11 and the simultaneous bidirectional input / output circuit 12 outputs the reception data RXData12 alternately. By doing so, it is possible to shift the timing at which the transmission data TXData 11 is taken into the simultaneous bidirectional input / output circuit 11 and the timing at which the reception data RXData 12 is output from the simultaneous bidirectional input / output circuit 12. Therefore, it is possible to output the reception data RXData 12 from the simultaneous bidirectional input / output circuit 12 after the transmission data TXData 11 taken in the simultaneous bidirectional input / output circuit 11 is transmitted to the simultaneous bidirectional input / output circuit 12. Occurrence of data errors during data transmission can be suppressed.

  In synchronization with the rising and falling edges of the clock signal φ2, the simultaneous bidirectional input / output circuit 12 alternately takes in the transmission data TXData12 and the simultaneous bidirectional input / output circuit 11 outputs the reception data RXData11 alternately. As a result, the timing at which the transmission data TXData 12 is taken into the simultaneous bidirectional input / output circuit 12 and the timing at which the reception data RXData 11 is output from the simultaneous bidirectional input / output circuit 11 can be shifted. For this reason, it is possible to output the reception data RXData 11 from the simultaneous bidirectional input / output circuit 11 after the transmission data TXData 12 taken into the simultaneous bidirectional input / output circuit 12 is transmitted to the simultaneous bidirectional input / output circuit 11. Occurrence of data errors during data transmission can be suppressed.

FIG. 5 is a block diagram showing a configuration example of the PLL circuit 13 of FIG.
In FIG. 5, the PLL circuit 13 is provided with a phase comparator 21, a charge pump circuit 22, a low pass filter 23, a voltage controlled oscillator 24, and a frequency divider 25. Here, clock signals φ 1 and φ 2 having different phases are output from the voltage controlled oscillator 24. The clock signal φ1 output from the voltage controlled oscillator 24 is input to the frequency divider 25, and the frequency divider 25 divides the clock signal φ1. Then, the signal frequency-divided by the frequency divider 25 is input to the phase comparator 21 and compared with the reference signal EXTclock input to the phase comparator 21. Then, the phase comparator 21 outputs an UP signal or a Down signal to the charge pump circuit 22 in response to a phase shift between the signal divided by the frequency divider 25 and the reference signal EXTclock. When the UP signal is output, the charge pump circuit 22 charges the capacitor with a charge, and when the Down signal is output, the charge pump circuit 22 discharges the charge accumulated in the capacitor. The charge pump circuit 22 generates a control voltage Vc corresponding to the amount of charge stored in the capacitor, and outputs the control voltage Vc to the voltage controlled oscillator 24 via the low pass filter 23. The voltage controlled oscillator 24 can lock the frequency of the clock signal φ1 by changing the frequency of the clock signal φ1 according to the control voltage Vc.

FIG. 6 is a diagram showing a configuration example of the voltage controlled oscillator 24 of FIG.
In FIG. 6, the voltage controlled oscillator 24 is provided with delay elements 31 to 35 whose delay amount can be varied according to the control voltage Vc. These delay elements 31 to 35 are connected in series, and the output of the delay element 35 at the last stage is input to the delay element 31 at the foremost stage to constitute a ring oscillator. Here, for example, by setting the output of the delay element 33 as the clock signal φ1 and the output of the delay element 35 as the clock signal φ2, the clock signals φ1 and φ2 having different phases can be extracted from the PLL circuit 13.

  In the example of FIG. 6, the method of using an odd number of delay elements 31 to 35 has been described. However, if the delay element is a complementary delay element, the delay element can be configured with an even number of stages. In the above-described embodiment, the method of using the PLL circuit 3 to generate the clock signals φ1 and φ2 having different phases has been described. However, in addition to the PLL circuit 3, a DLL (Delay Lock Loop) circuit or the like can be used. A frequency multiplication circuit may be used.

1 is a block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. 2 is a timing chart showing a data transfer method of the semiconductor integrated circuit of FIG. 1. The block diagram which shows the structure of the semiconductor integrated circuit which concerns on 2nd Embodiment of this invention. 4 is a timing chart showing a data transfer method of the semiconductor integrated circuit of FIG. 3. FIG. 4 is a block diagram illustrating a configuration example of a PLL circuit 13 in FIG. 3. FIG. 6 is a diagram illustrating a configuration example of the voltage controlled oscillator 24 of FIG. 5. The figure which shows the setup time and hold time at the time of data transmission.

Explanation of symbols

  1, 2, 11, 12 Simultaneous bidirectional input / output circuit, 3, 13 PLL circuit, 4, 5, 14, 15, 16, 17 Buffer, IF1, IF2 Simultaneous bidirectional input / output interface, CL1, CL2, CL11 to CL14 Clock line, 21 phase comparator, 22 charge pump circuit, 23 low-pass filter, 24 voltage controlled oscillator, 25 frequency divider, 31-35 delay element

Claims (10)

A plurality of CPUs mounted on the same chip;
A semiconductor integrated circuit comprising a simultaneous bidirectional input / output interface for interconnecting the CPUs. A simultaneous bidirectional I / O interface driven by a single clock;
A semiconductor integrated circuit comprising a plurality of CPUs connected via the simultaneous bidirectional input / output interface. The simultaneous bidirectional input / output interface is:
A first simultaneous bidirectional input / output circuit disposed on the first CPU side;
A second simultaneous bidirectional input / output circuit disposed on the second CPU side;
The transmission data captured by the first simultaneous bidirectional input / output circuit is transmitted to the second simultaneous bidirectional input / output circuit, and the transmission data captured by the second simultaneous bidirectional input / output circuit is transmitted to the first simultaneous bidirectional input / output circuit. A bus line for transmission to a bidirectional I / O circuit;
And a phase compensator for shifting the phases of clocks input to the first and second simultaneous bidirectional input / output circuits by a delay time of a signal transmitted through the bus line. Item 3. A semiconductor integrated circuit according to Item 2. A first simultaneous bidirectional input / output circuit disposed on the first CPU side and driven by a first clock;
A second simultaneous bidirectional input / output circuit disposed on the second CPU side and driven by a second clock having a phase different from the first clock by a certain amount;
The transmission data captured by the first simultaneous bidirectional input / output circuit is transmitted to the second simultaneous bidirectional input / output circuit, and the transmission data captured by the second simultaneous bidirectional input / output circuit is transmitted to the first simultaneous bidirectional input / output circuit. A semiconductor integrated circuit comprising a bus line for transmission to a bidirectional input / output circuit. Clock signal generating means for generating a clock signal;
The transmission data is captured in synchronization with either the rising edge or the falling edge of the clock generated by the clock signal generation means, and the rising edge or falling edge of the clock generated by the clock signal generation means A first simultaneous bidirectional input / output circuit that outputs received data in synchronization with either one of
The first simultaneous bidirectional input / output circuit captures transmission data in synchronization with an edge different from the rising edge or falling edge of the clock when reception data is output from the first simultaneous bidirectional input / output circuit. A second simultaneous bidirectional input / output circuit for outputting received data in synchronization with an edge different from a rising edge or a falling edge of a clock when transmission data is taken in,
The transmission data captured by the first simultaneous bidirectional input / output circuit is transmitted to the second simultaneous bidirectional input / output circuit, and the transmission data captured by the second simultaneous bidirectional input / output circuit is transmitted to the first simultaneous bidirectional input / output circuit. A semiconductor integrated circuit comprising a bus line for transmission to a bidirectional input / output circuit. A clock signal generating means for generating a clock signal based on a comparison result between the reference signal and the feedback signal;
A first simultaneous bidirectional input / output circuit to which the clock signal generated by the clock signal generation means is input;
A second simultaneous bidirectional input / output circuit in which a clock signal input to the first simultaneous bidirectional input / output circuit is input via a first clock line;
A second clock line for feeding back a clock signal input to the second simultaneous bidirectional input / output circuit to the clock signal generating means;
The transmission data captured by the first simultaneous bidirectional input / output circuit is transmitted to the second simultaneous bidirectional input / output circuit, and the transmission data captured by the second simultaneous bidirectional input / output circuit is transmitted to the first simultaneous bidirectional input / output circuit. A semiconductor integrated circuit comprising a bus line for transmission to a bidirectional input / output circuit. A clock signal generating means for generating a clock signal based on a comparison result between the reference signal and the feedback signal;
A first simultaneous bidirectional input / output circuit to which the clock signal generated by the clock signal generating means is input as a transmission clock;
A second simultaneous bidirectional input / output circuit in which a clock signal input to the first simultaneous bidirectional input / output circuit is input as a transmission clock and a reception clock via a first clock line;
A second clock line that feeds back a clock signal input to the second simultaneous bidirectional input / output circuit to the clock signal generation means, and inputs a clock for reception of the first simultaneous bidirectional input / output circuit;
The transmission data captured by the first simultaneous bidirectional input / output circuit is transmitted to the second simultaneous bidirectional input / output circuit, and the transmission data captured by the second simultaneous bidirectional input / output circuit is transmitted to the first simultaneous bidirectional input / output circuit. A semiconductor integrated circuit comprising a bus line for transmission to a bidirectional input / output circuit. The first simultaneous bidirectional input / output circuit captures transmission data in synchronization with either a rising edge or a falling edge of a clock signal input from the clock signal generation, and via the second clock line Receive data is output in synchronization with either the rising edge or falling edge of the input clock signal.
The second simultaneous bidirectional input / output circuit outputs received data from the first simultaneous bidirectional input / output circuit among rising edges or falling edges of a clock signal input via the first clock line. The transmission data is captured in synchronization with an edge different from the rising edge or falling edge of the clock at the time, and the rising edge or the falling edge of the clock signal input via the first clock line is 8. The semiconductor integrated circuit according to claim 7, wherein reception data is output in synchronization with an edge different from a rising edge or a falling edge of a clock when transmission data is taken into one simultaneous bidirectional input / output circuit. . A clock signal generating means for generating first and second clock signals having different phases based on a comparison result between the reference signal and the feedback signal;
A first simultaneous bidirectional input / output circuit to which the first clock signal generated by the clock signal generation means is input as a transmission clock;
A second simultaneous bidirectional input / output circuit in which a first clock signal input to the first simultaneous bidirectional input / output circuit is input as a reception clock via a first clock line;
A second clock line for inputting the second clock signal generated by the clock signal generating means to the second simultaneous bidirectional input / output circuit as a transmission clock;
A third clock line for feeding back the first clock signal input to the second simultaneous bidirectional input / output circuit to the clock signal generating means;
A fourth clock line for inputting the second clock signal inputted to the second simultaneous bidirectional input / output circuit as a reception clock to the first simultaneous bidirectional input / output circuit;
The transmission data captured by the first simultaneous bidirectional input / output circuit is transmitted to the second simultaneous bidirectional input / output circuit, and the transmission data captured by the second simultaneous bidirectional input / output circuit is transmitted to the first simultaneous bidirectional input / output circuit. A semiconductor integrated circuit comprising a bus line for transmission to a bidirectional input / output circuit. The first simultaneous bidirectional input / output circuit captures transmission data in synchronization with either the rising edge or the falling edge of the first clock signal input from the clock signal generation, and the fourth clock line The received data is output in synchronization with either the rising edge or the falling edge of the second clock signal input via
The second simultaneous bidirectional input / output circuit outputs received data from the first simultaneous bidirectional input / output circuit among rising edges or falling edges of the second clock signal input via the second clock line. The transmission data is captured in synchronization with an edge different from the rising edge or falling edge of the clock when the rising edge or the falling edge of the first clock signal input via the first clock line is detected. 10. The reception data is output in synchronization with an edge different from a rising edge or a falling edge of a clock when transmission data is taken into the first simultaneous bidirectional input / output circuit. Semiconductor integrated circuit.

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