JP2014137224A - Semiconductor test program, semiconductor test apparatus, and semiconductor test method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor test program and the like which shift in terms of time the peaks of current consumed by flip-flops (FF), thereby allowing a peak current of a semiconductor chip to be suppressed and an increase of a power supply noise in a scan test to be suppressed.SOLUTION: A computer-executable semiconductor test program for executing a scan test to a semiconductor integrated circuit provided with a plurality of clock domains (CD) that have a plurality of FFs causes a computer to execute the following steps: measuring the number of FFs per clock delay, for each of the CDs; obtaining, for each of the CDs, an in-domain peak latency in which the measured number of FFs becomes the maximum; obtaining a first CD that has the maximum number of FFs out of the CDs having the in-domain peak latency; and shifting the clock operation of the first CD or the other CDs so as to increase a difference between the first CD peak latency and the peak latencies of the CDs other than the first CD.

Description

  The present invention relates to a semiconductor test program for scanning a semiconductor device, a semiconductor test apparatus, and a semiconductor test method.

  In recent years, due to advances in semiconductor technology, semiconductor devices such as IC (Integrated Circuit) and LSI (Large Scale Integrated Circuit) have become more multifunctional and faster. Along with this, the reliability test and the shipping test of semiconductor devices are also progressing in many items and higher accuracy. In addition, various types of semiconductor devices have been developed, and a test adapted to the variety is also required.

  With the miniaturization of the semiconductor manufacturing process, low voltage operation and high integration of transistors have become possible. However, although the reduction in the operating voltage of the transistor contributes to the low power consumption operation, the resistance to power supply noise is reduced. In addition, with high integration, since power consumption per unit area tends to increase, noise resistance is further severe.

  This noise immunity problem is occurring not only at the time of operation of a semiconductor device, but also in a scan test which is one of the items of a shipping test that is generally performed. In the scan test, FF groups in a semiconductor integrated circuit (hereinafter referred to as a semiconductor chip) having a large number of FFs (flip-flops; clock-synchronized storage elements) are serially connected, and the FF groups are input / output terminals of the semiconductor chip. By providing a path called a scan chain that can be controlled and observed from the outside, and by setting “0” and “1” as test signals from the outside of the semiconductor chip to the register, values can be arbitrarily set in the circuit under test. It is a test method that has both observability and controllability.

  In general, clock tree generation is performed in semiconductor design. There is a method of generating a clock tree from a clock generation point by performing buffering in a tree structure using a macro and physical position information of FF, RAM, ROM, etc., by a buffer and an inverter, thereby suppressing clock skew. The design with the clock skew suppressed is for timing convergence in the semiconductor chip. Since it is common to generate a clock in this way, in the above-described scan test, the conditions under which FFs having clock delays operate simultaneously are easily prepared.

  In general, a clock tree is generated by semiconductor design, and the FFs in the semiconductor chip are designed to have a uniform clock delay. Within the same clock domain, a clock tree is generated so that the clock skew is matched to each FF. For this reason, when FFs extending over a plurality of clock domains are operated, clocks reach almost all FFs in the semiconductor chip at the same time when the delays between different clock domains are the same as well as within each domain.

FIG. 1 is a diagram showing the concept of a clock domain in a semiconductor chip.
The semiconductor chip 1 illustrated in FIG. 1 includes a first clock domain 2, a second clock domain 3, and a third clock domain 4. The first clock domain 2 includes an input / output terminal 21 and four flip-flop groups 22 to 25. The second clock domain 3 includes an input / output terminal 31 and two flip-flop groups 32 and 33. The third clock domain 4 includes an input / output terminal 41 and three flip-flop groups 42 to 44.

  As shown in FIG. 1, a plurality of FF groups are scattered on the entire surface of the semiconductor chip with different FF numbers for each clock domain, and each clock generally controls the FF groups in different clock domains.

  For example, in a test in which all FFs in a semiconductor chip operate like a scan test in a shipping test, the FFs in the semiconductor chip operate at the same time because the design is made so that there is a clock delay. In the scan test, since an arbitrary value is set in the FF, a phenomenon occurs in which the voltage of the logic cell around the FF drops below the operation guarantee voltage due to power supply noise caused by the consumption current of the FF generated at this time.

  The power supply noise referred to here is noise generated due to current / voltage changes in the LSI. Even if the total current consumption of the semiconductor chip is small, if there are many FFs that operate simultaneously, the current consumed instantaneously increases, so that the current change increases. As a result, noise increases, causing malfunction, and a scan test cannot be performed.

  The cause of the increase in power supply noise is that a large peak current is generated as a semiconductor chip by overlapping peaks with respect to the time axis of the current consumed by each FF. Although it is possible to reduce the peak current of the semiconductor chip by reducing the current consumption of the semiconductor chip, the peak current of the semiconductor chip can also be suppressed by shifting the current peak consumed by each FF in time. As described above, it is possible to reduce power supply noise (see, for example, Patent Documents 1, 2, and 3).

JP 2003-241847 A JP-A-11-194850 Japanese Patent Laid-Open No. 10-326303

However, there is a problem that the circuit configuration of the semiconductor device has to be changed in order to suppress an increase in power supply noise during the scan test of the semiconductor device.
The present invention has been made in view of the above situation, and by shifting the peak of the current consumed by each FF in time without changing the circuit configuration of the semiconductor device, the peak current as a semiconductor chip can be obtained. An object of the present invention is to provide a semiconductor test program, a semiconductor test apparatus, and a semiconductor test method capable of suppressing and suppressing an increase in power supply noise during a scan test.

The present invention employs the following configuration in order to solve the above problems.
In one proposal, a computer-executable semiconductor test program for executing a scan test on a semiconductor integrated circuit having a plurality of clock domains having a plurality of flip-flops is provided on a computer for each of the clock domains. The number of flip-flops for each delay is measured, and the peak latency in the domain in which the measured number of flip-flops is maximized is obtained for each clock domain, and the maximum number of flip-flops among the peak latency in the domain is obtained. Determining the first clock domain and increasing the difference between the peak latency of the first clock domain and the peak latency of a clock domain other than the first clock domain; 1 clock Characterized in that to offset the clocking of the clock domains other than the main.

  According to the present invention, when a semiconductor device is subjected to a scan test, the peak current as a semiconductor chip can be suppressed and an increase in power supply noise can be suppressed without changing the circuit configuration.

It is a figure showing the concept of the clock domain in a semiconductor chip. It is a figure for demonstrating the outline | summary of this Embodiment. It is a flowchart which shows the flow of the semiconductor test process which implement | achieves this Embodiment. It is a figure which shows the state (the 1) of a database. It is a figure which shows the state (the 2) of a database. It is a figure which shows the state (the 3) of a database. It is a figure which shows the state (the 4) of a database. It is a figure which shows the state (the 5) of a database. It is a figure which shows the state (the 6) of a database. It is a figure which shows the state (the 7) of a database. It is a figure which shows the state (the 8) of a database. It is a figure for demonstrating the effect of this Embodiment. It is a figure which shows the result of the conventional DVD analysis. It is a figure which shows the result of the DVD analysis of this Embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 2 is a diagram for explaining the outline of the present embodiment.
The netlist 51 is electronic data indicating a connection relationship between terminals in the electronic circuit. For example, it is data of connection information between cells (logic gates such as AND and OR), and a cell name that is unique in a net list is called an instance.

  SDC (Synopsys Design Constraints) 52 defines the timing constraints of the semiconductor chip. For example, clock frequency and delay constraints are defined. Widely and widely used as a file format for various setting condition data given to timing verification tools such as LSI timing verification.

  A TWF (Timing Window File) 53 is a file having information on the rising and falling transition times of the signal of each instance.

  The DEF (Design Exchange Format) 54 is a semiconductor chip layout database, and describes, for example, cell block arrangement positions (coordinate information), power supply wiring, and signal wiring information on the semiconductor chip. The activity file 55 is a file having cell operation rate (signal transition rate) information in the semiconductor chip, and the operation rate is 2 when transitioning to high / low in one cycle. SPEF (Standard Parasitic Exchange Format) 56 describes signal wiring RC information in circuit design. A library (.lib) 57 is a library in which cell delay (delay), standard values such as setup / hold, and power information are defined.

The database 58 stores the number of FFs for each clock domain.
An STA (Static Timing Analysis) tool 61 verifies the timing of the circuit based on the delay time assigned to each cell constituting the semiconductor chip. A DVD (Dynamic Voltage Drop) analysis 62 confirms a time-dependent voltage drop within a clock cycle. The SIM pattern 63 is a simulation pattern that is output as an analysis result of the DVD analysis 62.

  FIG. 3 is a flowchart showing the flow of the semiconductor test processing for realizing the present embodiment, and FIGS. 4 to 11 are views showing the state of the database.

  First, in step S301 of FIG. 3, the net list 51, the SDC 52 in the mode for reducing the DVD analysis such as the scan test, and the library 57 are read by the STA tool 61, and the clock defined by the SDC 52 at the time of scan shift is generated as a clock. Recognize the location.

  In step S302, all FFs in the semiconductor chip are extracted to recognize how many MHz the propagation clock is.

  In step S 303, the number of FFs is stored in the database (DB) 58 for each clock domain 2, 3, 4. An example of the state of the database 58 at this time is shown in FIG. Further, in each clock domain 2, 3, 4, the number of FFs for each clock delay value is ascertained and added to the database 58 for storage. An example of the state of the database 58 at this time is shown in FIG.

  In step S304, a histogram of clock delay values for each FF is created. In step S305, the most frequent clock delay value (peak latency) and its clock name are stored in the DB 58 for each test clock name. An example of the state of the database 58 at this time is shown in FIG. For example, in the database 58 shown in FIG. 6, the clock name xTESTCLK has a peak latency of a clock delay value of 4.7 [ns] in which 216688 FFs are operating. Although the clock delay distribution is omitted from FIG. 6 onward, it is the same as FIG.

  In step S306, the allowable voltage drop value is stored in the database 58 as a value that the user must not exceed the peak drop any more.

  In step S307, a TWF is created by the STA tool 61, and in step S308, DVD analysis is executed.

  In step S309, it is determined whether the result of the DVD analysis executed in step S308 is within the allowable voltage drop value set in step S306 or whether there is a 50% delay of the cycle.

  If the allowable voltage drop value has not been exceeded (step S309: YES), information that the DVD analysis is OK is given to the database 58 in step S310, and the clock skew is “0” (in FIG. 0 ”) is generated, and the process proceeds to the work after the simulation, the verification 64, and the tester 65. Moreover, when 50% of a period is exceeded, NG is output and it complete | finishes.

  On the other hand, when the allowable voltage drop value is exceeded (step S309: NO; first time), in step S311, the clock domain that drives the most FFs in each clock domain is extracted from the database 58, and the peak Get latency and its clock name. An example of the state of the database 58 at this time is shown in FIG. For example, in the case of the database 58 shown in FIG. 7, it is xTESTCLK.

  In step S312, the difference between the peak latency of the clock acquired in step S311 (xTESTCLK in the example of FIG. 7) and the peak latency of each FF is obtained, and the sum (sum) of the differences is obtained.

  In step S313, if the sum is positive, the clocks other than the clock that drives the FFs most are delayed by a predetermined amount, for example, 5%, of the minimum value of the clock cycle (in this case, 50 [MHz]). . On the other hand, in the negative case, the clock driving the FF most frequently is similarly delayed. In the example shown in FIG. 7, the peak latencies of the clock domains xTESTCLK, xDBG3_TCK, xDBG2_TCK, xUART_RXD, xDBG1_TCK are “4.7”, “5.5”, “6.5”, “3.6”, respectively. “5.8”. Therefore, the difference between the peak latency of each clock domain xDBG3_TCK, xDBG2_TCK, xUART_RXD, xDBG1_TCK and the peak latency of clock domain xTESTCLK is 5.5-4.7 = 0.8, 6.5-4.7 = 1.8, 3.6-4.7 = -1.1, 5.8-4.7 = 1.1, and the sum is 0.8 + 1.8-1.1 + 1.1 = 2.6. Since this value “2.6” is positive, it delays other than xTESTCLK by 1 [ns] (5% of 50 [MHz]). That is, the clock skew is set to “1”.

  An example of the state of the database 58 at this time is shown in FIG. However, since the clock delay distribution information in the database 58 is only clock delay information in the design, even if the clock input from the outside is delayed, the clock delay information in the design does not change and is not updated. For the same reason, the information of the clock list in the database 58 is also updated because it is design information. Only the clock skew information is updated.

  In step S314, the clock cycle is acquired from the database 58, and a 5% delay of the cycle is added. In step S315, the SDC 52 with a delay is created.

  In step S316, the STA tool 61 generates the TWF 53 with the clock delayed according to the value in the database 58.

  Returning to step S308, DVD analysis is executed. In step S309, is the result of the DVD analysis executed in step S308 within the allowable voltage drop value set in step S306, or is there a 50% delay in the cycle? Judge whether or not.

  If the allowable voltage drop value has not been exceeded (step S309: YES), in step S310, information that the DVD analysis is OK is given to the database 58, and a SIM pattern 63 having a clock skew of “1” is generated. Then, proceed to the work after the simulation, verification 64 and tester 65. An example of the state of the database 58 at this time is shown in FIG.

  On the other hand, when the allowable voltage drop value is exceeded (step S309: NO; second time), the clock period is acquired from the database 58 in step S314, and the minimum value of this clock period (in this case, 50 [MHz]) ) Is further delayed by 5%. The delayed information is stored in the database 58. An example of the state of the database 58 at this time is shown in FIG. As shown in FIG. 10, the clock skew other than xTESTCLK is 2 [ns] and stored in the database 58.

  In step S315, a delayed SDC 52 is created. In step S316, the STA tool 61 generates the TWF 53 with the clock delayed according to the value of the database 58, and the process returns to step S308 again to perform DVD analysis.

  Similarly, in step S309, it is determined whether the result of the DVD analysis executed in step S308 is within the allowable voltage drop value set in step S306, or whether there is a 50% delay of the cycle.

  If the allowable voltage drop value has not been exceeded (step S309: YES), in step S310, information that the DVD analysis is OK is given to the database 58, and a SIM pattern 63 having a clock skew of “1” is generated. Then, proceed to the work after the simulation, verification 64 and tester 65.

  On the other hand, when the allowable voltage drop value is exceeded (step S309: NO; however, after the third time), it is repeatedly executed until the given delay value is, for example, half the period (50%).

  When the period becomes half, it is delayed by one half of the minimum value of the clock period (in this case, 50 [MHz]). In the case of this database 58, other than xTESTCLK is delayed by 10 [ns] (20 [ns] / 2). The one-half delay is stored in the database 58. An example of the state of the database 58 at this time is shown in FIG.

  After that, the TWF 53 with the clock delayed according to the value of the database 58 is created by the STA tool 61, and the DVD analysis 62 is executed. Further, if the peak drop does not exceed, the process is terminated and information that the DVD analysis result is OK is given to the database 58. Then, a SIM pattern 63 with a clock skew is created, and the process proceeds to the verification 64 and subsequent steps. In the case of NG, the processing is terminated because it is not solved even if the external clock is shifted.

  As described above, by reducing the number of FFs that operate simultaneously, it is possible to reduce the voltage of the FF peripheral logic cells from dropping below the operation guarantee voltage due to power supply noise due to the current consumption of the FFs, leading to an improvement in yield.

  FIG. 12 is a diagram for explaining the effect of the present embodiment, FIG. 13 is a diagram showing the result of conventional DVD analysis, and FIG. 14 is the result of DVD analysis of the present embodiment. FIG.

  As shown in FIG. 12, the peak current as a semiconductor chip is suppressed by shifting the peak current consumed by each FF in time.

  As a result, the peak current as a semiconductor chip is suppressed as shown in FIG. 14 as compared with the result of the conventional DVD analysis as shown in FIG. 13, thereby suppressing an increase in power supply noise during the scan test. .

  As described above, the embodiments of the present invention have been described with reference to the drawings. However, the above-described embodiments of the present invention are not limited to hardware, a DSP (Digital Signal Processor) board or a CPU as a function of a semiconductor test apparatus. It can be realized by firmware or software on the board.

  Further, the semiconductor test apparatus to which the present invention is applied is not limited to the above-described embodiment as long as the function is executed, and even a single apparatus or a system composed of a plurality of apparatuses Needless to say, the integrated device may be a system in which processing is performed via a network such as a LAN or a WAN.

  It can also be realized by a system including a CPU, a ROM or RAM memory connected to a bus, an input device, an output device, an external recording device, a medium driving device, and a network connection device. That is, a ROM or RAM memory, an external recording device, or a portable recording medium that records a software program that implements the system of the above-described embodiment is supplied to a semiconductor test device, and the computer of the semiconductor test device performs the program. Needless to say, this can also be achieved by reading and executing.

  In this case, the program itself read from the portable recording medium or the like realizes the novel function of the present invention, and the portable recording medium or the like on which the program is recorded constitutes the present invention.

  Examples of portable recording media for supplying the program include flexible disks, hard disks, optical disks, magneto-optical disks, CD-ROMs, CD-Rs, DVD-ROMs, DVD-RAMs, magnetic tapes, and nonvolatile memory cards. Various recording media recorded via a network connection device (in other words, a communication line) such as a ROM card, electronic mail or personal computer communication can be used.

  The computer (information processing apparatus) executes the program read out on the memory, thereby realizing the functions of the above-described embodiment, and an OS running on the computer based on the instructions of the program. Performs part or all of the actual processing, and the functions of the above-described embodiments are also realized by the processing.

  Furthermore, a program read from a portable recording medium or a program (data) provided by a program (data) provider is stored in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer. After being written, the CPU of the function expansion board or function expansion unit performs part or all of the actual processing based on the instructions of the program, and the functions of the above-described embodiments are also realized by the processing. obtain.

  That is, the present invention is not limited to the embodiment described above, and can take various configurations or shapes without departing from the gist of the present invention.

1 Semiconductor integrated circuit (semiconductor chip)
2 First clock domain 3 Second clock domain 4 Third clock domain 21, 31, 41 Input / output terminals 22-25, 31, 32, 41-44 Flip-flop group 51 Netlist 52 SDC (Synopsys Design Constraints)
53 TWF (Timing Window File)
54 DEF (Design Exchange Format)
55 Activity file
56 SPEF (Standard Parasitic Exchange Format)
57 Library (.lib)
58 Database (DB)
61 STA tool 62 DVD (Dynamic Voltage Drop) analysis 63 SIM pattern 64 Validation
65 tester

Claims (6)

In a computer-executable semiconductor test program for executing a scan test on a semiconductor integrated circuit having a plurality of clock domains having a plurality of flip-flops,
On the computer,
For each of the clock domains, let the number of flip-flops per clock delay be measured,
For each of the clock domains, the peak latency in the domain where the measured number of flip-flops is maximum is obtained,
A first clock domain having a maximum number of flip-flops of the intra-domain peak latency is obtained;
The first clock domain or a clock domain other than the first clock domain is increased so that a difference between a peak latency of the first clock domain and a peak latency of a clock domain other than the first clock domain is increased. A semiconductor test program characterized by shifting clock operations.   The semiconductor test program according to claim 1, wherein a clock operation of a clock domain other than the first clock domain is shifted with respect to the first clock domain. The semiconductor test program according to claim 1, wherein a clock operation of the first clock domain is shifted with respect to a clock domain other than the first clock domain.
The semiconductor test program according to claim 1.   The sum of the differences between the peak latencies of the first clock domain and the peak latencies of clock domains other than the first clock domain is obtained. When the sum is positive, the maximum number of flip-flops is driven. Clocks other than the clock that is currently being delayed are delayed by a predetermined amount with respect to the minimum value of the clock cycle, and if the sum is negative, the clock driving the maximum number of flip-flops is delayed by a predetermined amount with respect to the minimum value of the clock cycle. The semiconductor test program according to claim 1. In a semiconductor test apparatus for performing a scan test on a semiconductor integrated circuit including a plurality of clock domains having a plurality of flip-flops,
Flip-flop number measuring means for measuring the number of flip-flops per clock delay for each of the clock domains;
For each clock domain, peak latency detection means for obtaining an intra-domain peak latency that maximizes the number of flip-flops measured by the flip-flop number measurement means;
First clock domain detecting means for obtaining a first clock domain having the maximum number of flip-flops among the in-domain peak latencies obtained by the peak latency detecting means;
The first clock domain or the second clock domain is set so that a difference between a peak latency of the first clock domain detected by the first clock domain detecting unit and a peak latency of a clock domain other than the first clock domain increases. Clock shift means for shifting clock operations in clock domains other than one clock domain;
A semiconductor test apparatus comprising: In a computer-executable semiconductor test method for performing a scan test on a semiconductor integrated circuit having a plurality of clock domains having a plurality of flip-flops,
Computer
For each of the clock domains, measure the number of flip-flops per clock delay,
For each clock domain, determine the peak latency in the domain where the measured number of flip-flops is maximum,
A first clock domain having a maximum number of flip-flops among the intra-domain peak latencies is obtained.
The first clock domain or a clock domain other than the first clock domain is increased so that a difference between a peak latency of the first clock domain and a peak latency of a clock domain other than the first clock domain is increased. A semiconductor test method characterized by staggering clock operations.