TWI531921B - Timing analysis method for digital circuit design and system thereof - Google Patents

Description

Timing analysis method and system for digital circuit design

The present invention relates to an analysis and simulation technique for a digital integrated circuit (IC) design, and more particularly to a timing analysis method and system for a digital circuit design.

In order to simplify the design complexity of the digital circuit, the user can use the digital circuit design program and its built-in library model to design the required circuit, and the digital circuit design to verify the function of the circuit. In order to judge whether the digital circuit design can smoothly meet the functional requirements of the user. Since the implementation of the circuit structure requires consideration of a considerable number of electronic circuits and electromagnetic characteristics, such as considering the placement of various components in the circuit, the influence of the line length on the signal, timing, and power transmission, etc., the digital circuit is routed ( Auto-Place-Route; APR) tools for subsequent circuit-related implementation and verification.

In order to perform timing analysis for each digital circuit design, each digital circuit design is obtained in a gate-level manner according to its circuit structure and variation by signal simulation to obtain delay and timely. sequence Timing parameters of timing checking, which may constitute multiple timing arcs. In this way, the routing tool can analyze the timing model of the circuit design only by using these timing arcs, without knowing the entire circuit architecture and component position. The set information of these specific timing parameters is called an extracted timing model (ETM). Sources of such variations may include manufacturing variations, device fatigue, environmental variability, phase-locked loop variations, and the like. However, regardless of the classification of the mutations, the sources of these variations clearly make the analysis and simulation of digital circuit design more difficult, so these variations must be accurately considered during the time series analysis.

The previous generation of timing model (ETM) generation process is to generate different ETMs for each working mode in each circuit design (for example, a single IP design component), and to follow each ETM according to its The wafer variations are derating, so that each circuit design may correspond to multiple ETMs. Since the routing tool must consider whether the timing verification of this circuit design meets the user requirements during the built-in self-test (BIST) phase or the funciton verification phase, ETM must be used for each operating mode. Provide the wiring tool for reference. However, currently known wiring tools cannot read all the complete ETMs in a single circuit design, and can only be used as a reference for this circuit design by the first read ETM, but cannot be considered in other ETMs. Time series data. In other words, current routing tools cannot fully analyze the timing data of all ETMs in a single circuit design.

Therefore, how to effectively make the wiring tool smoothly follow a single circuit design Circuit analysis is performed by counting multiple ETMs corresponding to different operating modes, which is a problem that has always existed in digital circuit design techniques.

The invention provides a timing analysis method and system for digital circuit design, which can reduce the number of time series models read by the back end wiring tool by integrating multiple capture timing models corresponding to multiple working modes in a single circuit design. Increase the efficiency and accuracy of the routing tool for static timing analysis.

The invention provides a timing analysis method for digital circuit design, which comprises the following steps: obtaining an integrated circuit design, wherein the integrated circuit design operates in multiple working modes; and the working modes for the integrated circuit design respectively generate multiple Extracting a time series model, wherein each of the captured time series models includes a non-wafer variation portion and a wafer variation portion; integrating the capture timing models corresponding to the operation modes into a non-wafer variation timing model and a wafer variation timing model, wherein the generation The non-wafer variation timing model does not consider the wafer variation portion of these working modes; and, based on the non-wafer variation timing model and the wafer variation timing model, simulates the timing verification of the integrated circuit design.

In an embodiment of the invention, the non-wafer variation portion includes a logic gate delay analysis information set and a timing arc verification information set. The above-mentioned wafer variation portion includes chip setup derating information and chip hold derating information (chip hold derating) Information). The logic gate delay analysis information group includes at least one combined circuit element delay message, at least one sequential cell delay message, and a pulse width message. The logic gate delay analysis information group and the timing arc test information group do not include a signal setup margin factor and a signal hold margin factor regarding wafer variation.

In an embodiment of the invention, the wafer setup adjustment information includes a chip setup margin message to consider wafer variation. The wafer hold calibration information includes a chip hold margin message to account for wafer variations. The wafer setting boundary information and the wafer holding boundary information can be supplemented and adjusted by using different on-chip variation derating factors, respectively.

In an embodiment of the invention, generating the capture timing models separately may include the step of disregarding the wafer setting adjustment information and the wafer retention calibration information when generating the non-wafer variation timing model.

In an embodiment of the invention, generating the capture timing models separately may include the step of using a global on-chip variation supplement derating technique to generate the capture timing model.

In an embodiment of the invention, simulating the timing verification of the integrated circuit design may include the steps of: the non-wafer variation timing model and the wafer The variant timing model is imported into the routing tool for static timing analysis.

In an embodiment of the invention, simulating the timing verification of the integrated circuit design may further comprise the steps of: importing a signal setting boundary factor and a signal holding boundary factor for wafer variation into the wiring tool for static timing analysis. Process.

In an embodiment of the invention, all of the above-described capture timing models are generated using the same library corner.

From another point of view, the present invention proposes a timing analysis system for digital circuit design that is suitable for use in a computer device. The timing analysis system includes a transmission module, a timing acquisition module, a timing model integration module, and a timing analysis module. The transmission module is configured to receive an integrated circuit design, wherein the integrated circuit is designed to operate in a plurality of operating modes. The timing capture module is configured to generate a plurality of capture timing models for each of the working modes of the integrated circuit design, wherein each of the captured timing models includes a non-wafer variation portion and a wafer variation portion. The timing model integration module is configured to integrate the captured timing models corresponding to the working modes into a non-wafer variation timing model and a wafer variation timing model, wherein the wafers of the working modes are not considered when generating the non-wafer variation timing model Variation part. The timing analysis module simulates the timing verification of the integrated circuit design based on the non-wafer variation timing model and the wafer variation timing model.

Please refer to the above description for the remaining implementation details of the timing analysis system of this digital circuit design, and will not be described here.

From another point of view, the present invention provides a computer readable storage medium for storing a computer program for loading into a computer system and causing the computer system to perform a timing analysis method such as the above-described digital circuit design. .

Based on the above, embodiments of the present invention integrate multiple capture timing models (ETMs) corresponding to multiple working modes in a single digital circuit design to form two special acquisition timing models (ie, non-wafer variation timing models). (NOCV ETM) and the Chip Variation Timing Model (OCV ETM), and the two captured timing models are imported into the routing tool for subsequent static timing analysis. In particular, although the NOCV ETM considers the setting information of the chip signal, it does not consider the boundary variation factor of the wafer variation, so that the timing arc of each working mode in the digital circuit design can be controlled by NOCV. ETM and OCV ETM are fully presented in the static timing analysis of the routing tool. In other words, the inventive embodiment of the present invention can greatly reduce the number of timing models read by the backend routing tool and increase the efficiency of the routing tool in performing static timing analysis.

The above described features and advantages of the invention will be apparent from the following description.

FUNC‧‧‧ functional mode

BIST‧‧‧ self-test mode

NOCV1, NOCV2‧‧‧ non-wafer variation time series model

OCV1, OCV2‧‧‧ wafer variation timing model

ETM, ETM1, ETM2‧‧‧撷 Time Series Model

210‧‧‧Non-Chip Variant Timing Model (NOCV ETM)

220‧‧‧ wafer variation timing model (OCV ETM)

300‧‧‧Time Analysis System

310‧‧‧Transmission module

320‧‧‧Sequence capture module

330‧‧‧Time Series Model Integration Module

340‧‧‧Time Series Analysis Module

S410~S440‧‧‧Steps

Figure 1 is a schematic diagram of a digital circuit design with different operating modes and corresponding ETM.

2 is a number of different working modes according to an embodiment of the invention. Bit circuit design and schematic diagram of the corresponding ETM.

3 is a block diagram of a timing analysis system for digital circuit design in accordance with an embodiment of the present invention.

4 is a flow chart of a timing analysis method for a digital circuit design according to an embodiment of the invention.

FIG. 5 is a schematic diagram of each information group in a captured time series model according to an embodiment of the invention.

The Extracted Timing Model (ETM) is a timing model and a liberty file generated from a gate-level circuit map of the wafer. The ETM has the same timing behavior as the circuit diagram of the chip, and the ETM data size is much smaller than the data size of the circuit diagram, and the ETM can be used instead of the circuit diagram in the hierarchical timing analysis. ETM's arc delay has various arc types in the ETM, and these arc delays vary with the input transition and output load of the circuit diagram. ETM is generated by using STA analysis tools based on block diagrams, third-party libraries (third (3 ^rd ) party library), and other restrictions. The STA analysis tool only captures the timing of interface logic. . In general, circuit diagrams typically have a sequential circuit and a combinational circuit. For ETM, the sequential circuit has timing checking (eg, setup, hold, clock gating) between the input data port and the clock pin. Clock gating setup, clock gating hold, recovery, and removal, and delays from the clock pin to the output data (eg, minimum sequence delay (minimum) Sequential delay) and maximum sequential delay. For ETM, the combining circuit has a delay from input 埠 to output ( (eg, minimum combinational delay and maximum combinational delay).

Non-wafer variations and wafer variations must be considered in the past when generating ETM for digital circuit design. The set and hold tuning factors can be different for wafer variations. Therefore, there are at least three ETMs for each mode of operation: non-wafer variation ETM, wafer variation setting ETM, and wafer variation retention ETM. When the working mode is increased, more ETM will be generated. When the routing tool reads in all ETMs, the routing tool cannot fully analyze the timing data of all ETMs in a single circuit design.

On the other hand, most of today's digital circuits have multiple modes of operation due to design requirements. For example, Figure 1 is a schematic diagram of a digital circuit design with different operating modes and corresponding ETM. The digital circuit usually has a function mode FUNC that operates normally and a built-in self-test (BIST) that is required during the wafer test or verification phase. In other embodiments, the digital circuit can also have more modes of operation according to its needs. The data paths of these working modes are different from each other due to their different functions, so that the ETM of the same digital circuit design is different in different working modes. For example, the first capture timing model ETM1 Corresponding to the functional mode FUNC of the digital circuit, the first acquisition timing model ETM1 is composed of the first non-wafer variation portion NOCV1 and the first wafer variation portion OCV1; the second acquisition timing model ETM2 corresponds to this The self-test mode BIST of the digital circuit is generated, and the second acquisition timing model ETM2 is composed of the second non-wafer variation portion NOCV2 and the second wafer variation portion OCV2. During the timing analysis, the routing tool treats each of the captured timing models ETM1 and ETM2 in different operating modes as different digital circuits, resulting in the current routing tool not being able to read into a single digital circuit design in different operating modes. All the complete ETM. It is worth mentioning that the functional mode FUNC and the self-test mode of the digital circuit are only examples of the embodiments of the present invention. In another embodiment of the present invention, the ETM can be generated by a scan mode of the digital circuit, a Joint Test Action Group (JTAG) mode, and/or an IP mode.

Embodiments of the present invention integrate multiple capture timing models (ETMs) corresponding to multiple operating modes in a single digital circuit design to form two special acquisition timing models (ie, non-wafer variation timing models (NOCV) ETM) 210 and Chip Variation Timing Model (OCV ETM) 220), and the two captured timing models are imported into the routing tool for subsequent static timing analysis. 2 is a schematic diagram of a digital circuit design with different operating modes and corresponding ETMs in accordance with an embodiment of the invention. 1 is different from the embodiment of FIG. 2 in that the first non-wafer variation portion NOCV1 and the second non-wafer variation portion NOCV2 are integrated to form a special non-wafer variation timing model NOCV ETM 210; The wafer variation portion OCV1 and the second wafer variation portion OCV2 are integrated to A special wafer variation timing model OCV ETM 220 is formed. It is worth mentioning that although the NOCV ETM 210 considers the setting information of the wafer signal, it does not consider the boundary variation factor regarding the wafer variation. In this way, the timing arc of each working mode in the digital circuit design can be fully presented in the static timing analysis of the wiring tool by the two NOCV ETM 210 and OCV ETM 220. On the other hand, the boundary variation factor for wafer variation allows the routing tool to be read in for a more detailed and complete static timing analysis process. This reduces the number of ETMs in a digital circuit design with multiple operating modes and simplifies the operation of the static timing analysis process. Corresponding embodiments consistent with the above disclosure will be described in detail below.

3 is a block diagram of a timing analysis system 300 for digital circuit design in accordance with an embodiment of the present invention. 4 is a flow chart of a timing analysis method for a digital circuit design according to an embodiment of the invention. The timing analysis method and system for the digital circuit design described in the embodiments of the present invention are mainly applicable to a computer device. In other words, the timing analysis technology of digital circuit design is realized by the core processor, memory and related hardware of the computer device. In this embodiment, the timing analysis system 300 can include a transmission module 310, a timing acquisition module 320, a timing model integration module 330, and a timing analysis module 340. The modules 310-340 may be implemented by software consisting of instructions, or may be interconnected by one or more firmware or hardware processors.

Referring to FIG. 3 and FIG. 4 simultaneously, in step S410, the transmission module 310 is configured to receive an integrated circuit design. This integrated circuit design can operate in multiple working modes formula. In this embodiment, the integrated circuit design may be a net-list file for describing the position of each logic gate. The integrated circuit design can also be a circuit or a circuit component made up of third party intellectual property (IP) components. In step S420, the timing capture module 320 can generate a plurality of capture timing models for all working modes of the integrated circuit design. In other words, the timing capture module 320 will generate corresponding capture timing models ETM for each of the operational modes of the integrated circuit design. When the number of working modes of the integrated circuit design is increased, the corresponding number of the timing model ETM is also increased. In this embodiment, these ETMs are all generated using the same library corner.

The timing model ETM and the various information groups therein are described in detail herein. The application of the present embodiment should be able to know the definition of the acquisition timing model ETM and the classification of the information group from the following description, but the embodiment of the present invention Not only is this limited. FIG. 5 is a schematic diagram of each information group in a time series model ETM according to an embodiment of the invention. In the present embodiment, each of the captured timing models ETM includes a non-wafer variation portion 510 and a wafer variation portion 520. The non-wafer variation portion 510 includes a logic gate delay analysis information group 512, a timing arc inspection information group 514, and a minimum period (MP) constraint. The information in the logic gate delay analysis information set 512 is primarily information generated based on the gate delay of the logic gate, such information including, for example, at least one combined circuit element delay information, at least one sequential circuit delay Information and pulse_width information. At least one combined circuit element delay information is, for example, used to describe the maximum combined circuit element delay of the combined circuit (max_comb_delay) information and minimum combined circuit element delay (min_comb_delay) information. The at least one sequential circuit element delay information is, for example, information describing maximum sequential circuit element delay (max_seg_delay) and minimum sequential circuit element delay (min_seg_delay) information of the sequential circuit. In detail, max_comb_delay is the maximum delay arc information in the circuit diagram from the input 组合 of the combining circuit to the output 组合 of the combining circuit, and min_comb_delay is the minimum delay arc information in the circuit diagram from the input 组合 of the combining circuit to the output 埠 of the combining circuit. Max_seg_delay is the maximum delay arc information from the clock pin of the sequential circuit to the output port in the circuit diagram. min_seg_delay is the minimum delay arc information from the clock pin of the sequential circuit to the output port. The minimum period limit is also defined to capture the timing pin of the timing model ETM.

The information in the timing arc check information group 514 includes setting arc information setup1, return arc information recovery1, hold arc information hold1, removal arc information removal1, clock gating setting arc information clock_gating_setup1, and clock gating holding arc information clock_gating_hold1. Set arc information setup1, return arc information recovery1, hold arc information hold1, remove arc information remove1, clock gating set arc information clock_gating_setup1, and clock gating hold arc information clock_gating_hold1 for the main input connected to the sequential circuit in the circuit diagram埠Defined by timing verification between the clock pin of the sequential circuit. The information in these non-wafer variants 510 is not caused by wafer variations, but may be due to the logic gates of its circuit structure itself.

The information in the wafer variation portion 520 is generated due to the semiconductor system. The drift of the process will affect some of the information. For example, the wafer variation portion 520 includes wafer setting adjustment information 522 and wafer retention adjustment information 524. The information in the wafer setting adjustment information 522 includes at least the set arc information setup2, the return arc information recovery2, and the clock gate setting arc information clock_gating_setup2. The arc information setup2, the return arc information recovery2, and the clock gating setting arc information clock_gating_setup2 are defined for timing verification between the main input port of the sequential circuit and the clock pin of the sequential circuit in the circuit diagram. The information in the wafer hold calibration information 524 includes at least the hold arc information hold2, the removal arc information removal2, and the clock gating hold arc information clock_gating_hold2. The hold arc information hold2, the remove arc information remove2, and the clock gating hold arc information clock_gating_hold2 are defined for timing verification between the main input port of the sequential circuit and the clock pin of the sequential circuit in the circuit diagram.

However, in the embodiment of the present invention, the logic gate delay analysis information group 512 and the sequence arc check information group 514 of the embodiment of the present invention may not include signal setting regarding wafer variation, in order to enable ETMs in these different operation modes to be easily integrated with each other. The boundary factor and the signal maintain the boundary factor. In contrast, the wafer setting adjustment information 522 of the present embodiment may include the above-described wafer setting boundary information to consider the wafer variation, and the wafer retention adjustment information 524 may also include the above-described wafer holding boundary information to consider the wafer variation. The wafer setting adjustment information 522 and the wafer retention adjustment information 524 described above may be subjected to additional deraging of wafer variations using different on-chip variation derating factors.

With reference to FIG. 4 and FIG. 5, in step S430, the timing model integration module 330 of FIG. 3 can integrate the captured timing models ETM corresponding to the multiple working modes in the digital circuit design and the information groups therein. The non-wafer variation timing model NOCV ETM 210 and the wafer variation timing model OCV ETM 220. It is specifically mentioned that the timing model integration module 330 is a wafer variation portion 520 that does not consider these operating modes when generating the NOCV ETM 210. In other words, the generation of the NOCV ETM 210 mainly considers the logic gate delay analysis information group 512 and the timing arc inspection information group 514 of the non-wafer variation portion 510, but does not consider the wafer setting adjustment information 522, the wafer retention adjustment information group 524, Signals due to wafer variations set boundary factors and signal retention boundary factors.

In particular, in this embodiment, the timing capture module 320 and the timing model integration module 330 can use the global chip variation supplement adjustment technique to generate or integrate these ETMs instead of integrating them in static timing analysis. These ETMs.

In step S440, the timing analysis module 340 of FIG. 3 simulates the timing verification of the integrated circuit design according to the NOCV ETM 210 and the OCV ETM 220. In detail, the timing analysis module 340 can import the NOCV ETM 210 and the OCV ETM 220 into the routing tool (ARP tool) for the static timing analysis process.

In order to make the static timing analysis process more complete, this embodiment can import the boundary variation factor (ie, the gate delay boundary factor, the signal setting boundary factor, and the signal retention boundary factor) about the wafer variation into the wiring tool to perform These factors can be considered in the static timing analysis process.

In summary, the embodiment of the present invention has multiple work in a single digital circuit design. The multiple acquisition timing models (ETMs) corresponding to the pattern are integrated to form two special acquisition timing models (ie, non-wafer variation timing model (NOCV ETM) and wafer variation timing model (OCV ETM)), The two captured timing models are imported into the routing tool for subsequent static timing analysis. In particular, although the NOCV ETM considers the setting information of the chip signal, it does not consider the boundary variation factor of the wafer variation, so that the timing arc of each working mode in the digital circuit design can be controlled by NOCV. ETM and OCV ETM are fully presented in the static timing analysis of the routing tool. In other words, the inventive embodiment of the present invention can greatly reduce the number of timing models read by the backend routing tool and increase the efficiency of the routing tool in performing static timing analysis.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

S410~S440‧‧‧Steps

Claims (17)

A timing analysis method for digital circuit design includes: obtaining an integrated circuit design, wherein the integrated circuit design operates in a plurality of working modes; and the working modes designed for the integrated circuit respectively generate a plurality of captured timing models Each of the capture timing models includes a non-wafer variation portion and a wafer variation portion; the capture timing models corresponding to the operation modes are integrated into a non-wafer variation timing model and a wafer variation timing model, wherein The non-wafer variation timing model is generated without considering the wafer variation portion of the operation modes; and the timing verification of the integrated circuit design is simulated according to the non-wafer variation timing model and the wafer variation timing model. The timing analysis method according to claim 1, wherein the non-wafer variation portion includes a logic gate delay analysis information group and a timing arc inspection information group, the wafer variation portion includes a wafer setting adjustment information and a wafer retention Tuning information, wherein the logic gate delay analysis information group includes at least one combined circuit element delay information, at least one sequential circuit element delay information, and a clock width information, and the logic gate delay analysis information group and the time series arc inspection information group A signal setting boundary factor and a signal retention boundary factor for a wafer variation are not included. The timing analysis method according to claim 2, wherein the wafer setting adjustment information includes a wafer setting boundary information to consider the wafer variation, and the wafer retention adjustment information includes a wafer holding boundary information to consider the wafer variation. And The wafer setting boundary information and the wafer holding boundary information respectively use different wafer variation adjustment factors to perform supplemental adjustment of the wafer variation. For example, the timing analysis method described in claim 2, respectively, generating the capture timing models includes the following steps: when generating the non-wafer variation timing model, regardless of the wafer setting adjustment information and the wafer retention adjustment information . For example, the timing analysis method described in claim 2, respectively, generating the captured timing models includes the following steps: using a global wafer variation supplemental tuning technique to generate the captured timing models. As the timing analysis method described in claim 1 of the patent application, simulating the timing verification of the integrated circuit design includes the following steps: integrating the non-wafer variation timing model and the wafer variation timing model into a capture timing model file; The non-wafer variation timing model and the wafer variation timing model are imported into a routing tool to perform a static timing analysis process. For the timing analysis method described in claim 6, the timing verification for simulating the integrated circuit design further includes the steps of: importing a signal setting boundary factor and a signal retention boundary factor for the wafer variation into the wiring tool. To perform this static timing analysis process. The timing analysis method according to claim 1, wherein the captured timing models are generated by using the same library. A timing analysis system for digital circuit design, suitable for a computer device, The timing analysis system includes: a transmission module for receiving an integrated circuit design, wherein the integrated circuit is designed to operate in a plurality of working modes; and a timing capture module is configured for the integrated circuit The working modes respectively generate a plurality of capture timing models, wherein each of the captured timing models includes a non-wafer variation portion and a wafer variation portion; and a timing model integration module is configured to correspond to the operation modes The acquisition timing model is integrated into a non-wafer variation timing model and a wafer variation timing model, wherein the non-wafer variation timing model is generated without considering the wafer variation portion of the working modes; and a timing analysis module according to the non-wafer The variation timing model and the wafer variation timing model are used to simulate the timing verification of the integrated circuit design. The timing analysis system of claim 9, wherein the non-wafer variation portion comprises a logic gate delay analysis information group and a timing arc inspection information group, the wafer variation portion includes a wafer setting adjustment information and a wafer retention Tuning information, wherein the logic gate delay analysis information group includes at least one combined circuit element delay information, at least one sequential circuit element delay information, and a clock width information, and the logic gate delay analysis information group and the time series arc inspection information group A signal setting boundary factor and a signal retention boundary factor for a wafer variation are not included. The timing analysis system of claim 10, wherein the wafer setting adjustment information comprises a wafer setting boundary information to consider the wafer variation, the wafer maintaining calibration information including a wafer holding boundary information to consider the wafer variation , And the wafer setting boundary information and the wafer holding boundary information respectively use different wafer variation adjustment factors. The timing analysis system of claim 10, wherein the timing capture module does not consider the wafer setting adjustment information and the wafer retention adjustment information when generating the non-wafer variation timing model. The timing analysis system of claim 9, wherein the timing acquisition module uses a global wafer variation supplement adjustment technique to generate the acquisition timing models. The timing analysis system of claim 9, wherein the timing analysis module merges the non-wafer variation timing model and the wafer variation timing model into a routing tool to perform a static timing analysis process. The timing analysis system of claim 14, wherein the timing analysis module further imports a signal setting boundary factor and a signal retention boundary factor for the wafer variation into the wiring tool to perform the static timing analysis process. . The timing analysis system of claim 9, wherein the timing capture module uses the same library to generate the captured timing models. A computer readable storage medium for storing a computer program for loading into a computer system and causing the computer system to perform the digits as described in any one of claims 1 to 8. Timing analysis method for circuit design.