JPH01169828U - - Google Patents
Info
- Publication number
- JPH01169828U JPH01169828U JP6665588U JP6665588U JPH01169828U JP H01169828 U JPH01169828 U JP H01169828U JP 6665588 U JP6665588 U JP 6665588U JP 6665588 U JP6665588 U JP 6665588U JP H01169828 U JPH01169828 U JP H01169828U
- Authority
- JP
- Japan
- Prior art keywords
- input terminal
- terminal
- clock
- output
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案による２分周回路の実施例を示
す回路図、第２図は第１図の動作を説明するため
のタイムチヤートである。第３図は従来の２分周
回路の一例を示す回路図、第４図は第３図の動作
を説明するためのタイムチヤートである。
１……フリツプフロツプ、２……クロツク入力
端子、３……データ出力端子、４……データ入力
端子、８……論理和ゲート、９……モノマルチ回
路、１０，２５……クロツク波形、１１，２６，
２７……２分周後の波形。
FIG. 1 is a circuit diagram showing an embodiment of a divide-by-2 circuit according to the present invention, and FIG. 2 is a time chart for explaining the operation of FIG. 1. FIG. 3 is a circuit diagram showing an example of a conventional frequency divider circuit, and FIG. 4 is a time chart for explaining the operation of FIG. 3. 1... Flip-flop, 2... Clock input terminal, 3... Data output terminal, 4... Data input terminal, 8... OR gate, 9... Mono multi circuit, 10, 25... Clock waveform, 11, 26,
27...Waveform after frequency division by 2.
Claims (1)
力端子Ｄを接続し、クロツク入力端子Ｔにクロツ
クを入力することにより出力端子Ｑから前記クロ
ツクを２分周した波形を得る２分周回路において
、前記クロツク幅より充分に長い幅の出力パルス
を出すモノマルチ回路の入力を前記クロツク入力
端子Ｔに接続し、前記Ｄ形フリツプフロツプの出
力端子とデータ入力端子Ｄとの間に、出力端子
が前記データ入力端子Ｄに、第１の入力端子が前
記モノマルチ回路の出力に、第２の入力端子が前
記出力端子にそれぞれ接続されるように論理和
ゲートを挿入したことを特徴とする２分周回路。 In a divide-by-2 circuit that connects the output terminal of a D-type flip-flop and the data input terminal D, and inputs a clock to the clock input terminal T, a waveform obtained by dividing the frequency of the clock by two is obtained from the output terminal Q. The input of a monomulti circuit that produces output pulses with a sufficiently long width is connected to the clock input terminal T, and the output terminal is connected to the data input terminal D between the output terminal of the D-type flip-flop and the data input terminal D. . A divide-by-2 circuit characterized in that an OR gate is inserted such that a first input terminal is connected to the output of the monomulti circuit and a second input terminal is connected to the output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6665588U JPH01169828U (en) | 1988-05-20 | 1988-05-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6665588U JPH01169828U (en) | 1988-05-20 | 1988-05-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01169828U true JPH01169828U (en) | 1989-11-30 |
Family
ID=31292053
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6665588U Pending JPH01169828U (en) | 1988-05-20 | 1988-05-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01169828U (en) |
-
1988
- 1988-05-20 JP JP6665588U patent/JPH01169828U/ja active Pending
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