JPS60144328U - 2-phase clock signal generation circuit - Google Patents
2-phase clock signal generation circuitInfo
- Publication number
- JPS60144328U JPS60144328U JP2934884U JP2934884U JPS60144328U JP S60144328 U JPS60144328 U JP S60144328U JP 2934884 U JP2934884 U JP 2934884U JP 2934884 U JP2934884 U JP 2934884U JP S60144328 U JPS60144328 U JP S60144328U
- Authority
- JP
- Japan
- Prior art keywords
- frequency divider
- clock signal
- generation circuit
- signal generation
- count value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、本考案の２相りロック信号発生回路の一実施
例のブロック回路図、第２図は、本考案の他の実施例の
具体的な回路図、第３図は、本考案の別の他の実施例の
具体的な回路図である。 、１：発振器、２：第
１の分周器、３：第２の分周器、８，１３，１６：カウ
ント値検出器、１１．１９：分周器制御回路。FIG. 1 is a block circuit diagram of one embodiment of the two-phase lock signal generation circuit of the present invention, FIG. 2 is a specific circuit diagram of another embodiment of the present invention, and FIG. FIG. 3 is a specific circuit diagram of another embodiment of the present invention. , 1: Oscillator, 2: First frequency divider, 3: Second frequency divider, 8, 13, 16: Count value detector, 11.19: Frequency divider control circuit.
Claims (1)
ロック信号を入力としてクロック信号をそれぞれに発生
する第１と第２の分周器と、前記第２の分周器が所定の
カウント値であることを検出して出力を生ずるカウント
値検出器と、このカウント値検出器の出力により前記績
２の分周器のカウント動作を停止せしめ前記第１の分周
器からの基準信号で前記第２の分周器のカウント動作の
停止を解除する分周器制御回路とからなることを特徴と
する２相りロック信号発生回路。an oscillator that generates a master clock signal; first and second frequency dividers that receive the master clock signal as input and generate clock signals respectively; and that the second frequency divider has a predetermined count value. A count value detector detects and produces an output, and the output of this count value detector causes the count operation of the frequency divider of the second function to be stopped, and the reference signal from the first frequency divider causes the second frequency divider to stop. A two-phase lock signal generation circuit comprising: a frequency divider control circuit that releases the stoppage of the counting operation of a frequency divider.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2934884U JPS60144328U (en) | 1984-03-02 | 1984-03-02 | 2-phase clock signal generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2934884U JPS60144328U (en) | 1984-03-02 | 1984-03-02 | 2-phase clock signal generation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60144328U true JPS60144328U (en) | 1985-09-25 |
| JPH0321076Y2 JPH0321076Y2 (en) | 1991-05-08 |
Family
ID=30528074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2934884U Granted JPS60144328U (en) | 1984-03-02 | 1984-03-02 | 2-phase clock signal generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60144328U (en) |
-
1984
- 1984-03-02 JP JP2934884U patent/JPS60144328U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0321076Y2 (en) | 1991-05-08 |
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