JPS6438033U - - Google Patents

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Publication number
JPS6438033U
JPS6438033U JP1987130602U JP13060287U JPS6438033U JP S6438033 U JPS6438033 U JP S6438033U JP 1987130602 U JP1987130602 U JP 1987130602U JP 13060287 U JP13060287 U JP 13060287U JP S6438033 U JPS6438033 U JP S6438033U
Authority
JP
Japan
Prior art keywords
time register
values
start time
end time
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987130602U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987130602U priority Critical patent/JPS6438033U/ja
Publication of JPS6438033U publication Critical patent/JPS6438033U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の概念構成図、第2
図は別の実施例の概念構成図である。 1……遅延値信号、2……時間加算回路、3…
…開始時間レジスタ、4……終了時間レジスタ、
5,6……比較器、7,12……開始信号、8,
13……終了信号、9……タイマ、11……マイ
クロコンピユータ。
Figure 1 is a conceptual configuration diagram of an embodiment of the present invention;
The figure is a conceptual configuration diagram of another embodiment. 1... Delay value signal, 2... Time addition circuit, 3...
...Start time register, 4...End time register,
5, 6... Comparator, 7, 12... Start signal, 8,
13...End signal, 9...Timer, 11...Microcomputer.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 開始時間レジスタ、終了時間レジスタにそれぞ
れ開始時間値、終了時間値を設定しておくタイマ
予約録画装置において、所定の遅延時間に相応す
る遅延信号を入力し、開始時間レジスタおよび終
了時間レジスタの設定値とそれぞれ加算する手段
と、前記それぞれの加算値により開始時間レジス
タ、終了時間レジスタの設定値を更新する手段と
を有することを特徴とするタイマワンタツチ遅延
回路。
In a timer reservation recording device in which a start time value and an end time value are set in the start time register and end time register, respectively, a delay signal corresponding to a predetermined delay time is input, and the set values of the start time register and end time register are set. 1. A timer one-touch delay circuit comprising: means for adding each of the values; and means for updating set values of a start time register and an end time register using the respective added values.
JP1987130602U 1987-08-26 1987-08-26 Pending JPS6438033U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987130602U JPS6438033U (en) 1987-08-26 1987-08-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987130602U JPS6438033U (en) 1987-08-26 1987-08-26

Publications (1)

Publication Number Publication Date
JPS6438033U true JPS6438033U (en) 1989-03-07

Family

ID=31385920

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987130602U Pending JPS6438033U (en) 1987-08-26 1987-08-26

Country Status (1)

Country Link
JP (1) JPS6438033U (en)

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