JPH03110531U

JPH03110531U -

Info

Publication number: JPH03110531U
Application number: JP1680790U
Authority: JP
Priority date: 1990-02-23
Filing date: 1990-02-23
Publication date: 1991-11-13

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例に係るノンロツク・
ロツクスイツチ変換回路を示す回路図、第２図ａ
は第１図のロツクスイツチをＯＮ側に設定した場
合のタイミングチヤート、第２図ｂは第１図のロ
ツクスイツチをＯＦＦ側に設定した場合のタイミ
ングチヤート、第３図は従来のノンロツク・ロツ
クスイツチ変換回路を示す回路図、第４図ａは第
３図のロツクスイツチをＯＮ側に設定した場合の
タイミングチヤート、第４図ｂは第３図のロツク
スイツチをＯＦＦ側に設定した場合のタイミング
チヤートである。図に於いて、１はロツクスイツチ、２はプルア
ツプ抵抗、３は第１のフリツプフロツプ、４は電
源リセツト回路、５は発振回路、６は第２のフリ
ツプフロツプ、７は第３のフリツプフロツプ、８
は第１のＮＡＮＤ回路、９は第４のフリツプフロ
ツプ、１０は第５のフリツプフロツプ、１１は第
２のフリツプフロツプである。 Figure 1 shows a non-locking device according to an embodiment of the present invention.
Circuit diagram showing the lock switch conversion circuit, Figure 2a
is a timing chart when the lock switch in Figure 1 is set to the ON side, Figure 2b is a timing chart when the lock switch in Figure 1 is set to the OFF side, and Figure 3 is a diagram of a conventional non-lock/lock switch conversion circuit. The circuit diagram shown in FIG. 4A is a timing chart when the lock switch shown in FIG. 3 is set to the ON side, and FIG. 4B is a timing chart when the lock switch shown in FIG. 3 is set to the OFF side. In the figure, 1 is a lock switch, 2 is a pull-up resistor, 3 is a first flip-flop, 4 is a power supply reset circuit, 5 is an oscillation circuit, 6 is a second flip-flop, 7 is a third flip-flop, 8
1 is a first NAND circuit, 9 is a fourth flip-flop, 10 is a fifth flip-flop, and 11 is a second flip-flop.

Claims

[Scope of claim for utility model registration] A power supply reset circuit that outputs a reset signal for a certain period of time when the power is turned on, the ON side terminal and the OFF side terminal are each connected to a constant voltage power supply via a pull-up resistor, and the midpoint is a grounded lock switch, a first flip-flop whose ON side is input to a set side and whose OFF side is input to a reset side to provide a set output and a reset output; and a reset output of the first flip-flop. is D
a second flip-flop to which a reference clock is input to the input terminal, a reference clock is input to the clock terminal, and a reset signal from the power supply reset circuit is input to the reset terminal;
The output is input to the D input terminal, the reference clock is input to the clock terminal, and the reset signal from the power supply reset circuit is input to the reset terminal.
an OFF detection circuit consisting of a flip-flop, and a Q output of the second flip-flop and an output of the third flip-flop of the OFF-only circuit.
The first NA that performs AND logic and outputs an OFF signal
The set output of the ND circuit and the first flip-flop is D.
A fourth flip-flop is input to the input terminal, a reference clock is input to the clock terminal, and a reset signal from the power supply reset circuit is input to the reset terminal;
A fifth circuit in which the output is input to the D input terminal, the reference clock is input to the clock terminal, and the reset signal from the power supply reset circuit is input to the reset terminal.
an ON detection circuit consisting of a flip-flop, and a Q of the third flip-flop of the ON-only circuit.
The output and the output of the fourth flip-flop are set to NA
Second NAND that performs ND logic and outputs an ON signal
A non-lock/lock switch conversion circuit characterized by comprising a circuit.