JPH0250793U - - Google Patents

Info

Publication number
JPH0250793U
JPH0250793U JP12683888U JP12683888U JPH0250793U JP H0250793 U JPH0250793 U JP H0250793U JP 12683888 U JP12683888 U JP 12683888U JP 12683888 U JP12683888 U JP 12683888U JP H0250793 U JPH0250793 U JP H0250793U
Authority
JP
Japan
Prior art keywords
logical sum
signals
outputting
circuit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12683888U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12683888U priority Critical patent/JPH0250793U/ja
Publication of JPH0250793U publication Critical patent/JPH0250793U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Audible And Visible Signals (AREA)
  • Alarm Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係わる警報装置の一実施例を
示すブロツク回路図、第2図は出力波形図、第3
図は従来の警報装置を示すブロツク回路図である
。 1…発振器、2…論理積回路、3…論理和回路
、4…警報器。
Fig. 1 is a block circuit diagram showing an embodiment of the alarm device according to the present invention, Fig. 2 is an output waveform diagram, and Fig. 3 is an output waveform diagram.
The figure is a block circuit diagram showing a conventional alarm device. 1... Oscillator, 2... AND circuit, 3... OR circuit, 4... Alarm.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 発振器と、該発振器の出力信号を多段分周して
複数の同期信号を作るための分周回路と、該複数
の同期信号とこれに対応する複数の故障信号との
それぞれの論理積信号を出力するための論理積回
路と、該複数の論理積信号の論理和信号を出力す
るための論理和回路と、該論理和信号に基づいて
ランプ・ブザー・表示装置等で複数の故障態様を
報知する1個の警報器とを備えてなる警報装置。
an oscillator, a frequency dividing circuit for dividing the output signal of the oscillator in multiple stages to create a plurality of synchronization signals, and outputting an AND signal of each of the plurality of synchronization signals and a plurality of corresponding failure signals. an AND circuit for outputting a logical sum signal of the plurality of logical product signals; and a logical sum circuit for outputting a logical sum signal of the plurality of logical product signals, and a lamp, buzzer, display device, etc. to notify of a plurality of failure modes based on the logical sum signal. An alarm device comprising one alarm device.
JP12683888U 1988-09-27 1988-09-27 Pending JPH0250793U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12683888U JPH0250793U (en) 1988-09-27 1988-09-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12683888U JPH0250793U (en) 1988-09-27 1988-09-27

Publications (1)

Publication Number Publication Date
JPH0250793U true JPH0250793U (en) 1990-04-10

Family

ID=31378722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12683888U Pending JPH0250793U (en) 1988-09-27 1988-09-27

Country Status (1)

Country Link
JP (1) JPH0250793U (en)

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