JPS63195424U - - Google Patents

Info

Publication number
JPS63195424U
JPS63195424U JP8604287U JP8604287U JPS63195424U JP S63195424 U JPS63195424 U JP S63195424U JP 8604287 U JP8604287 U JP 8604287U JP 8604287 U JP8604287 U JP 8604287U JP S63195424 U JPS63195424 U JP S63195424U
Authority
JP
Japan
Prior art keywords
time
terminal device
generates
output
computer terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8604287U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8604287U priority Critical patent/JPS63195424U/ja
Publication of JPS63195424U publication Critical patent/JPS63195424U/ja
Pending legal-status Critical Current

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  • Input From Keyboards Or The Like (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例による電子計算機
の端末装置を示すブロツク構成図、第2図a,b
は第1図に示すタイマー回路と警告音発生回路の
具体的な構成図及び入力と出力信号の関係を示す
信号波形図、第3図は従来の電子計算機の端末装
置のブロツク構成図である。 図において、1はキーボード部、2は送信回路
、3は受信回路、4は表示制御回路、5は表示部
、6はタイマー回路、7は警告音発生回路である
Fig. 1 is a block diagram showing a terminal device for a computer according to an embodiment of this invention, Fig. 2 a, b
1 is a specific configuration diagram of the timer circuit and alarm sound generation circuit shown in FIG. 1, and a signal waveform diagram showing the relationship between input and output signals, and FIG. 3 is a block configuration diagram of a conventional computer terminal device. In the figure, 1 is a keyboard section, 2 is a transmitting circuit, 3 is a receiving circuit, 4 is a display control circuit, 5 is a display section, 6 is a timer circuit, and 7 is an alarm sound generating circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電子計算機の端末装置におけるキーボードを操
作する毎に発生する信号を検出して、その検出時
から時間を測定すると共に、所定時間以上経過し
たときに出力を発生するタイマー回路と、このタ
イマー回路からの出力を受けて警告を発生する警
告音発生回路とを備えた電子計算機の端末装置。
A timer circuit that detects a signal generated each time a keyboard in a computer terminal device is operated, measures time from the time of detection, and generates an output when a predetermined time has elapsed; An electronic computer terminal device comprising an alarm sound generation circuit that generates a warning upon receiving an output.
JP8604287U 1987-06-02 1987-06-02 Pending JPS63195424U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8604287U JPS63195424U (en) 1987-06-02 1987-06-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8604287U JPS63195424U (en) 1987-06-02 1987-06-02

Publications (1)

Publication Number Publication Date
JPS63195424U true JPS63195424U (en) 1988-12-15

Family

ID=30941992

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8604287U Pending JPS63195424U (en) 1987-06-02 1987-06-02

Country Status (1)

Country Link
JP (1) JPS63195424U (en)

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