JPH01155543U - - Google Patents
Info
- Publication number
- JPH01155543U JPH01155543U JP4924688U JP4924688U JPH01155543U JP H01155543 U JPH01155543 U JP H01155543U JP 4924688 U JP4924688 U JP 4924688U JP 4924688 U JP4924688 U JP 4924688U JP H01155543 U JPH01155543 U JP H01155543U
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- signal
- outputs
- monitored
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図は本考案に係る無信号検出回路の回路図
、第２図はそのタイムチヤート、第３図は従来の
無信号検出回路の回路図、第４図はそのタイムチ
ヤートである。
１……第１フリツプフロツプ、２……アンプ、
３……トランス、４……整流回路、５……コンデ
ンサ、６……カウンタ、７……クロツク発生器、
８……第２フリツプフロツプ、９……アンプ、１
０……トランス、１１……整流回路、１２……コ
ンデンサ、１３……リレー。なお、図中、同一符
号は同一、又は相当部分を示す。
FIG. 1 is a circuit diagram of a no-signal detection circuit according to the present invention, FIG. 2 is a time chart thereof, FIG. 3 is a circuit diagram of a conventional no-signal detection circuit, and FIG. 4 is a time chart thereof. 1...first flip-flop, 2...amplifier,
3...Transformer, 4...Rectifier circuit, 5...Capacitor, 6...Counter, 7...Clock generator,
8...Second flip-flop, 9...Amplifier, 1
0...transformer, 11...rectifier circuit, 12...capacitor, 13...relay. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
に基づきその故障を検出する回路において、 監視対象回路からのパルス信号により２出力端
子から交互に信号を出力する第１フリツプフロツ
プを有し、この出力に基づいて所定電圧を出力す
る第１電源回路と、 これに与えられるクロツク信号を計数し、監視
対象回路からのパルス信号が入力される都度リセ
ツトされるカウンタと、 該カウンタの計数値が所定値に達した際に出力
する信号をリセツト信号とする一方、前記クロツ
ク信号に応じて２出力端子から交互に信号を出力
する第２フリツプフロツプを有し、前記第１電源
回路から電圧が出力されている場合に第２フリツ
プフロツプ出力に基づいて所定電圧を出力する第
２電源回路と、 第２電源回路出力に応じて監視対象回路からの
パルス信号の無出力状態を報知する報知手段と を備えたことを特徴とする無信号検出回路。[Claim for Utility Model Registration] In a circuit that detects a failure based on the presence or absence of a pulse signal output from a circuit to be monitored, a first flip-flop that alternately outputs signals from two output terminals depending on the pulse signal from the circuit to be monitored. a first power supply circuit that outputs a predetermined voltage based on the output; a counter that counts clock signals applied to the first power supply circuit and is reset each time a pulse signal from the monitored circuit is input; A second flip-flop is provided which outputs a signal output when the count value reaches a predetermined value as a reset signal, and alternately outputs a signal from two output terminals according to the clock signal, a second power supply circuit that outputs a predetermined voltage based on the second flip-flop output when a voltage is being output; and a notification means that reports a non-output state of a pulse signal from the monitored circuit in accordance with the second power supply circuit output. A no-signal detection circuit characterized by comprising and.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4924688U JPH01155543U (en) | 1988-04-12 | 1988-04-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4924688U JPH01155543U (en) | 1988-04-12 | 1988-04-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01155543U true JPH01155543U (en) | 1989-10-25 |
Family
ID=31275360
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4924688U Pending JPH01155543U (en) | 1988-04-12 | 1988-04-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01155543U (en) |
-
1988
- 1988-04-12 JP JP4924688U patent/JPH01155543U/ja active Pending