JPH01104744U - - Google Patents
Info
- Publication number
- JPH01104744U JPH01104744U JP41388U JP41388U JPH01104744U JP H01104744 U JPH01104744 U JP H01104744U JP 41388 U JP41388 U JP 41388U JP 41388 U JP41388 U JP 41388U JP H01104744 U JPH01104744 U JP H01104744U
- Authority
- JP
- Japan
- Prior art keywords
- output
- wiring
- chip
- series
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
第1図は本考案の一実施例を示す図である。
Q1〜Q4……MOSトランジスタ、1,2…
…出力パツド、3,4……インバータ回路、L1
……インダクタンス回路、Vcc……電源。
FIG. 1 is a diagram showing an embodiment of the present invention. Q1 to Q4...MOS transistors, 1, 2...
...Output pad, 3, 4...Inverter circuit, L1
...Inductance circuit, Vcc...Power supply.
Claims (1)
上の配線で形成したインダクタンスを直列に接続
したことを特徴とする出力回路。 An output circuit characterized in that an inductance formed by wiring on a chip is connected in series between an output transistor and an output pad.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP41388U JPH01104744U (en) | 1988-01-05 | 1988-01-05 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP41388U JPH01104744U (en) | 1988-01-05 | 1988-01-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01104744U true JPH01104744U (en) | 1989-07-14 |
Family
ID=31199417
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP41388U Pending JPH01104744U (en) | 1988-01-05 | 1988-01-05 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01104744U (en) |
-
1988
- 1988-01-05 JP JP41388U patent/JPH01104744U/ja active Pending