JPS63165846U - - Google Patents
Info
- Publication number
- JPS63165846U JPS63165846U JP5838187U JP5838187U JPS63165846U JP S63165846 U JPS63165846 U JP S63165846U JP 5838187 U JP5838187 U JP 5838187U JP 5838187 U JP5838187 U JP 5838187U JP S63165846 U JPS63165846 U JP S63165846U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- attached
- lead frame
- tab
- wire bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Description
第１図は一実施例を示す平面図、第２図は第１
図のＡ―Ａ線位置での断面図、第３図は同実施例
で使用するリードフレームを示す平面図である。
２……リードフレーム、４……ＩＣチツプ、６
……リード、８……グランド用リード、１０……
絶縁フイルム、１２……ワイヤ。
FIG. 1 is a plan view showing one embodiment, and FIG. 2 is a plan view showing one embodiment.
FIG. 3 is a cross-sectional view taken along the line AA in the figure, and a plan view showing the lead frame used in the same embodiment. 2...Lead frame, 4...IC chip, 6
...Lead, 8...Ground lead, 10...
Insulating film, 12...wire.
Claims (1)
か又は取りつけられるＩＣチツプより小さいタブ
をもつリードフレームに、絶縁フイルムを介して
ＩＣチツプが取りつけられており、このＩＣチツ
プのパツドとリードフレームのリードの間がワイ
ヤボンデイング法により接続されているワイヤボ
ンデイング実装体。 The IC chip is attached via an insulating film to a lead frame that does not have a tab on the part where the IC chip is attached or has a tab that is smaller than the IC chip to be attached, and the pad of the IC chip and the leads of the lead frame are attached. A wire bonding assembly in which the parts are connected using the wire bonding method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987058381U JP2524967Y2 (en) | 1987-04-17 | 1987-04-17 | Wire bonding mount |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987058381U JP2524967Y2 (en) | 1987-04-17 | 1987-04-17 | Wire bonding mount |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63165846U true JPS63165846U (en) | 1988-10-28 |
| JP2524967Y2 JP2524967Y2 (en) | 1997-02-05 |
Family
ID=30888901
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987058381U Expired - Lifetime JP2524967Y2 (en) | 1987-04-17 | 1987-04-17 | Wire bonding mount |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2524967Y2 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53105970A (en) * | 1977-02-28 | 1978-09-14 | Hitachi Ltd | Assembling method for semiconductor device |
| JPS58143541A (en) * | 1982-02-22 | 1983-08-26 | Hitachi Ltd | Semiconductor device |
| JPS622626A (en) * | 1985-06-28 | 1987-01-08 | Nec Corp | Semiconductor device |
-
1987
- 1987-04-17 JP JP1987058381U patent/JP2524967Y2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53105970A (en) * | 1977-02-28 | 1978-09-14 | Hitachi Ltd | Assembling method for semiconductor device |
| JPS58143541A (en) * | 1982-02-22 | 1983-08-26 | Hitachi Ltd | Semiconductor device |
| JPS622626A (en) * | 1985-06-28 | 1987-01-08 | Nec Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2524967Y2 (en) | 1997-02-05 |