JPS61109148U - - Google Patents
Info
- Publication number
- JPS61109148U JPS61109148U JP1984193736U JP19373684U JPS61109148U JP S61109148 U JPS61109148 U JP S61109148U JP 1984193736 U JP1984193736 U JP 1984193736U JP 19373684 U JP19373684 U JP 19373684U JP S61109148 U JPS61109148 U JP S61109148U
- Authority
- JP
- Japan
- Prior art keywords
- lead
- plan
- view
- wire bonding
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案の一実施例の平面図、第２図は
これに半導体素子の電極線をボンデイングしたも
のの平面図、第３図はインナーリードの連結部を
除去したものの平面図、第４図は従来のものの平
面図、第５図はこれに電極線をボンデイングした
ものの平面図を示す。
１……インナーリードのワイヤボンデイング部
、２……インナーリード、３……電極線、４……
半導体素子、５……樹脂封止部、６……連結部。
Fig. 1 is a plan view of one embodiment of the present invention, Fig. 2 is a plan view of this to which electrode wires of a semiconductor element are bonded, Fig. 3 is a plan view of the case with the connecting portion of the inner lead removed, and Fig. 4 is a plan view of an embodiment of the present invention. The figure shows a plan view of a conventional device, and FIG. 5 shows a plan view of a device to which electrode wires are bonded. 1... Wire bonding part of inner lead, 2... Inner lead, 3... Electrode wire, 4...
Semiconductor element, 5... resin sealing part, 6... connecting part.
Claims (1)
イング点近傍を相互に連結したことを特徴とする
リードフレーム。 A lead frame characterized in that the inner lead and the electrode lead are interconnected near the wire bonding point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984193736U JPS61109148U (en) | 1984-12-21 | 1984-12-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984193736U JPS61109148U (en) | 1984-12-21 | 1984-12-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61109148U true JPS61109148U (en) | 1986-07-10 |
Family
ID=30751162
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984193736U Pending JPS61109148U (en) | 1984-12-21 | 1984-12-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61109148U (en) |
-
1984
- 1984-12-21 JP JP1984193736U patent/JPS61109148U/ja active Pending