JPS6190245U - - Google Patents

Info

Publication number
JPS6190245U
JPS6190245U JP17521184U JP17521184U JPS6190245U JP S6190245 U JPS6190245 U JP S6190245U JP 17521184 U JP17521184 U JP 17521184U JP 17521184 U JP17521184 U JP 17521184U JP S6190245 U JPS6190245 U JP S6190245U
Authority
JP
Japan
Prior art keywords
semiconductor device
utility
scope
external connection
registration request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17521184U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17521184U priority Critical patent/JPS6190245U/ja
Publication of JPS6190245U publication Critical patent/JPS6190245U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図Ａは本考案の一実施例による半導体装置
のリードフレームを示した平面図、第１図Ｂはそ
の側面図である。第２図は従来の半導体装置のリ
ードフレームを示した平面図である。 １…ペレツトマウント部、２…半導体チツプ、
３…外部導出リード、４…ボンデイングワイヤー
、５…フレーム部。 FIG. 1A is a plan view showing a lead frame of a semiconductor device according to an embodiment of the present invention, and FIG. 1B is a side view thereof. FIG. 2 is a plan view showing a lead frame of a conventional semiconductor device. 1... Pellet mount part, 2... Semiconductor chip,
3...External lead-out lead, 4...Bonding wire, 5...Frame part.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ペレツトマウント部の上方にその先端が突出し
た複数の外部接続ピンを有することを特徴とする
半導体装置。 A semiconductor device comprising a plurality of external connection pins whose tips protrude above a pellet mount.
JP17521184U 1984-11-19 1984-11-19 Pending JPS6190245U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17521184U JPS6190245U (en) 1984-11-19 1984-11-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17521184U JPS6190245U (en) 1984-11-19 1984-11-19

Publications (1)

Publication Number Publication Date
JPS6190245U true JPS6190245U (en) 1986-06-12

Family

ID=30732815

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17521184U Pending JPS6190245U (en) 1984-11-19 1984-11-19

Country Status (1)

Country Link
JP (1) JPS6190245U (en)

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