JPS62196356U - - Google Patents

Info

Publication number
JPS62196356U
JPS62196356U JP8495086U JP8495086U JPS62196356U JP S62196356 U JPS62196356 U JP S62196356U JP 8495086 U JP8495086 U JP 8495086U JP 8495086 U JP8495086 U JP 8495086U JP S62196356 U JPS62196356 U JP S62196356U
Authority
JP
Japan
Prior art keywords
integrated circuit
wire
inner lead
circuit element
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8495086U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8495086U priority Critical patent/JPS62196356U/ja
Publication of JPS62196356U publication Critical patent/JPS62196356U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案の集積回路装置の断面図、第
2図は従来の集積回路の断面図を表わす。 1a,1…リード、2…ワイヤー、3…集積回
路素子、4…封止樹脂。
FIG. 1 is a sectional view of an integrated circuit device according to the present invention, and FIG. 2 is a sectional view of a conventional integrated circuit. 1a, 1... Lead, 2... Wire, 3... Integrated circuit element, 4... Sealing resin.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 集積回路素子、インナーリード及びこの集積回
路素子とインナーリードとを接続するワイヤーが
樹脂封止された集積回路装置において、外部リー
ドと前記のワイヤー接続する際のステツチ部とに
段差を設けたことを特徴とする集積回路装置。
In an integrated circuit device in which an integrated circuit element, an inner lead, and a wire connecting the integrated circuit element and the inner lead are sealed with resin, a step is provided between the external lead and the stitching part when connecting the wire. Features of integrated circuit devices.
JP8495086U 1986-06-03 1986-06-03 Pending JPS62196356U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8495086U JPS62196356U (en) 1986-06-03 1986-06-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8495086U JPS62196356U (en) 1986-06-03 1986-06-03

Publications (1)

Publication Number Publication Date
JPS62196356U true JPS62196356U (en) 1987-12-14

Family

ID=30939910

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8495086U Pending JPS62196356U (en) 1986-06-03 1986-06-03

Country Status (1)

Country Link
JP (1) JPS62196356U (en)

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