JPS62147360U - - Google Patents
Info
- Publication number
- JPS62147360U JPS62147360U JP3560586U JP3560586U JPS62147360U JP S62147360 U JPS62147360 U JP S62147360U JP 3560586 U JP3560586 U JP 3560586U JP 3560586 U JP3560586 U JP 3560586U JP S62147360 U JPS62147360 U JP S62147360U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- lead frame
- lead
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図は本考案の一実施例の断面図、第２図は
従来の半導体集積回路の断面図である。
１，１１……リードフレームＩＣチツプ固着部
、２……上面側ＩＣチツプ、３……下面側ＩＣチ
ツプ、４，５……金属細線、６，１３……リード
部、７……封止樹脂。
FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional semiconductor integrated circuit. 1, 11...Lead frame IC chip fixing part, 2...Upper side IC chip, 3...Lower side IC chip, 4, 5...Metal thin wire, 6, 13...Lead part, 7...Sealing resin .
Claims (1)
両面にＩＣチツプを固着し、前記リードフレーム
のリード部とＩＣチツプの電極との間に接続し、
外装体内に封止してなることを特徴とする半導体
集積回路。 An IC chip is fixed to both the front and back sides of the IC chip fixing part of the lead frame, and connected between the lead part of the lead frame and the electrode of the IC chip,
A semiconductor integrated circuit characterized by being sealed within an exterior body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3560586U JPS62147360U (en) | 1986-03-11 | 1986-03-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3560586U JPS62147360U (en) | 1986-03-11 | 1986-03-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62147360U true JPS62147360U (en) | 1987-09-17 |
Family
ID=30845252
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3560586U Pending JPS62147360U (en) | 1986-03-11 | 1986-03-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62147360U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100277308B1 (en) * | 1997-04-17 | 2001-02-01 | 마찌다 가쯔히꼬 | Semiconductor device |
-
1986
- 1986-03-11 JP JP3560586U patent/JPS62147360U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100277308B1 (en) * | 1997-04-17 | 2001-02-01 | 마찌다 가쯔히꼬 | Semiconductor device |