JPH01107141U - - Google Patents
Info
- Publication number
- JPH01107141U JPH01107141U JP1988000901U JP90188U JPH01107141U JP H01107141 U JPH01107141 U JP H01107141U JP 1988000901 U JP1988000901 U JP 1988000901U JP 90188 U JP90188 U JP 90188U JP H01107141 U JPH01107141 U JP H01107141U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- shield plate
- conductive shield
- utility
- scope
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000007789 sealing Methods 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Description
第１図は、本考案の正面図、第２図は第１図の
側面図、第３図は、本考案を使用した半導体装置
の縦断面図、第４図は、従来のキヤツプを使用し
た半導体装置の縦断面図である。
１，６……キヤツプ、２……導電性シールド板
、３，８……入出力信号ピン、４，７……半導体
チツプ、５……ボンデイングワイヤー。
Figure 1 is a front view of the present invention, Figure 2 is a side view of Figure 1, Figure 3 is a vertical cross-sectional view of a semiconductor device using the present invention, and Figure 4 is a semiconductor device using a conventional cap. FIG. 2 is a longitudinal cross-sectional view of a semiconductor device. 1, 6... Cap, 2... Conductive shield plate, 3, 8... Input/output signal pin, 4, 7... Semiconductor chip, 5... Bonding wire.
Claims (1)
けたことを特徴とする高周波半導体装置。 A high-frequency semiconductor device characterized by having a conductive shield plate placed vertically on a sealing cap.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988000901U JPH01107141U (en) | 1988-01-07 | 1988-01-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988000901U JPH01107141U (en) | 1988-01-07 | 1988-01-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01107141U true JPH01107141U (en) | 1989-07-19 |
Family
ID=31200319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988000901U Pending JPH01107141U (en) | 1988-01-07 | 1988-01-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01107141U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006269564A (en) * | 2005-03-22 | 2006-10-05 | Sony Corp | Semiconductor device |
| JP2007019403A (en) * | 2005-07-11 | 2007-01-25 | Toshiba Corp | High frequency package device |
| JP2012009675A (en) * | 2010-06-25 | 2012-01-12 | Mitsubishi Electric Corp | High frequency semiconductor package |
| JP2022510411A (en) * | 2018-12-04 | 2022-01-26 | クリー インコーポレイテッド | How to form a packaged transistor device with separate inputs and outputs, and a packaged transistor device with separate inputs and outputs. |
-
1988
- 1988-01-07 JP JP1988000901U patent/JPH01107141U/ja active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006269564A (en) * | 2005-03-22 | 2006-10-05 | Sony Corp | Semiconductor device |
| JP4696621B2 (en) * | 2005-03-22 | 2011-06-08 | ソニー株式会社 | Semiconductor device |
| JP2007019403A (en) * | 2005-07-11 | 2007-01-25 | Toshiba Corp | High frequency package device |
| JP4575247B2 (en) * | 2005-07-11 | 2010-11-04 | 株式会社東芝 | High frequency packaging equipment |
| JP2012009675A (en) * | 2010-06-25 | 2012-01-12 | Mitsubishi Electric Corp | High frequency semiconductor package |
| JP2022510411A (en) * | 2018-12-04 | 2022-01-26 | クリー インコーポレイテッド | How to form a packaged transistor device with separate inputs and outputs, and a packaged transistor device with separate inputs and outputs. |