JPH0325252U - - Google Patents
Info
- Publication number
- JPH0325252U JPH0325252U JP1989085961U JP8596189U JPH0325252U JP H0325252 U JPH0325252 U JP H0325252U JP 1989085961 U JP1989085961 U JP 1989085961U JP 8596189 U JP8596189 U JP 8596189U JP H0325252 U JPH0325252 U JP H0325252U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- view
- lead frame
- showing
- pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
- H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
- H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
- H01L2224/48478—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
- H01L2224/4848—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball outside the semiconductor or solid-state body
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は一実施例を用いて半導体チツプを実装
した状態を示す部分断面図、第２図は同実施例の
部分平面図、第３図は一実施例の製造工程を示す
工程断面図、第４図はインナーリード部がエツチ
ングされた後の金属板を示す図であり、Ａは平面
図、Ｂはその−′線位置での断面図、第５図
は他の実施例を用いて半導体チツプを実装した状
態を示す部分断面図、第６図は従来のリードフレ
ームを用い微細加工された半導体チツプを実装し
た場合を示す平面図、第７図は同従来例の部分断
面図である。
１０……リードフレーム、１２……インナーリ
ード、１４……アイランド、１６……半導体チツ
プ、１８……ワイヤ。
FIG. 1 is a partial sectional view showing a state in which a semiconductor chip is mounted using one embodiment, FIG. 2 is a partial plan view of the same embodiment, and FIG. 3 is a process sectional view showing the manufacturing process of one embodiment. FIG. 4 is a diagram showing the metal plate after the inner lead part has been etched, A is a plan view, B is a cross-sectional view at the -' line position, and FIG. FIG. 6 is a partial sectional view showing a state in which a chip is mounted, FIG. 6 is a plan view showing a case in which a microfabricated semiconductor chip is mounted using a conventional lead frame, and FIG. 7 is a partial sectional view of the same conventional example. 10...Lead frame, 12...Inner lead, 14...Island, 16...Semiconductor chip, 18...Wire.
Claims (1)
プのパツドとの間で接続がなされるインナーリー
ドの板厚がアウターリードの板厚より薄くなつて
いるリードフレーム。 A lead frame in which the inner leads, which are placed facing the semiconductor chip and are connected to the pads of the semiconductor chip, are thinner than the outer leads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989085961U JPH0325252U (en) | 1989-07-21 | 1989-07-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989085961U JPH0325252U (en) | 1989-07-21 | 1989-07-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0325252U true JPH0325252U (en) | 1991-03-15 |
Family
ID=31635352
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989085961U Pending JPH0325252U (en) | 1989-07-21 | 1989-07-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0325252U (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5957439A (en) * | 1982-09-27 | 1984-04-03 | Fujitsu Ltd | Semiconductor device |
| JPS628545A (en) * | 1985-07-05 | 1987-01-16 | Hitachi Ltd | High density lead frame |
| JPS6248053A (en) * | 1985-08-28 | 1987-03-02 | Nec Corp | Manufacture of lead frame for semiconductor device |
| JPS62177953A (en) * | 1986-01-30 | 1987-08-04 | Nec Corp | Lead frame |
-
1989
- 1989-07-21 JP JP1989085961U patent/JPH0325252U/ja active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5957439A (en) * | 1982-09-27 | 1984-04-03 | Fujitsu Ltd | Semiconductor device |
| JPS628545A (en) * | 1985-07-05 | 1987-01-16 | Hitachi Ltd | High density lead frame |
| JPS6248053A (en) * | 1985-08-28 | 1987-03-02 | Nec Corp | Manufacture of lead frame for semiconductor device |
| JPS62177953A (en) * | 1986-01-30 | 1987-08-04 | Nec Corp | Lead frame |