JPS62177953A - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPS62177953A JPS62177953A JP61019414A JP1941486A JPS62177953A JP S62177953 A JPS62177953 A JP S62177953A JP 61019414 A JP61019414 A JP 61019414A JP 1941486 A JP1941486 A JP 1941486A JP S62177953 A JPS62177953 A JP S62177953A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- lead
- semiconductor element
- external connection
- thinner
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 229910001111 Fine metal Inorganic materials 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85385—Shape, e.g. interlocking features
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体素子の搭載に使用するリードフレームに
関し、特に多端子でチップサイズの小さな半導体素子を
搭載するリードフレームに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame used for mounting a semiconductor element, and particularly to a lead frame for mounting a multi-terminal, small-chip semiconductor element.
最近、ＩＣの多機能化に対応し多ビンのパッケージが必
要とされてきている。またＩＣは内部配線の微細化によ
シチップが小さくなっている。これらのことから小チッ
プを搭載する多ビンのリードフレームが要求されるよう
になった。Recently, there has been a need for multi-bin packages to accommodate the increasing functionality of ICs. Furthermore, IC chips are becoming smaller due to miniaturization of internal wiring. For these reasons, a multi-bin lead frame on which small chips can be mounted has become required.
従来のリードフレームは、リード部分の半導体素子と接
続される側の厚さと、外部接続用リードとなる側の厚さ
が同じであシ、外部接続用リードとしては、ＩＣ製品と
するため、リードを曲げて成形するので、このリード成
形に耐える強度を持つのに２００μｍ程度の厚さが必要
であった。In conventional lead frames, the thickness of the lead part on the side connected to the semiconductor element is the same as the thickness on the side that becomes the external connection lead. Since the lead is formed by bending it, a thickness of about 200 μm was required to have enough strength to withstand this lead forming.
リードフレームはエツチング等の方法によシバターン形
成されるが、リードフレームが厚いと微細パターンを形
成することが困難である。このため第３図に示すように
、チップと接続されるリード部分に微細パターンの形成
されていないリードフレームに半導体素子を搭載した場
合には、第４図に示すように、特にチップ３が小さいと
チップ３とリード５との距離が長くなり接続用金属細線
４が長くなシ、金属細線４が垂れ下がる等の変形をし、
隣接リードや他の金属細線と接触することがある。この
ように多ビン化に伴い、接続用金属細線が隣接リードと
接触する々ど製品の歩留シを下げるという欠点があった
。A lead frame is patterned by a method such as etching, but if the lead frame is thick, it is difficult to form a fine pattern. For this reason, as shown in Fig. 3, when a semiconductor element is mounted on a lead frame in which a fine pattern is not formed on the lead portion connected to the chip, as shown in Fig. 4, the chip 3 is particularly small. The distance between the chip 3 and the leads 5 becomes longer, the thin metal wire 4 for connection becomes longer, and the thin metal wire 4 becomes deformed such as hanging down.
May come into contact with adjacent leads or other thin metal wires. As described above, with the increase in the number of bottles, there has been a drawback that whenever the thin metal wire for connection comes into contact with an adjacent lead, the yield of the product decreases.
本発明は上記実情に鑑みてなされたもので、その目的は
リードフレームに微細パターンを形成でき、多ピンであ
りながらチップサイズの小さな半導体素子を搭載しても
、製品の歩留υを下げることのないリードフレームを提
供することにある。The present invention was made in view of the above circumstances, and its purpose is to reduce the yield υ of products even when a fine pattern can be formed on a lead frame and a semiconductor element with a large number of pins and a small chip size is mounted. Our goal is to provide lead frames without lead frames.
本発明の１月−ドフレームは、半導体素子の搭載に使用
するリードフレームにおいて、リードフレームのリード
部分の半導体素子と接続される側の厚さが外部接続用リ
ードとがる側より薄くなっていることを特徴とする。The lead frame of the present invention is a lead frame used for mounting a semiconductor element, in which the thickness of the lead portion of the lead frame on the side connected to the semiconductor element is thinner than the side where the external connection lead is pointed. It is characterized by the presence of
本発明について図面を１照して説明する。第１図は本発
明の一実施例のリードフレームに半導体素子を搭載した
断面図で、第１図に示すようにリードフレームのリード
部分の半導体素子３と金属細線４で接続される側１の厚
さが外部接続用り−ドとなる側２より薄くなっている。The present invention will be explained with reference to the drawings. FIG. 1 is a sectional view of a semiconductor element mounted on a lead frame according to an embodiment of the present invention. As shown in FIG. The thickness is thinner than that of the side 2 which serves as an external connection cord.
このため、第２図に示すようにリードフレームの半導体
系子３と接続される側１に微細パターンを形成すること
が出来るだめ、隣接り・−ドとの距離な保って、リード
が半導体素子搭載部近くまで延びており、接続用金属細
線４の長さも短かいので、金属細線の変形も少ない。For this reason, as shown in FIG. 2, it is possible to form a fine pattern on the side 1 of the lead frame connected to the semiconductor device 3, keeping the distance between the leads and the semiconductor device 3. Since it extends close to the mounting part and the length of the connecting metal thin wire 4 is short, there is little deformation of the metal thin wire.
リードフレームのリード部分の半導体素子と接続される
側を外部接続用リードとなる側より薄くするには、リー
ドフレームのパターンを形成する前に、半導体素子と接
続される側となる部分を予かじめ機械的に研磨すること
により可能となるが、化学エツチングその他の方法によ
っても可能である。In order to make the side of the lead frame of the lead frame that will be connected to the semiconductor element thinner than the side that will become the external connection lead, the side that will be connected to the semiconductor element should be pre-screwed before forming the lead frame pattern. This can be done by mechanical polishing, but it can also be done by chemical etching or other methods.
第５図は本発明の他の実施例を示す断面図であり、リー
ドフレームのリード部分の半導体素子と接続される側が
チップ搭載部に近いほど薄いテーパー状となっている。FIG. 5 is a sectional view showing another embodiment of the present invention, in which the side of the lead portion of the lead frame connected to the semiconductor element becomes thinner and tapered closer to the chip mounting portion.
以上説明したように、本発明はリードフレームのリード
部分の半導体素子と接続される側を外部接続用リードと
なる側より薄くすることにより、リードフレームの半導
体素子と接続される側に微細パターンを形成することが
できるため、隣接リードとの距離を保って、リードを半
導体素子搭載部近くまで延ばすことができ、接続用金属
細線の長さを短くでき、特に多リードでチップサイズの
小さな半導体素子を歩留りよく搭載することができる効
果がある。As explained above, the present invention makes the side of the lead portion of the lead frame that is connected to the semiconductor element thinner than the side that becomes the external connection lead, thereby forming a fine pattern on the side of the lead frame that is connected to the semiconductor element. Since the lead can be extended close to the semiconductor element mounting area while maintaining the distance from adjacent leads, the length of the thin metal wire for connection can be shortened, especially for semiconductor elements with many leads and small chip size. This has the effect of allowing high yields to be loaded.
第１図は本発明の一実施例のリードフレームに半導体素
子を搭載した様子を示す断面図、第２図は本発明の一実
施例の微細パターンを形成したリードフレームの一部平
面図、第３図は従来の微細パターンが形成されていない
リードフレームの一部平面図、第４図は従来の微細パタ
ーンが形成されていないリードフレームにチップサイズ
の小さな半導体素子を搭載し接続用金属細線が垂れ下が
った様子を示す断面図、第５図は本発明の他の実流側の
り・−ドフレームに半導体素子を搭載した様子を示す断
面図である。
１・・・・・・リードフレームの半導体素子と接続され
る側、２・・・・・・リードフレームの外部接続用リー
ドとなる側、３・・・・・・半導体素子、４・・・・・
・金属細線、５−・・・・・従来のリードフレーム。
第１図
奉２ 図
第３ 園
熟４ 回FIG. 1 is a sectional view showing a semiconductor element mounted on a lead frame according to an embodiment of the present invention, FIG. 2 is a partial plan view of a lead frame on which a fine pattern is formed according to an embodiment of the present invention, and FIG. Figure 3 is a partial plan view of a conventional lead frame on which fine patterns are not formed, and Figure 4 is a partial plan view of a conventional lead frame on which fine patterns are not formed, with a semiconductor element of small chip size mounted and thin metal wires for connection. FIG. 5 is a cross-sectional view showing a state in which a semiconductor element is mounted on another actual flow side glued frame according to the present invention. 1... Side of the lead frame to be connected to the semiconductor element, 2... Side of the lead frame that becomes an external connection lead, 3... Semiconductor element, 4...・・・
・Thin metal wire, 5-...Conventional lead frame. 1st picture 2nd picture 3 Sonju 4 times
Claims (1)
、該リードフレームのリード部分の半導体素子と接続さ
れる側の厚さが外部接続用リードとなる側より薄くなっ
ていることを特徴とするリードフレーム。A lead frame used for mounting a semiconductor element, characterized in that the side of the lead portion of the lead frame that is connected to the semiconductor element is thinner than the side that becomes an external connection lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61019414A JPS62177953A (en) | 1986-01-30 | 1986-01-30 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61019414A JPS62177953A (en) | 1986-01-30 | 1986-01-30 | Lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62177953A true JPS62177953A (en) | 1987-08-04 |
Family
ID=11998594
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61019414A Pending JPS62177953A (en) | 1986-01-30 | 1986-01-30 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62177953A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63173351A (en) * | 1987-01-13 | 1988-07-16 | Toshiba Corp | Lead frame of semiconductor device |
| EP0347238A2 (en) * | 1988-06-17 | 1989-12-20 | Ngk Insulators, Ltd. | Minutely patterned structure, and method of producing the same |
| JPH0325252U (en) * | 1989-07-21 | 1991-03-15 | ||
| US5451813A (en) * | 1991-09-05 | 1995-09-19 | Rohm Co., Ltd. | Semiconductor device with lead frame having different thicknesses |
-
1986
- 1986-01-30 JP JP61019414A patent/JPS62177953A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63173351A (en) * | 1987-01-13 | 1988-07-16 | Toshiba Corp | Lead frame of semiconductor device |
| EP0347238A2 (en) * | 1988-06-17 | 1989-12-20 | Ngk Insulators, Ltd. | Minutely patterned structure, and method of producing the same |
| JPH0325252U (en) * | 1989-07-21 | 1991-03-15 | ||
| US5451813A (en) * | 1991-09-05 | 1995-09-19 | Rohm Co., Ltd. | Semiconductor device with lead frame having different thicknesses |
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