JPS61148856A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61148856A
JPS61148856A JP59270820A JP27082084A JPS61148856A JP S61148856 A JPS61148856 A JP S61148856A JP 59270820 A JP59270820 A JP 59270820A JP 27082084 A JP27082084 A JP 27082084A JP S61148856 A JPS61148856 A JP S61148856A
Authority
JP
Japan
Prior art keywords
leads
terminals
lead
package
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59270820A
Other languages
Japanese (ja)
Inventor
Toshinori Hirashima
平島　利宣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59270820A priority Critical patent/JPS61148856A/en
Publication of JPS61148856A publication Critical patent/JPS61148856A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49534—Multi-layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent unexpected accidents such as contact of terminals, by bending external connecting terminals so that the connecting terminals are overlapped, and improving the strength without shortening the distance between the terminals. CONSTITUTION:Leads 4 and 5 are bent in an overlapped state. Tip parts 4a and 5a of the leads are compressed to the base parts of the leads 4 and 5 by a package 6. As a result, the mechanical strengths of the leads 4 and 5 become approximately twice, but the area observed from the upper part is not changed. Therefore, the strengths of the leads can be improved without changing the intervals between the leads 4 and 5 and the neighboring other leads. Thus the integration degree of an IC chip 2 is improved. Even if the number of the leads is increased thereby, accidents such as contact between the leads can be decreased.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は半導体装置に関し、特に小型パッケージで多リ
ード端子を有する半導体集積回路に用いて有効な技術に
関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to a technique effective for use in a semiconductor integrated circuit having a small package and multiple lead terminals.

〔背景技術〕[Background technology]

ｒｓｏｌｉｄ　５ｔａｔｅ　ｔｅｃｈｎｏｌｇｙＪ（日
本版、　Ｓｅｐｔｅｍｂｅｒ１９８２、ｐ７１）には、
ＩＣチップ集積度の向上にともないリード数が増加し、
しかもパッケージの小型化が要求されているので、パッ
ケージの寸法、端子位置に関する余裕度が一層きｐ　Ｌ
／　＜　ｆ；っている、との記載がある。rsolid 5tate technologyJ (Japanese version, September 1982, p71),
As IC chip integration increases, the number of leads increases.
Moreover, as there is a demand for smaller packages, there is more leeway regarding package dimensions and terminal positions.
There is a statement that / <f;

一方、半導体集積回路の製造工程はもとより。On the other hand, not only the manufacturing process of semiconductor integrated circuits.

運搬時、実装時においては、端子数が少なく、しかも端
子位置の余裕度が充分にあった方が端子間の接触などが
発生しにくく好都合である。During transportation and mounting, it is advantageous if the number of terminals is small and there is sufficient margin for terminal position, since contact between the terminals is less likely to occur.

本発明者は、半導体集積回路に関する上記技術的動向と
実務的な希望条件とを検討し、両者を満足し得る半導体
装置を提供するに至った。The present inventor has studied the above-mentioned technical trends and practical desired conditions regarding semiconductor integrated circuits, and has now provided a semiconductor device that can satisfy both.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、パッケージから突出する外部接続端子
の端子間距離を狭めることなく上記端子の強度を向上さ
せ、端子間の接触などの不測の事故の発生を低減し得る
半導体装置を提供すること　　′にある。　　　、 本発明の上記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面から明らかになるであろう。An object of the present invention is to provide a semiconductor device in which the strength of external connection terminals protruding from a package can be improved without narrowing the distance between the terminals, and the occurrence of unexpected accidents such as contact between the terminals can be reduced. 'It is in. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

【Ｒ明の概要〕[Overview of R-ming]

本、願において開示される発明の概要を簡単に述べれば
、下記の通りである。A brief summary of the invention disclosed in this application is as follows.

すなわち、パッケージから所定間隔をもって突出した外
部接続端子を該接続端子に重ね合せるように折り曲げる
ことにより、各端子間の距離を狭めることなく強度を向
上せしめ、各端子の接触等の不測の事故を低減する、と
いう本発明の目的を達成するものである。In other words, by bending the external connection terminals that protrude from the package at predetermined intervals so as to overlap the connection terminals, strength is improved without reducing the distance between each terminal, and unexpected accidents such as contact between the terminals are reduced. This achieves the object of the present invention.

〔実施例−１〕 以下、第１図を参照して本発明を適用した半導体装置の
第１実施例を説明する。なお、以下に述べる各実施例は
、半導体装置として半導体集積回路への適用例を示すも
のである。[Embodiment 1] Hereinafter, a first embodiment of a semiconductor device to which the present invention is applied will be described with reference to FIG. Note that each of the embodiments described below shows an example of application to a semiconductor integrated circuit as a semiconductor device.

本実施例の特徴は、半導体集積回路（以下においてＩＣ
という）の各外部接続端子を折り曲げて、その先端部を
パッケージにて固定したことにある。The feature of this embodiment is that the semiconductor integrated circuit (hereinafter referred to as IC)
), each external connection terminal is bent and the tip is fixed with a package.

ＩＣＩにおいて、２はＩＣチップ、３はタブ、４．５は
外部接続端子（以下においてリードという）である、そ
して各リード４，５とＩＣチップ２のタップとの間は、
例えばＡｕ線６，７によって接続されている。In the ICI, 2 is an IC chip, 3 is a tab, 4.5 is an external connection terminal (hereinafter referred to as a lead), and between each lead 4, 5 and the tap of the IC chip 2,
For example, they are connected by Au wires 6 and 7.

ここで注目すべきは、リード４，５の構造である。What should be noted here is the structure of the leads 4 and 5.

すなわち、リード４，５は図示の如く２枚重ねに折り曲
げられ、その先端部４ａ、５ａはパッケージ６によって
各リード４，５の基部に圧接させられている。この結果
、各リード４，５の機械的強度はほぼ２倍になるが、上
面からみた面積は変らない。従らて、各リード４，５に
隣接して設けられた他のリード（図示せず）との間の距
離、換言すれば間隔を変えることなく、その強度が向上
されたことになる。That is, the leads 4 and 5 are bent into two layers as shown in the figure, and their tips 4a and 5a are pressed against the base of each lead 4 and 5 by the package 6. As a result, the mechanical strength of each lead 4, 5 is approximately doubled, but the area seen from the top surface remains unchanged. Therefore, the strength can be improved without changing the distance between each lead 4, 5 and another lead (not shown) provided adjacent to it, in other words, the interval.

故に、ＩＣチップ２の集積度が向上し、これにともなっ
てリード数が増大しても、各リード間の接触等の不所望
な事故を低減することができる。Therefore, even if the degree of integration of the IC chip 2 improves and the number of leads increases accordingly, undesirable accidents such as contact between the leads can be reduced.

（実施例−２〕 次に、第２図を参照して本発明の第２実施例を説明する
。(Example 2) Next, a second example of the present invention will be described with reference to FIG.

なお、上記第１実施例と同一の部分には同一の符号を附
し、説明の重複を避るものとする。Note that the same parts as in the first embodiment are given the same reference numerals to avoid duplication of explanation.

本実施例の特徴は、各リード４，５の先端部４ａ。A feature of this embodiment is the tip portion 4a of each lead 4,5.

５ａをパッケージ６によって固定せず、言わば開放端と
したことにある。上記構造によれば、各リード４．５の
折り曲げ作業は、パッケージング以前におこなってよく
、その後であってもよい、換言すれば、製造工程が限定
されることなく自由度が増すことになる。　　　　　　
　　　　　　　　□一方、強度についてみると、先端部
４ａ、５ａとパッケージ６の側面の距離が小であるので
二上記折り曲げを行わない場合に托較すればその強度は
遥かに大であり、第１実施例同様の効果が得られる。　
　　　　　　　　　　　　　　・・　５　　　。5a is not fixed by the package 6, but rather has an open end. According to the above structure, the bending work of each lead 4.5 may be performed before or after packaging. In other words, the manufacturing process is not limited and the degree of freedom is increased. .
□On the other hand, when looking at the strength, since the distance between the tips 4a, 5a and the side surface of the package 6 is small, the strength is much greater when compared to the case where the bending described above is not performed. A similar effect can be obtained.
... 5.

しかも、本実施例に示した構造によれば、各リード４，
５の形成に要する金属板の総体面積を□削減できるので
、その分ＩＣ１の生産コストを低減することができる。Moreover, according to the structure shown in this embodiment, each lead 4,
Since the total area of the metal plate required for forming the IC 5 can be reduced, the production cost of the IC 1 can be reduced accordingly.

なお、上記削減量は各リード４．５に要求される強度と
の関連で決定される。Note that the above reduction amount is determined in relation to the strength required for each lead 4.5.

〔効果〕〔effect〕

（１）ＩＣの各リードを２枚重ねに折り曲げたので、上
面からみた面積は変らず体積が増大して゛機械的強度も
大となり、各リード間の距離を狭めることなく各リード
相互の接触、或いは不所望な変形を低減する、という効
果が得られる。(1) Since each lead of the IC is folded into two layers, the area seen from the top surface remains unchanged, the volume increases, and the mechanical strength is also increased, allowing the leads to contact each other without reducing the distance between them. Alternatively, the effect of reducing undesired deformation can be obtained.

以上に本発明によってな□された発明を実施例に゛もと
づき具体的に説明したが、本発明は上記実施例に限定さ
れるものではなく、その要旨を逸脱しない範囲で種々変
更可能であることは言うまでもない。Although the invention made by the present invention has been specifically explained above based on examples, the present invention is not limited to the above-mentioned examples, and various changes can be made without departing from the gist thereof. Needless to say.

例えば、ＩＣチップはタブ下げ構造のタブ上に設けても
よい、　　　′ また、第１実施例を例に述べると、各先端部４ａ。For example, the IC chip may be provided on a tab of a tab lowering structure.' Further, taking the first embodiment as an example, each tip portion 4a.

５ａを点線のように上方に折り曲げ、水分の浸透を低減
させ、ＩＣの耐湿性が向上するように構成してもよい、
　　　　　　　　′ 〔利用分野〕 以上の説明では主として本発明者によってなされた発明
をその背景となった技術分野であるＩＣのカードに適用
した場合について説明したが、それに限定されるもので
はない。5a may be bent upward as shown by the dotted line to reduce moisture penetration and improve the moisture resistance of the IC.
[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to an IC card, which is the technical field in which the invention is based, but the present invention is not limited thereto.

例えばＩＣの形状の如何に関わらず、各種のＩＣ１半導
体装置に利用することができる。For example, it can be used in various IC1 semiconductor devices regardless of the shape of the IC.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の第１実施例を示すＩＣの要部の断面図
を示し、 第２図は第２実施例を示すＩＣの要部の断面図を示す。 ■・・・ＩＣ１２・・・ＩＣチップ、３・・・タブ、４
，５・・・リード、４ａ、５ａ・・・先端部、６・・・
ノ（ツケージ。 第　　１　　図 第　　２　　図 １　　　　　　σ　　　ＣFIG. 1 shows a sectional view of a main part of an IC showing a first embodiment of the present invention, and FIG. 2 shows a sectional view of a main part of an IC showing a second embodiment. ■...IC12...IC chip, 3...tab, 4
, 5... Lead, 4a, 5a... Tip, 6...
Figure 1 Figure 2 Figure 1 σ C

Claims (1)

【特許請求の範囲】[Claims] １、外部接続端子の先端部を該外部接続端子のパッケー
ジからの突出位置方向に折り曲げたことを特徴とする半
導体装置。1. A semiconductor device characterized in that the tip of the external connection terminal is bent in the direction of the position where the external connection terminal protrudes from the package.
JP59270820A 1984-12-24 1984-12-24 Semiconductor device Pending JPS61148856A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59270820A JPS61148856A (en) 1984-12-24 1984-12-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59270820A JPS61148856A (en) 1984-12-24 1984-12-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61148856A true JPS61148856A (en) 1986-07-07

Family

ID=17491467

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59270820A Pending JPS61148856A (en) 1984-12-24 1984-12-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61148856A (en)

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