JPS61148855A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61148855A JPS61148855A JP27081984A JP27081984A JPS61148855A JP S61148855 A JPS61148855 A JP S61148855A JP 27081984 A JP27081984 A JP 27081984A JP 27081984 A JP27081984 A JP 27081984A JP S61148855 A JPS61148855 A JP S61148855A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- leads
- twisted
- external connecting
- connecting terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
- H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置、特に多数の外部接続端子を必要と
する半導体集積回路に用いて有効な技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique that is effective for use in semiconductor devices, particularly semiconductor integrated circuits that require a large number of external connection terminals.
ｒｓｏｌｉｄ ５ｔａｔｅ ｔｅｃｈｎｏ１ｇｙ日本版
Ｊ （Ｓｅｐ、 １９１２Ｐ６９〜Ｐ７２）には、半
導体集積回路の機能密度の増加、リード（外部接続端子
）数の増加にともなってパッケージの寸法、端子位置に
関する余裕が一層きびしくなっている、との記載がある
。rsolid 5tate technology Japanese version J (Sep, 1912 P69-P72) states that as the functional density of semiconductor integrated circuits increases and the number of leads (external connection terminals) increases, margins regarding package dimensions and terminal positions become more stringent. There is a description that there is.
このため、高集積度の半導体集積回路においては、各外
部接続端子の間隔を狭めるとともに、各外部接続端子自
体を細くして、多数の外部接続端子を設けるようにして
いる。For this reason, in highly integrated semiconductor integrated circuits, the distance between each external connection terminal is narrowed, and each external connection terminal itself is made thinner, so that a large number of external connection terminals are provided.
しかし１本発明者の検討によると、上記構成では各外部
接続端子が曲がり易く、その上間隔が狭いので必然的に
配線パターンの間隔も狭くせねばならず、このため実装
時にハンダショートが発生し易い、などの問題点が明ら
かになった。However, according to the inventor's study, in the above configuration, each external connection terminal is easy to bend, and the spacing between them is narrow, so the spacing between the wiring patterns must also be narrowed, and as a result, solder shorts may occur during mounting. Problems such as ease of use were clarified.
本発明の目的は、多数の外部接続端子を設けるとともに
、実装時におけるハンダショートなどの不測の事故を低
減し得る半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device that is provided with a large number of external connection terminals and that can reduce unexpected accidents such as solder shorts during mounting.
本発明の上記ならびにその他の目的と新規な特徴は、本
発明書の記述及び添付図面から明らかになるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present invention and the accompanying drawings.
本願において開示される発明の概要を簡単に述べれば、
下記の通りである。A brief summary of the invention disclosed in this application is as follows:
It is as follows.
すなわち、半導体集積回路のパッ゛ケージの側面から突
出する板状の外部接続端子を捻り構造にして補強すると
ともに、各外部接続端子間の間隔を実質的に拡大して外
部接続端子の曲がり、ハンダショートなどを低減する、
という本発明の目的を達成するものである。In other words, the plate-shaped external connection terminals protruding from the side surface of the semiconductor integrated circuit package are reinforced with a twisted structure, and the spacing between each external connection terminal is substantially expanded to prevent bending and soldering of the external connection terminals. Reduces short circuits, etc.
This achieves the object of the present invention.
〔実施例−１〕
以下、第１図〜第３図を参照して本発明を適用した半導
体装置の第１実施例を説明する。なお、第１図は面実装
型と呼ばれている半導体集積回路（以下においてＩＣと
いう）の斜視図を示し、第２図はＩＣの要部の平面図を
示し、第３図は要部の側面図を示す。[Embodiment 1] Hereinafter, a first embodiment of a semiconductor device to which the present invention is applied will be described with reference to FIGS. 1 to 3. Note that Fig. 1 shows a perspective view of a semiconductor integrated circuit (hereinafter referred to as IC) called a surface-mount type, Fig. 2 shows a plan view of the main parts of the IC, and Fig. 3 shows the main parts of the IC. A side view is shown.
本実施例の特徴は、外部接続端子（以下においてリード
という）捻り構造としたことにある。The feature of this embodiment is that the external connection terminal (hereinafter referred to as lead) has a twisted structure.
第１図に示すように、ＩＣ１を構成するパッケージ２の
外周囲からは多数のり一部３が突出している。そして、
根元付近では水平状であるが約９０度に捻ることにより
、その先端部は板状体が垂直に直立したような状態にな
っている。As shown in FIG. 1, a large number of adhesive portions 3 protrude from the outer periphery of a package 2 constituting an IC 1. As shown in FIG. and,
It is horizontal near the base, but by twisting it about 90 degrees, the tip becomes like a plate-shaped body standing vertically.
リード３を上記構造に形成することにより、各リード３
の間隔１が第２図に示すように実質的に拡大される。By forming the leads 3 in the above structure, each lead 3
The distance 1 is substantially enlarged as shown in FIG.
すなわち、仮りにリード３が仮想線で示すように広幅の
ままであるとすると、配線パターン４もこれに対応して
仮想線で示す如く広幅にしなければならず、このままで
は配線パターン４の間隔がせまくなり、実装時にハンダ
シュートなどが発生し易い。しかし、リード３を捻るこ
とにより、リード３の間隔１が拡大されるので、配線パ
ターン４は点線で示すように極めて狭い幅に形成するこ
とができる。従って、リード３を上記構成になすことに
より、配線パターン４間の隙間を大にすることができ、
ハンダディップ時におけるハンダショートの発生を低減
することができる。That is, if the lead 3 remains wide as shown by the imaginary line, the wiring pattern 4 must also be made wide correspondingly as shown by the imaginary line, and if this continues, the spacing between the wiring patterns 4 will become wider. It becomes narrow, and solder shoots are likely to occur during mounting. However, by twisting the leads 3, the interval 1 between the leads 3 is expanded, so that the wiring pattern 4 can be formed to have an extremely narrow width as shown by the dotted line. Therefore, by making the leads 3 have the above structure, the gap between the wiring patterns 4 can be increased.
The occurrence of solder shorts during solder dipping can be reduced.
また、リード３を上記構造になすことし；より、ハンダ
ディップ時におけるハンダのりを良好にすることもでき
る。Further, by forming the lead 3 in the above structure, it is possible to improve solder adhesion during solder dipping.
すなわち、実装時においては、各リード３の垂直部が第
３図に示すようにプリント基板５上に形成された配線パ
ターン４上に直立する。That is, during mounting, the vertical portion of each lead 3 stands upright on the wiring pattern 4 formed on the printed circuit board 5, as shown in FIG.
そして、ハンダディップ時においては、上記垂直部に沿
ってハンダ６が伸び上がり、リード３と配線パターン４
とを確実にハンダ付けする。Then, during solder dipping, the solder 6 stretches up along the vertical portion, and the lead 3 and the wiring pattern 4
Make sure to solder.
また、上記捻り部分においては、リード３が上下、左右
の何れにも変形しにくくリード３の変形が低減する。Further, in the twisted portion, the lead 3 is difficult to deform either vertically or horizontally, and deformation of the lead 3 is reduced.
〔実施例−２〕
次に１本発明の第２実施例を第４図を参照して説明する
。[Embodiment 2] Next, a second embodiment of the present invention will be described with reference to FIG. 4.
なお１本実施例は面実装型以外のＩＣに本発明を適用し
た例を示すものである。Note that this embodiment shows an example in which the present invention is applied to an IC other than a surface-mount type.
第４図に示すように、水平方向に突当したり一部１３は
、一旦垂直方向に折り曲げられ、しかる後に捻られてい
る。この形状によれば、各リード１３間の間隔を上記の
如く実質的に拡大することができ、しかもハンダ付けも
上記同様に確実に行い得られる。As shown in FIG. 4, the horizontally abutting portion 13 is once bent vertically and then twisted. According to this shape, the distance between the leads 13 can be substantially increased as described above, and soldering can also be performed reliably as described above.
また、ハンダショート、リード１３の変形低減について
も、上記同様の効果かえられる。Furthermore, the same effects as described above can be achieved in reducing solder shorts and deformation of the leads 13.
〔実施例−３〕
次に１本発明の第３実施例を第５図を参照して説明する
。[Embodiment 3] Next, a third embodiment of the present invention will be described with reference to FIG.
本実施例は、上記第１及び第２実施例を併合したもので
ある。This embodiment is a combination of the first and second embodiments described above.
第５図に示すように、各リード３，１３が二段にわたっ
て設けられている。この場合、ＩＣチップ（図示せず）
はパッケージ２内において積層して設けられ、下段のＩ
Ｃチップがリード３に接続され、上段のＩＣチップがリ
ード１３に接続される。As shown in FIG. 5, each lead 3, 13 is provided in two stages. In this case, an IC chip (not shown)
are provided in a stacked manner within the package 2, and the lower I
The C chip is connected to lead 3, and the upper IC chip is connected to lead 13.
上部構成によれば、リード３，１３が配線パターン４に
接触する位置ではり−ド３，１３の間隔が大になってい
るので、多数のリードを設けるにも関わらず、ハンダシ
ョートなどの事故を低減し得る。According to the upper structure, the distance between the leads 3 and 13 is large at the position where the leads 3 and 13 come into contact with the wiring pattern 4, so accidents such as solder shorts can occur even though a large number of leads are provided. can be reduced.
（，１，） 、、Ｉ Ｃのリードを捻り構造にしたこと
により、リード９先！部の間隔を実質的に大にすること
ができ、多数のリードを設け、かつリード間の接触を低
減する、という効果が得られる°。(,1,) ,,By making the IC lead into a twisted structure, the lead is 9 points ahead! It is possible to substantially increase the distance between the parts, provide a large number of leads, and reduce contact between the leads.
（２）上記（１）により、配線パターンの間隔も大にす
ることができるので、ハンダディップ時におけるハンダ
シュートを低減することができる。(2) According to (1) above, the intervals between the wiring patterns can be increased, so that solder shoots during solder dipping can be reduced.
以下に本発明者によってなされた発明を実施例にもとづ
き具体的に説明したが、本発明は上記実施例に限定され
るものではなく、その要旨を逸脱しない範囲で種々変更
可能であることは言うまでもない。The invention made by the present inventor has been specifically explained below based on Examples, but it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. stomach.
例えば、第３実施例に示す構造では、高集積密度の１個
のＩＣにつき、上記の如き形態でリードを設けてもよい
。For example, in the structure shown in the third embodiment, a lead may be provided in the form described above for one IC with high integration density.
以上の説明では、主として本発明者によってなされた発
明をその背景となった利用分野であるＩＣのリードに適
用した場合について説明したが、それに限定されるもの
ではなく、半導体装置全搬に利用することができる。In the above explanation, the invention made by the present inventor was mainly applied to IC leads, which is the field of application that formed the background of the invention, but it is not limited to this, and it can be applied to the entire transportation of semiconductor devices. be able to.
本発明はすくなくとも、各種のソケットの端子などに利
用することができる。The present invention can be used at least for terminals of various sockets.
第１図〜第３図は本発明を適用したＩＣの第１実施例を
示すものであり、
第１図は上記ＩＣの斜視図を示し、
第２図は上記ＩＣの要部の平面図を示し、第３図は上記
ＩＣの要部の側面図を示し、第４図は本発明の第２実施
例を示すＩＣの要部の斜視図を示し、
第５図は本発明の第３実施例を示すＩＣの要部の斜視図
を示し、
１・・・ＩＣ，２・・・パッケージ、３．１３・・・リ
ード。
４・・・配線パターン、５・・・プリント基板、６・・
・ハンダ。
第 １ 図
／、
第 ２ 図
第 ４ 図
第 ５ 図1 to 3 show a first embodiment of an IC to which the present invention is applied, FIG. 1 shows a perspective view of the above IC, and FIG. 2 shows a plan view of the main parts of the above IC. FIG. 3 shows a side view of the main parts of the above IC, FIG. 4 shows a perspective view of the main parts of the IC showing the second embodiment of the invention, and FIG. 5 shows a third embodiment of the invention. A perspective view of the main parts of an IC is shown as an example. 1...IC, 2...Package, 3.13...Lead. 4... Wiring pattern, 5... Printed circuit board, 6...
・Solder. Figure 1/, Figure 2, Figure 4, Figure 5
Claims (1)
導体装置。1. A semiconductor device characterized in that an external connection terminal has a twisted structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59270819A JPH0618246B2 (en) | 1984-12-24 | 1984-12-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59270819A JPH0618246B2 (en) | 1984-12-24 | 1984-12-24 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61148855A true JPS61148855A (en) | 1986-07-07 |
| JPH0618246B2 JPH0618246B2 (en) | 1994-03-09 |
Family
ID=17491452
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59270819A Expired - Lifetime JPH0618246B2 (en) | 1984-12-24 | 1984-12-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0618246B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0310530A (en) * | 1989-06-08 | 1991-01-18 | Matsushita Electric Ind Co Ltd | Control method for mca controlled station talk time mode |
| JPH0383953U (en) * | 1989-12-15 | 1991-08-26 | ||
| JP2011114137A (en) * | 2009-11-26 | 2011-06-09 | Mitsubishi Electric Corp | Power semiconductor device |
| JP2013211945A (en) * | 2012-03-30 | 2013-10-10 | Hitachi Automotive Systems Ltd | On-vehicle motor and electric power steering device using the same |
| JP2018110143A (en) * | 2016-12-28 | 2018-07-12 | 三菱電機株式会社 | Semiconductor device, power converter, lead frame, and manufacturing method of semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5324208U (en) * | 1976-08-06 | 1978-03-01 | ||
| JPS58193414U (en) * | 1982-06-14 | 1983-12-22 | パイオニア株式会社 | flat cable |
-
1984
- 1984-12-24 JP JP59270819A patent/JPH0618246B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5324208U (en) * | 1976-08-06 | 1978-03-01 | ||
| JPS58193414U (en) * | 1982-06-14 | 1983-12-22 | パイオニア株式会社 | flat cable |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0310530A (en) * | 1989-06-08 | 1991-01-18 | Matsushita Electric Ind Co Ltd | Control method for mca controlled station talk time mode |
| JPH0383953U (en) * | 1989-12-15 | 1991-08-26 | ||
| JP2011114137A (en) * | 2009-11-26 | 2011-06-09 | Mitsubishi Electric Corp | Power semiconductor device |
| JP2013211945A (en) * | 2012-03-30 | 2013-10-10 | Hitachi Automotive Systems Ltd | On-vehicle motor and electric power steering device using the same |
| JP2018110143A (en) * | 2016-12-28 | 2018-07-12 | 三菱電機株式会社 | Semiconductor device, power converter, lead frame, and manufacturing method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0618246B2 (en) | 1994-03-09 |
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