JPH04199552A - Ic package - Google Patents
Ic packageInfo
- Publication number
- JPH04199552A JPH04199552A JP2335375A JP33537590A JPH04199552A JP H04199552 A JPH04199552 A JP H04199552A JP 2335375 A JP2335375 A JP 2335375A JP 33537590 A JP33537590 A JP 33537590A JP H04199552 A JPH04199552 A JP H04199552A
- Authority
- JP
- Japan
- Prior art keywords
- package
- lead terminal
- dummy lead
- heat radiation
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000017525 heat dissipation Effects 0.000 claims description 4
- 230000005855 radiation Effects 0.000 abstract description 3
- 230000000191 radiation effect Effects 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract 3
- 230000000694 effects Effects 0.000 description 5
- 210000001015 abdomen Anatomy 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明はT S OP (Th1n Small O
utlinePackage) 形I Cパッケージの
リード端子構造に関するものである。[Detailed Description of the Invention] [Industrial Field of Application] This invention is applicable to T S OP (Th1n Small O
utlinePackage) This relates to the lead terminal structure of an IC package.
第5図〜第7図は従来のTSOP形ICパッケージの平
面図、正面図および側面図である。5 to 7 are a plan view, a front view, and a side view of a conventional TSOP type IC package.
図において、(1)はICパッケージ、(2)はICパ
ッケージ(1)のリードである。In the figure, (1) is an IC package, and (2) is a lead of the IC package (1).
TSOP形ICパッケージ(1)はパッケージの2側面
に細いリート(2)が設けられ、リード(2)は2状に
形成されている。A TSOP type IC package (1) is provided with thin leads (2) on two sides of the package, and the leads (2) are formed in two shapes.
このように構成されたICパッケージ(1)において、
リードを通じてICパッケージ(1)内部のLSI回路
と外部回路の信号のやりとりが行なわれる。In the IC package (1) configured in this way,
Signals are exchanged between the LSI circuit inside the IC package (1) and the external circuit through the leads.
従来のICパッケージは以上のように構成されていたの
で、熱抵抗か高く、また、TSOP形ICパッケージは
高さの制限か有る基板に実装する場合、ICパッケージ
上部に放熱板を取付ける事ができないという問題点かあ
った。Conventional IC packages have the above structure, so their thermal resistance is high, and when TSOP type IC packages are mounted on a board with height restrictions, it is not possible to attach a heat sink to the top of the IC package. There was a problem.
この発明は上記のような問題点を解決するためになされ
たもので、TSOP形ICパッケージの放熱効果を向上
させる事を目的とする。This invention was made to solve the above-mentioned problems, and its purpose is to improve the heat dissipation effect of a TSOP type IC package.
この発明に係るICパッケージは、TSOP形ICパッ
ケージの空いている側面にダミーリード端子を設けたも
のである。The IC package according to the present invention is a TSOP type IC package in which dummy lead terminals are provided on the vacant side surfaces.
この発明におけるICパッケージは、ダミーリード端子
を設けたことにより放熱効果か向上して熱抵抗を低減す
る。The IC package of the present invention improves heat dissipation effect and reduces thermal resistance by providing dummy lead terminals.
以下この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第1図〜第3図はこの発明の一実施例であるTSOP形
ICパッケージの平面図、正面図および側面図、第4図
は第1図〜第3図のダミーリード端子(5)と基板(4
)との取付状態を示す部分拡大正面図である。1 to 3 are a plan view, a front view, and a side view of a TSOP type IC package that is an embodiment of the present invention, and FIG. 4 is a diagram showing the dummy lead terminal (5) and the board shown in FIGS. (4
) is a partially enlarged front view showing the attached state.
図において、(1)はICパッケージ、(2)はリード
端子、(3)は基板上の配線パターン、(4)は基板、
(5)は放熱用のダミーリード端子である。In the figure, (1) is the IC package, (2) is the lead terminal, (3) is the wiring pattern on the board, (4) is the board,
(5) is a dummy lead terminal for heat radiation.
次に動作について説明する。Next, the operation will be explained.
本実施例におけるICパッケージ(1)はTSOP形I
Cパッケージの空いている側面にダミーリード端子(5
)を設け、基板(4)のVss等の太い配線パターン(
3)と接続することにより、その放熱効果を向上させた
ものである。The IC package (1) in this example is TSOP type I.
Connect dummy lead terminals (5
), and thick wiring patterns such as Vss on the board (4) (
3), the heat dissipation effect is improved.
なお、上記実施例ては幅の広いダミーリード端子(5)
を設けた場合を示したか、通常のリート端子と同形のタ
ミーリード端子を設けてもよい。In addition, in the above embodiment, a wide dummy lead terminal (5) is used.
However, a tummy lead terminal having the same shape as a normal lead terminal may also be provided.
また、ダミーリード端子の先端は2状でなくコの字状に
内側にまげでもよい。Furthermore, the tips of the dummy lead terminals may be bent inward in a U-shape instead of being bi-shaped.
以上のようにこの発明によれば、放熱用のタミーリード
端子を設けたので、放熱効果が増大し、熱抵抗を下げら
れるという効果が有る。As described above, according to the present invention, since the tummy lead terminal for heat radiation is provided, the heat radiation effect is increased and the thermal resistance is reduced.
第1図〜第3図はこの発明の一実施例によるICパッケ
ージの平面図、正面図および側面図、第4図は第1図の
ICパッケージを実装した状態を示す部分拡大正面図、
第5図〜第7図は従来のICパッケージの平面図、正面
図および側面図である。
図において、(1)はTCCバラゲージ(2)はリード
、(3)は基板の配線パターン、(4)は基板、(5)
はダミーリード端子を示す。
なお、図中、同一符号は同一、または相当部分を示す。
第1図
第4図1 to 3 are a plan view, a front view, and a side view of an IC package according to an embodiment of the present invention, and FIG. 4 is a partially enlarged front view showing a state in which the IC package of FIG. 1 is mounted.
5 to 7 are a plan view, a front view, and a side view of a conventional IC package. In the figure, (1) is the TCC barrier gauge (2) is the lead, (3) is the wiring pattern of the board, (4) is the board, (5) is
indicates a dummy lead terminal. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Figure 1 Figure 4
Claims (1)
ード端子を設けた事を特徴とするICパッケージAn IC package characterized by having dummy lead terminals for heat dissipation in a TSOP type IC package.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2335375A JPH04199552A (en) | 1990-11-28 | 1990-11-28 | Ic package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2335375A JPH04199552A (en) | 1990-11-28 | 1990-11-28 | Ic package |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04199552A true JPH04199552A (en) | 1992-07-20 |
Family
ID=18287837
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2335375A Pending JPH04199552A (en) | 1990-11-28 | 1990-11-28 | Ic package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04199552A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0629153U (en) * | 1992-09-17 | 1994-04-15 | アイワ株式会社 | Electronic parts |
US9472538B2 (en) | 2013-07-04 | 2016-10-18 | Mitsubishi Electric Corporation | Semiconductor device manufacturing method and semiconductor device |
NL2022346A (en) * | 2018-01-17 | 2019-07-25 | Shindengen Electric Mfg | Electronic module |
-
1990
- 1990-11-28 JP JP2335375A patent/JPH04199552A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0629153U (en) * | 1992-09-17 | 1994-04-15 | アイワ株式会社 | Electronic parts |
US9472538B2 (en) | 2013-07-04 | 2016-10-18 | Mitsubishi Electric Corporation | Semiconductor device manufacturing method and semiconductor device |
JP6065978B2 (en) * | 2013-07-04 | 2017-01-25 | 三菱電機株式会社 | Semiconductor device manufacturing method, semiconductor device |
NL2022346A (en) * | 2018-01-17 | 2019-07-25 | Shindengen Electric Mfg | Electronic module |
US11309250B2 (en) | 2018-01-17 | 2022-04-19 | Shindengen Electric Manufacturing Co., Ltd. | Electronic module |
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