JPH04170057A - Ic package - Google Patents

Ic package

Info

Publication number
JPH04170057A
JPH04170057A JP2297533A JP29753390A JPH04170057A JP H04170057 A JPH04170057 A JP H04170057A JP 2297533 A JP2297533 A JP 2297533A JP 29753390 A JP29753390 A JP 29753390A JP H04170057 A JPH04170057 A JP H04170057A
Authority
JP
Japan
Prior art keywords
package
external leads
external
flat part
adjacent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2297533A
Other languages
Japanese (ja)
Inventor
Kobo Minami
南　弘法
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP2297533A priority Critical patent/JPH04170057A/en
Publication of JPH04170057A publication Critical patent/JPH04170057A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent short-circuits due to solder between adjacent external leads by a method wherein first and second external leads with a different length or shape are alternately located. CONSTITUTION:A dimension up to a top of respective flat parts 4, 5 of first and second external leads 2, 3 extending outside from four sides of an IC package 1 is different. Namely, the IC package 1 is so moulded that a certain interval between an inner side of the flat part 4 and a top of the flat part 5 can be spaced. Therefore, these first and second external leads 2, 3 are alternately moulded, and a gap 7 of an external lead 2 or 3 with the same dimension can be twice as long as a gap 6 of the adjacent external leads 2, 3. Thus, mounting inferiority by soldering can be prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はＩＣパッケージに関し、特にその外部リードの
形状を改良したＩＣパッケージに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC package, and more particularly to an IC package in which the shape of its external leads is improved.

〔従来の技術〕[Conventional technology]

従来、かかるＩＣパッケージ、特にクアド・フラット型
ＩＣパッケージ（ＱＦＰ型ＩＣパッケージ）は四辺に形
成される外部リードが同一寸法。Conventionally, in such IC packages, especially quad flat type IC packages (QFP type IC packages), external leads formed on all four sides have the same size.

同一形状で形成されている。They are formed in the same shape.

第２図（ａ＞、（ｂ）はそれぞれ従来の一例を示すＩＣ
パッケージの平面図および断面図である。Figures 2 (a> and (b) each show an example of a conventional IC
FIG. 3 is a plan view and a cross-sectional view of the package.

第２図（ａ）、（ｂ）に示すように、従来のＩＣパッケ
ージ１は、パッケージ端面からリード平坦部９の先端ま
での長さがすべて同一の外部リート８を四辺に形成して
いる。As shown in FIGS. 2(a) and 2(b), the conventional IC package 1 has external reams 8 formed on all four sides with the same length from the package end face to the tip of the lead flat portion 9.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のＩＣパッケージは、外部リートが同一形
状であるので、隣接する外部リード間の寸法が小さくな
るにつれて、ＩＣを実装する際に用いるプリント基板上
のパッドの間隔も狭くなる。従って、ＩＣパッケージを
プリント基板上に半田付けで実装する際、隣り合う外部
リードが半田により短絡し、実装不良を生じ易いという
欠点がある。In the conventional IC package described above, the external leads have the same shape, so as the dimensions between adjacent external leads become smaller, the spacing between the pads on the printed circuit board used when mounting the IC becomes narrower. Therefore, when an IC package is mounted on a printed circuit board by soldering, adjacent external leads are easily short-circuited by the solder, resulting in poor mounting.

本発明の目的は、かかる半田付けによる実装不良を防止
するＩＣパッケージを提供することにある。An object of the present invention is to provide an IC package that prevents mounting defects caused by such soldering.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のＩＣパッケージは、外部リードを四方に突出さ
せるＩＣパッケージにおいて、パッケージ端面からリー
ド先端までの長さあるいは形状が異なる第一および第二
の外部リードを有し、前記第一および第二の外部リード
を交互に配置して構成される。The IC package of the present invention is an IC package in which external leads protrude in all directions, and has first and second external leads having different lengths or shapes from the end face of the package to the tip of the lead, and Consists of external leads arranged alternately.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を用いて説明する。 Next, embodiments of the present invention will be described using the drawings.

第１図（ａ’）、（ｂ）はそれぞれ本発明の一実施例の
ＩＣパッケージを示す平面図および断面図である。FIGS. 1(a') and 1(b) are a plan view and a sectional view, respectively, showing an IC package according to an embodiment of the present invention.

第１図（ａ）、（ｂ）に示すように、本実施例は■Ｃパ
ッケージ１の四辺から外部に延びる第一の外部リード２
および第二の外部リード３の各々の平坦部４および５の
先端部までの寸法を異ならせている。すなわち、平坦部
４の内側と平坦部５の先端部との間にある程度の間隔を
もたせるように成形する。これにより、これら第一およ
び第二の外部リード２および３を交互に成形し、同一寸
法の外部リード２あるいは３の間隔７を隣り合う外部リ
ード２および３の間隔６の２倍にすることが可能になる
９ 〔発明の効果〕 以上説明したように、本発明ＩＣパッケージは交互に隣
り合う第一および第二の外部リードのパッケージ端面か
らの長さあるいは形状を変え、パッケージ端面からの長
さが同一である第一あるいは第二の外部リードの間隔を
従来の間隔の２倍にすることにより、プリント基板上に
実装するなめに形成される配線の間隔を２倍に広げるこ
とができるので、隣り合う外部リード間の半田による短
絡を発生しにくくできるという効果がある。As shown in FIGS. 1(a) and 1(b), in this embodiment, first external leads 2 extend outward from the four sides of the C package 1.
The flat portions 4 and 5 of the second external lead 3 have different dimensions up to their tips. That is, the molding is performed so that a certain distance is provided between the inside of the flat part 4 and the tip of the flat part 5. As a result, the first and second external leads 2 and 3 can be formed alternately, and the interval 7 between the external leads 2 or 3 of the same size can be made twice the interval 6 between the adjacent external leads 2 and 3. [Effects of the Invention] As explained above, in the IC package of the present invention, the length or shape of the first and second external leads that are adjacent to each other from the package end surface is changed, and the length from the package end surface is changed. By making the spacing between the first or second external leads, which are the same, twice the conventional spacing, it is possible to double the spacing between the wiring formed on the printed circuit board. This has the effect that short circuits due to solder between adjacent external leads are less likely to occur.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）、（ｂ）はそれぞれ本発明の一実施例を示
すＩＣパッケージの平面図および断面図、第２図（ａ）
、（ｂ）はそれぞれ従来の一例番示すＩＣパッケージの
平面図および断面図である。 １・・・ＩＣパッケージ、２・・・第一の外部リード、
３・・・第二の外部リード、４，５・・・平坦部。FIGS. 1(a) and 1(b) are a plan view and a cross-sectional view of an IC package showing an embodiment of the present invention, respectively, and FIG. 2(a) is
, (b) are a plan view and a sectional view, respectively, of an example of a conventional IC package. 1...IC package, 2...first external lead,
3... Second external lead, 4, 5... Flat part.

Claims (1)

【特許請求の範囲】[Claims] 　外部リードを四方に突出させるＩＣパッケージにおい
て、パッケージ端面からリード先端までの長さあるいは
形状が異なる第一および第二の外部リードを有し、前記
第一および第二の外部リードを交互に配置したことを特
徴とするＩＣパッケージ。An IC package having external leads protruding in all directions, which has first and second external leads having different lengths or shapes from the package end face to the lead tips, and the first and second external leads are arranged alternately. An IC package characterized by:
JP2297533A 1990-11-02 1990-11-02 Ic package Pending JPH04170057A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2297533A JPH04170057A (en) 1990-11-02 1990-11-02 Ic package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2297533A JPH04170057A (en) 1990-11-02 1990-11-02 Ic package

Publications (1)

Publication Number Publication Date
JPH04170057A true JPH04170057A (en) 1992-06-17

Family

ID=17847769

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2297533A Pending JPH04170057A (en) 1990-11-02 1990-11-02 Ic package

Country Status (1)

Country Link
JP (1) JPH04170057A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980039676A (en) * 1996-11-28 1998-08-17 황인길 Easy to mount bottom lead package chip scale package
US6707135B2 (en) * 2000-11-28 2004-03-16 Texas Instruments Incorporated Semiconductor leadframe for staggered board attach
JP2015149363A (en) * 2014-02-05 2015-08-20 株式会社デンソー semiconductor module

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980039676A (en) * 1996-11-28 1998-08-17 황인길 Easy to mount bottom lead package chip scale package
US6707135B2 (en) * 2000-11-28 2004-03-16 Texas Instruments Incorporated Semiconductor leadframe for staggered board attach
US7002240B2 (en) 2000-11-28 2006-02-21 Texas Instruments Incorporated Semiconductor leadframe for staggered board attach
JP2015149363A (en) * 2014-02-05 2015-08-20 株式会社デンソー semiconductor module

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