JPH04284660A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04284660A
JPH04284660A JP4853791A JP4853791A JPH04284660A JP H04284660 A JPH04284660 A JP H04284660A JP 4853791 A JP4853791 A JP 4853791A JP 4853791 A JP4853791 A JP 4853791A JP H04284660 A JPH04284660 A JP H04284660A
Authority
JP
Japan
Prior art keywords
leads
group
lead
width
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4853791A
Other languages
Japanese (ja)
Inventor
Shuji Beppu
修治 別府
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyushu Fujitsu Electronics Ltd
Fujitsu Ltd
Original Assignee
Kyushu Fujitsu Electronics Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyushu Fujitsu Electronics Ltd, Fujitsu Ltd filed Critical Kyushu Fujitsu Electronics Ltd
Priority to JP4853791A priority Critical patent/JPH04284660A/en
Publication of JPH04284660A publication Critical patent/JPH04284660A/en
Withdrawn legal-status Critical Current

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enable the deformation and displacement due to the external force of the leads in narrowing width to be avoided by a method wherein the width of the leads on both end parts is made wider than that of the leads on the inner side out of multiple leads to be arrayed on the side of a package. CONSTITUTION:The title semiconductor device is provided with an insulating member 1 sealing a chip formed of integrated circuits as well as a multitude of conductive leads 2 having outer conductors extending from one ends electrically connected to the integrated circuits and passing through the insulating member 1 to be arrayed in parallel with one another. At this time, the outer leading part of the leads 21 of the first group at least positioned on both end parts out of the leads 2 are formed wider than the leads 22 of the second group positioned inner side of the leads 21 in the direction making a right angle with said extending direction. Furthermore, for example, the outer leading parts of the leads 21 of the first group are made narrower than the ends of the leads 22 of the second group.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は,集積回路チップを外部
回路と接続するためのリードを有するパッケージに封入
された半導体装置に係り,とくに,該半導体装置の取扱
時における該リードの変形防止に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device enclosed in a package having leads for connecting an integrated circuit chip to an external circuit, and in particular to prevention of deformation of the leads during handling of the semiconductor device. .

【0002】0002

【従来の技術】樹脂モールド型のパッケージあるいは一
部のセラミックパッケージを用いて封止される集積回路
チップは,パッケージに埋め込まれたリードにより外部
接続される。図7は樹脂モールドパッケージの一例を示
し, トランスファモールド法等によって成形された樹
脂層1内部には, 図示しない集積回路チップが封入さ
れており, この集積回路チップに対する外部接続手段
として複数のリード2が設けられている。通常,このよ
うな外部接続用リード2は,樹脂層1の二側面あるいは
四側面の各々に外部に一列に配列される。
2. Description of the Related Art An integrated circuit chip sealed using a resin molded package or some ceramic packages is connected to the outside through leads embedded in the package. FIG. 7 shows an example of a resin mold package, in which an integrated circuit chip (not shown) is sealed inside a resin layer 1 molded by a transfer molding method, etc., and a plurality of leads 2 are used as external connection means for this integrated circuit chip. is provided. Usually, such external connection leads 2 are arranged in a line on each of two or four sides of the resin layer 1.

【0003】0003

【発明が解決しようとする課題】一方,パッケージの小
型化および集積回路の高機能化にともなって,リード2
の幅および配列ピッチを縮小する必要が生じている。そ
の結果, パッケージの試験, 輸送, あるいはプリ
ント配線基板等への搭載時等に, リード2が外力によ
って変形したりあるいは配列ピッチにずれが生じやすく
なる。このような変形や位置ずれにより, プリント配
線パターニンとの半田付けが完全に行われず, 接続不
良が生じることになる。とくに, プリント配線基板へ
の搭載および半田付けを行う実装工程が自動化にともな
って, 上記外部接続用リードの僅かな変形等による影
響を受けやすくなっている。
[Problems to be Solved by the Invention] On the other hand, as packages become smaller and integrated circuits become more sophisticated, lead
There is a need to reduce the width and arrangement pitch of the As a result, when the package is tested, transported, or mounted on a printed wiring board, etc., the leads 2 are likely to be deformed by external force or the arrangement pitch may be misaligned. Due to such deformation and misalignment, soldering to the printed wiring pattern cannot be completed completely, resulting in poor connections. In particular, as the mounting process of mounting onto a printed wiring board and soldering has become automated, it has become more susceptible to the effects of slight deformation of the external connection leads mentioned above.

【0004】本発明は, 上記のような外力によるリー
ドの変形や変位を防止する方法を提供することを目的と
する。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for preventing lead deformation and displacement caused by external forces as described above.

【0005】[0005]

【課題を解決するための手段】上記目的は, 集積回路
が形成されたチップを封入する絶縁部材と,該集積回路
に電気的に接続された一端から延在し且つ該絶縁部材を
貫通して互いに平行に配列された外部導出部を有する複
数の導電性のリードとを備え,該リードのうちの少なく
とも両側端部に位置する第1群のリードについては,そ
の内側部に位置する第2群のリードに比べて該外部導出
部が前記延在方向に直角な方向における幅が広く形成さ
れていることを特徴とする本発明に係る半導体装置,ま
たは,上記において,前記第1群のリードの前記外部導
出部における先端が前記第2群のリードの先端よりも幅
が狭くされていることを特徴とする本発明に係る半導体
装置,または,上記において,前記第1群のリードにお
ける前記幅が広くされた先端部に前記延在方向に平行な
方向に延在するスリットが設けられていることを特徴と
する本発明に係る半導体装置のいずれかによって達成さ
れる。
[Means for Solving the Problem] The above object is to provide an insulating member that encapsulates a chip on which an integrated circuit is formed, and an insulating member that extends from one end electrically connected to the integrated circuit and that extends through the insulating member. and a plurality of conductive leads having external lead-out portions arranged in parallel with each other, and for the first group of leads located at least at both end portions of the leads, a second group of leads located at the inner side thereof. The semiconductor device according to the present invention is characterized in that the external lead-out portion is formed to have a wider width in the direction perpendicular to the extending direction than the leads of the first group. The semiconductor device according to the present invention, wherein the width of the tip of the external lead-out portion is narrower than the tip of the second group of leads, or in the above, the width of the first group of leads is This is achieved by any one of the semiconductor devices according to the present invention, characterized in that the widened tip portion is provided with a slit extending in a direction parallel to the extending direction.

【0006】[0006]

【作用】本発明らの調査によれば, パッケージの各側
面に配列された外部接続用リード2のうち, 外側端に
近いリードほど前記変形等を受けやすく, 図8に示す
ように, 両側端部のリード21が極端に変形しやすく
, 一方, 内側部に位置するリード22の変形等はま
れであることが分かった。
[Operation] According to the research conducted by the present inventors, among the external connection leads 2 arranged on each side of the package, the leads closer to the outer edge are more susceptible to the above-mentioned deformation, and as shown in FIG. It was found that the lead 21 located at the inner part was extremely prone to deformation, while deformation of the lead 22 located at the inner part was rare.

【0007】この結果にもとづき, 図1の構造原理図
に示すように, 両側端部のリード21については, 
リード2の配列方向における幅を拡張することを試みた
ところ, リード2全体の接続不良が低減可能となった
。両側端部のリード21のみを主として拡幅するのであ
るから, リード2の配列ピッチを変更する必要はなく
, 各側面におけるリード2全体の配列幅もほとんど増
加しない。
Based on this result, as shown in the structural principle diagram of FIG. 1, for the leads 21 at both ends,
When we attempted to expand the width of the leads 2 in the arrangement direction, we were able to reduce the number of connection failures across the leads 2. Since only the leads 21 at both end portions are mainly widened, there is no need to change the arrangement pitch of the leads 2, and the overall arrangement width of the leads 2 on each side surface hardly increases.

【0008】[0008]

【実施例】第1の実施例として, 図1における両側端
部のリード21の幅を, 内側部に位置するリード22
の幅に対して, 例えば1.5 〜2倍にする。これに
より前記変形等の防止に対して効果が得られた。ちなみ
に, リード22の幅は従来と同一で450 μmであ
り, これに対して, リード21の幅は 600〜9
00 μm である。リード21およびリード22の長
さは共に1300μm 程度であり, 厚さは共に15
0 μm である。
[Example] As a first example, the width of the leads 21 at both ends in FIG.
For example, increase the width by 1.5 to 2 times. This was effective in preventing the deformation and the like. By the way, the width of the lead 22 is 450 μm, which is the same as the conventional one, whereas the width of the lead 21 is 600 to 9 μm.
00 μm. The length of both lead 21 and lead 22 is about 1300 μm, and the thickness of both is about 15 μm.
It is 0 μm.

【0009】図2は本発明をセラミックパッケージに適
用した第2の実施例説明図であって,低融点ガラス層3
によって接着された二枚のセラミック板4の間には,図
示しない集積回路チップが封入されている。低融点ガラ
ス層3を貫通するようにして配列された外部接続用リー
ド5のうち,両側端部のリード51の幅が,内側部に位
置するリード52のそれよりも拡張されている。低融点
ガラス層3とセラミック板4とから成る図示のセラミッ
クパッケージにおけるリード5は,図1におけるリード
2とは異なって折り曲げられていないが, その変形等
の防止に対する効果は, 図1と同じである。
FIG. 2 is a diagram illustrating a second embodiment in which the present invention is applied to a ceramic package, in which a low melting point glass layer 3
An integrated circuit chip (not shown) is enclosed between the two ceramic plates 4 bonded together. Among the external connection leads 5 arranged to penetrate the low melting point glass layer 3, the widths of the leads 51 at both ends are wider than those of the leads 52 located on the inner side. The leads 5 in the illustrated ceramic package consisting of the low melting point glass layer 3 and the ceramic plate 4 are not bent unlike the leads 2 in FIG. 1, but the effect of preventing deformation etc. is the same as in FIG. be.

【0010】図3は本発明の第3の実施例説明図であっ
て, 図1と同様のパッケージにおける拡幅された両側
端部のリード21の先端部が, 内側部に位置するリー
ド22の幅とほぼ等しくなるように, 選択的に狭小に
されている。換言すれば, リード21の先端部を除い
た部分の幅を拡張するのである。拡幅部分および狭小部
分のそれぞれの幅は前記実施例と同様である。とくに,
 前記狭小化のための切り欠きを,両リード21の外側
に設けることが望ましい。これにより, リード21お
よびリード22全体の配列ピッチが均等になり,プリン
ト配線パターニンに変更を加える必要がない。すなわち
,本発明の半導体装置に, 従来の半導体装置と互換性
を持たせることができる。この利点は, 図2に示すよ
うなセラミックパッケージにおける両側端部のリード5
1に対しても有効である。
FIG. 3 is an explanatory diagram of a third embodiment of the present invention, in which the tips of the leads 21 at the widened both ends of a package similar to that shown in FIG. is selectively narrowed so that it is approximately equal to . In other words, the width of the lead 21 excluding the tip is expanded. The widths of the widened portion and the narrowed portion are the same as in the previous embodiment. especially,
It is preferable that the notch for narrowing is provided on the outside of both leads 21. This makes the overall arrangement pitch of the leads 21 and 22 uniform, and there is no need to make any changes to the printed wiring pattern. That is, the semiconductor device of the present invention can be made compatible with conventional semiconductor devices. This advantage is due to the fact that the leads on both ends of a ceramic package as shown in Figure 2
It is also valid for 1.

【0011】図4は本発明の第4の実施例説明図であっ
て, パッケージの四つの側面に図1と同様の外部接続
用リード2が設けられている構造を示す。このようなパ
ッケージに対しても, 両側端部のリード21の幅を拡
張しておくことにより, 変形等の防止に対して有効が
あり, また, その先端を, 図3に示した実施例と
同様に, 内側部に位置するリード22の幅と等しくな
るように狭小にしておくことにより, 従来の半導体装
置と互換性を持たせることができる。
FIG. 4 is an explanatory diagram of a fourth embodiment of the present invention, showing a structure in which external connection leads 2 similar to those in FIG. 1 are provided on four sides of the package. Even for such a package, expanding the width of the leads 21 at both ends is effective in preventing deformation, etc., and the tips of the leads 21 can be made similar to the embodiment shown in Fig. 3. Similarly, by making the width of the lead 22 narrow to be equal to the width of the lead 22 located inside, compatibility with conventional semiconductor devices can be achieved.

【0012】図5は本発明の第5の実施例説明図であっ
て, いわゆるZIP 型のパッケージに本発明を適用
した場合を示す。すなわち,ZIP型パッケージにおい
ては, 例えば樹脂層1の一側面に配列された複数の外
部接続用リード6が, 交互に上下反対に折り曲げられ
ている。このようなリード6のうち, 両側端部のリー
ド61の幅を拡張することにより, 変形が防止される
。また, リード61の先端を, 内側部に位置するリ
ード62のそれと等しくしておくことにより,従来のZ
IP 型パッケージのリードと同様に, プリント配線
基板のスルーホールに嵌挿することができる。
FIG. 5 is a diagram illustrating a fifth embodiment of the present invention, and shows a case where the present invention is applied to a so-called ZIP type package. That is, in the ZIP type package, for example, a plurality of external connection leads 6 arranged on one side of the resin layer 1 are alternately bent upside down. Among such leads 6, deformation can be prevented by expanding the width of the leads 61 at both ends. In addition, by making the tip of the lead 61 equal to that of the lead 62 located inside, the conventional Z
Like the leads of an IP type package, it can be inserted into a through hole on a printed wiring board.

【0013】図6は本発明の第6の実施例説明図であっ
て, 拡幅された両側端部のリードにスリットを設けた
構造を示す。同図(a) は, パッケージの一側面に
一直線上に配列された複数のリード2のうち, 拡幅さ
れた両側端部のリード21に, リード2の配列方向に
交差する方向に延在するスリット7が設けられている。 同図(b) は,上記スリット7が, その延在方向に
沿って二分割された場合である。同図(c)は,   
図3に示した実施例における, 先端部が狭小にされた
リード21の拡幅部分にスリット7を設けた場合である
FIG. 6 is an explanatory diagram of a sixth embodiment of the present invention, showing a structure in which slits are provided in the leads at both ends of the lead which are widened. In the same figure (a), among a plurality of leads 2 arranged in a straight line on one side of the package, slits are formed in the leads 21 at the widened ends of both sides, extending in a direction intersecting the direction in which the leads 2 are arranged. 7 is provided. Figure (b) shows the case where the slit 7 is divided into two along its extending direction. The same figure (c) is
This is a case where the slit 7 is provided in the widened part of the lead 21 whose tip end is narrowed in the embodiment shown in FIG.

【0014】一般に, 図1等に示すような湾曲した形
状にするために, 外部接続用リード2をプレス加工に
よって成形する。拡幅された両側端部のリード21は,
 内側部に位置するリード22よりも降服応力が大きい
。したがって, 湾曲成形後に, これらのリード21
および22が一直線上に配列するように成形するために
は, リード21をより大きな角度だけ折り曲げる必要
があるが, このような加工方法は実際上困難である。 上記実施例のように, 拡幅されたリード21にスリッ
ト7を設けることにより, 内側部に位置するリード2
2とほぼ同じ降服応力を有するようになり, これらリ
ード21および22を一直線上に配列させることが容易
になる。すなわち,拡幅された両側端部のリードを含む
複数のリードを, 従来のプレス工程に変更を加えるこ
となしに湾曲成形可能となる。なお, 上記スリット7
の幅は,厚さ150 μm のリード21を, リード
22の2倍に拡幅するとして,例えば約 150μm 
程度である。
Generally, the external connection lead 2 is formed by press working to form a curved shape as shown in FIG. 1 and the like. The widened leads 21 at both ends are as follows:
The yield stress is greater than that of the lead 22 located on the inner side. Therefore, after curve forming, these leads 21
In order to form the leads 21 so that they are aligned in a straight line, it is necessary to bend the leads 21 by a larger angle, but such a processing method is difficult in practice. As in the above embodiment, by providing the slit 7 in the widened lead 21, the lead 2 located on the inner side
2, and it becomes easy to arrange these leads 21 and 22 in a straight line. In other words, multiple leads, including the widened leads at both ends, can be curved without making any changes to the conventional pressing process. In addition, the above slit 7
For example, the width of the lead 21 is approximately 150 μm, assuming that the lead 21 with a thickness of 150 μm is expanded to twice the width of the lead 22.
That's about it.

【0015】[0015]

【発明の効果】本発明によれば,半導体集積回路を封入
する小型のパッケージまたは高密度集積回路を封入する
パッケージにおける外部接続用のリードが外力によって
変形し, プリント配線との位置ずれを生じることに起
因する接続不良を低減可能とする効果がある。
[Effects of the Invention] According to the present invention, the leads for external connection in a small package enclosing a semiconductor integrated circuit or a package enclosing a high-density integrated circuit are deformed by external force and misaligned with the printed wiring. This has the effect of reducing connection failures caused by.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】  本発明の構造原理図[Figure 1] Structural principle diagram of the present invention

【図2】  本発明の第2実施例説明図[Figure 2] Explanatory diagram of the second embodiment of the present invention

【図3】  本
発明の第3実施例説明図
[Figure 3] Explanatory diagram of the third embodiment of the present invention

【図4】  本発明の第4実施
例説明図
[Fig. 4] Explanatory diagram of the fourth embodiment of the present invention

【図5】  本発明の第5実施例説明図[Fig. 5] Explanatory diagram of the fifth embodiment of the present invention

【図6
】  本発明の第6実施例説明図
[Figure 6
] Explanatory diagram of the sixth embodiment of the present invention

【図7】  樹脂モー
ルド型パッケージの一例を示す斜視図
[Figure 7] A perspective view showing an example of a resin molded package.

【図8】  従来の問題点調査結果説明図[Figure 8] Illustration of conventional problem investigation results

【符号の説明】[Explanation of symbols]

1  樹脂層 2, 5  外部接続用リード 21, 51, 61  両側端部のリード22, 5
2, 62, 内側部に位置するリード3  低融点ガ
ラス層 4  セラミック板 7  スリット
1 Resin layer 2, 5 External connection leads 21, 51, 61 Leads on both ends 22, 5
2, 62, Lead located inside 3 Low melting point glass layer 4 Ceramic plate 7 Slit

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】  集積回路が形成されたチップを封入す
る絶縁部材と,該集積回路に電気的に接続された一端か
ら延在し且つ該絶縁部材を貫通して互いに平行に配列さ
れた外部導出部を有する複数の導電性のリードとを備え
,該リードのうちの少なくとも両側端部に位置する第1
群のリードについては,その内側部に位置する第2群の
リードに比べて該外部導出部が前記延在方向に直角な方
向における幅が広く形成されていることを特徴とする半
導体装置。
Claim 1: An insulating member enclosing a chip on which an integrated circuit is formed, and external leads extending from one end electrically connected to the integrated circuit and extending through the insulating member and arranged in parallel to each other. a plurality of electrically conductive leads having a plurality of electrically conductive leads;
A semiconductor device characterized in that, regarding the leads of the group, the external lead-out portion is formed to have a wider width in a direction perpendicular to the extending direction than the leads of the second group located inside the group.
【請求項2】  前記第1群のリードの前記外部導出部
における先端が前記第2群のリードの先端よりも幅が狭
くされていることを特徴とする請求項1記載の半導体装
置。
2. The semiconductor device according to claim 1, wherein tips of the first group of leads at the external lead-out portions are narrower than tips of the second group of leads.
【請求項3】  前記第1群のリードにおける前記幅が
広くされた先端部に前記延在方向に平行な方向に延在す
るスリットが設けられていることを特徴とする請求項1
または2記載の半導体装置。
3. A slit extending in a direction parallel to the extending direction is provided in the widened end portion of the first group of leads.
Or the semiconductor device according to 2.
JP4853791A 1991-03-14 1991-03-14 Semiconductor device Withdrawn JPH04284660A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4853791A JPH04284660A (en) 1991-03-14 1991-03-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4853791A JPH04284660A (en) 1991-03-14 1991-03-14 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04284660A true JPH04284660A (en) 1992-10-09

Family

ID=12806116

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4853791A Withdrawn JPH04284660A (en) 1991-03-14 1991-03-14 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04284660A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06260582A (en) * 1993-03-09 1994-09-16 Hitachi Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06260582A (en) * 1993-03-09 1994-09-16 Hitachi Ltd Semiconductor device

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