JPH04368160A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPH04368160A JPH04368160A JP3144713A JP14471391A JPH04368160A JP H04368160 A JPH04368160 A JP H04368160A JP 3144713 A JP3144713 A JP 3144713A JP 14471391 A JP14471391 A JP 14471391A JP H04368160 A JPH04368160 A JP H04368160A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor package
- mounting
- outer lead
- outer leads
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 229910000679 solder Inorganic materials 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 7
- 230000000694 effects Effects 0.000 description 3
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】この発明は半導体パッケージに関
し、特にそのアウターリードの実装接面に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly to a mounting surface of an outer lead thereof.
【0002】0002
【従来の技術】図4,図5はこの種の従来の半導体パッ
ケージを示し、図4はその平面図を図5は側面図、図6
は該半導体パッケージを実装する基板のマウントパッド
を示す平面図である。図において、1は図示していない
が例えばダイパッド上に半導体素子チップを接合し半導
体素子チップに設けられた複数のボンディングパッドと
ダイパッド周辺に配置された内部リードを金属細線で接
続し樹脂封止して形成されたこの種の半導体パッケージ
、2は内部リードの延長で半導体パッケージ1の外周に
均一長さで突出し微少間隔で配置された外部接続用のア
ウターリードで2aはその接合面である。3は半導体パ
ッケージ1のアウターリード2の接合面2aが接合され
る実装基板のマウントパッドである。2. Description of the Related Art FIGS. 4 and 5 show this type of conventional semiconductor package, in which FIG. 4 is a plan view, FIG. 5 is a side view, and FIG.
FIG. 2 is a plan view showing a mounting pad of a substrate on which the semiconductor package is mounted. In the figure, 1 is not shown, but for example, a semiconductor element chip is bonded onto a die pad, and a plurality of bonding pads provided on the semiconductor element chip and internal leads arranged around the die pad are connected with thin metal wires and sealed with resin. In this type of semiconductor package, 2 is an extension of the inner leads, and outer leads 2 for external connection protrude at uniform lengths from the outer periphery of the semiconductor package 1 and are arranged at minute intervals, and 2a is the bonding surface thereof. Reference numeral 3 denotes a mounting pad of the mounting board to which the bonding surface 2a of the outer lead 2 of the semiconductor package 1 is bonded.
【0003】次に動作について説明する。上述のように
構成された半導体パッケージ1はアウターリード2の接
合面2aを実装基板のマウントパッド3上に位置させハ
ンダを介して実装される。Next, the operation will be explained. The semiconductor package 1 configured as described above is mounted with the bonding surface 2a of the outer lead 2 positioned on the mounting pad 3 of the mounting board through solder.
【0004】0004
【発明が解決しようとする課題】従来の半導体パッケー
ジは以上のように構成され実装されるので、アウターリ
ードピッチが微細化されると実装時において隣接する接
合面が接近して半田ブリッジ不具合即ち、隣接間がハン
ダの流出等により接触状態になることがある。このため
半導体パッケージの多ピン、小型化の阻害要因の一つと
なっていた。[Problems to be Solved by the Invention] Since conventional semiconductor packages are constructed and mounted as described above, as the outer lead pitch becomes finer, adjacent bonding surfaces become closer together during mounting, resulting in solder bridging problems, that is, Adjacent parts may come into contact due to solder leakage, etc. This has been one of the obstacles to increasing the number of pins and reducing the size of semiconductor packages.
【0005】この発明は上記の様な問題点を解消するた
めになされたもので、実装時の半田ブリッジ不具合を発
生させることなく、多ピン、小型化の半導体パッケージ
を得ることを目的とする。The present invention was made to solve the above-mentioned problems, and its object is to obtain a semiconductor package with a large number of pins and a reduced size without causing solder bridging defects during mounting.
【0006】[0006]
【課題を解決するための手段】この発明に係る半導体パ
ッケージは、マウントパッドに接合されるアウターリー
ドの接合面が隣接間でそれぞれ千鳥状になるように長短
形状のアウターリードを交互に配するものである。[Means for Solving the Problems] A semiconductor package according to the present invention has long and short outer leads arranged alternately so that the bonding surfaces of the outer leads bonded to the mounting pads are staggered between adjacent ones. It is.
【0007】[0007]
【作用】この発明の半導体パッケージにおけるアウター
リードは千鳥状に位置させた実装基板との接合面の隣間
隔が確保され半田ブリッジの不具合を防止する。[Function] The outer leads in the semiconductor package of the present invention are arranged in a staggered manner so that a distance between adjacent surfaces of the outer leads and the bonding surfaces with the mounting substrate is ensured, thereby preventing problems caused by solder bridging.
【0008】[0008]
実施例1.以下、この発明の実施例1を図について説明
する。図1,図2はこの発明の実施例1における半導体
パッケージを示し、図1はその平面図を図2は側面図、
図3は該半導体パッケージを実装する基板のマウントパ
ッドを示す平面図である。図において、1は従来例と同
様であるのでその説明は省略する。4は接合面4aを有
し内部リードの延長で半導体パッケージ1の外周より突
出して配置された外部接続用の短形状アウターリード、
5は接合面5aを有し短形状アウターリード4と交互に
内部リードの延長で半導体パッケージ1の外周より突出
して配置された外部接続用の長形状アウターリードで、
接合面4aおよび5aはそれぞれ内および外に位置した
千鳥状形をなしている。6および7は短形状アウターリ
ード4の接合面4aおよび長形状アウターリード5の接
合面5aがそれぞれ接合される実装基板のマウントパッ
ドである。Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. 1 and 2 show a semiconductor package in Embodiment 1 of the present invention, FIG. 1 is a plan view thereof, FIG. 2 is a side view thereof,
FIG. 3 is a plan view showing a mounting pad of a substrate on which the semiconductor package is mounted. In the figure, 1 is the same as the conventional example, so its explanation will be omitted. 4 is a short outer lead for external connection that has a bonding surface 4a and is arranged to protrude from the outer periphery of the semiconductor package 1 as an extension of the inner lead;
Reference numeral 5 denotes a long outer lead for external connection, which has a bonding surface 5a and is arranged to protrude from the outer periphery of the semiconductor package 1 as an extension of the inner lead, alternately with the short outer lead 4;
The joint surfaces 4a and 5a have a staggered shape with inner and outer positions, respectively. Reference numerals 6 and 7 designate mounting pads of the mounting board to which the bonding surface 4a of the short outer lead 4 and the bonding surface 5a of the elongated outer lead 5 are bonded, respectively.
【0009】次に動作について説明する。上述のように
短、長形状アウターリード4,5を有して形成された半
導体パッケージ1は実装基板のマウントパッド6,7上
に実装される際その接合面が隣接間で互いに千鳥状に位
置し充分な隣間隔が確保できる。なお、短、長形状アウ
ターリードはトランスファーモールド装置(図示せず)
で樹脂封止した後、隣接するアウターリード長さを交互
に短、長となる様にリード加工装置(図示せず)により
、半導体装置用リードフレーム(図示せず)から切り離
すことにより形成され個々の半導体パッケージを完成さ
せている。Next, the operation will be explained. When the semiconductor package 1 formed with the short and long outer leads 4 and 5 as described above is mounted on the mounting pads 6 and 7 of the mounting board, the bonding surfaces thereof are positioned in a staggered manner between adjacent ones. This will ensure sufficient distance between the two. In addition, the short and long outer leads are made using a transfer molding device (not shown).
After sealing with resin, adjacent outer leads are cut from a semiconductor device lead frame (not shown) using a lead processing device (not shown) so that the lengths of the adjacent outer leads are alternately short and long. has completed semiconductor packages.
【0010】実施例2.なお、上記実施例1では四方向
でアウターリード出し(クワッドフラッドパッケージ)
の半導体パッケージについて説明したが二方向でアウタ
ーリード出し等の表面実装形(スモールアウトラインパ
ッケージ)の半導体パッケージであってもよく、上記実
施例1と同様の効果を奏する。Example 2. In addition, in the above example 1, outer leads are drawn out in four directions (quad flood package).
Although the semiconductor package described above has been described, it may be a surface mount type (small outline package) semiconductor package with outer leads extending in two directions, etc., and the same effects as in the first embodiment can be obtained.
【0011】[0011]
【発明の効果】以上の様に、この発明によれば半導体パ
ッケージのマウントパッドに接合されるアウターリード
の接合面が隣接間でそれぞれ千鳥状になるように長短形
状のアウターリードを交互に配する構成としたので、実
装基板への実装時に接面の隣間隔が確保され半田ブリッ
ジ不具合が防止でき、よって多ピン、小型化の半導体パ
ッケージが得られる効果がある。[Effects of the Invention] As described above, according to the present invention, long and short outer leads are arranged alternately so that the bonding surfaces of the outer leads bonded to the mounting pads of the semiconductor package are staggered between adjacent ones. With this configuration, when mounting on a mounting board, the adjacent spacing between the contact surfaces can be ensured, and solder bridging problems can be prevented, resulting in the effect that a multi-pin, miniaturized semiconductor package can be obtained.
【図1】この発明の実施例1における半導体パッケージ
を示す平面図である。FIG. 1 is a plan view showing a semiconductor package in Example 1 of the present invention.
【図2】この発明の実施例1を示す側面図である。FIG. 2 is a side view showing Embodiment 1 of the present invention.
【図3】実施例1の半導体パッケージが実装される基板
のマウントパッドを示す平面図である。FIG. 3 is a plan view showing a mounting pad of a substrate on which the semiconductor package of Example 1 is mounted.
【図4】従来の半導体パッケージを示す平面図である。FIG. 4 is a plan view showing a conventional semiconductor package.
【図5】従来の半導体パッケージを示す側面図である。FIG. 5 is a side view showing a conventional semiconductor package.
【図6】従来の半導体パッケージが実装される基板のマ
ウントパッドを示す平面図である。FIG. 6 is a plan view showing a mounting pad of a substrate on which a conventional semiconductor package is mounted.
1 半導体パッケージ 4 短形状アウターリード 5 長形状アウターリード 6 実装基板のマウントパッド 7 実装基板のマウントパッド 1 Semiconductor package 4 Short outer lead 5 Long outer lead 6 Mounting pad of mounting board 7 Mounting pad of mounting board
Claims (1)
配置され実装基板のマウントパッド上に実装される半導
体パッケージにおいて、上記マウントパッドに接合され
る上記アウターリードの接合面が隣接間でそれぞれ千鳥
状になるように短、長形状のアウターリードを交互に配
したことを特徴とする半導体パッケージ。1. In a semiconductor package in which outer leads are arranged around the periphery at a fine pitch and mounted on a mounting pad of a mounting board, bonding surfaces of the outer leads that are bonded to the mount pads are staggered between adjacent ones. A semiconductor package characterized by alternately arranging short and long outer leads so that
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3144713A JPH04368160A (en) | 1991-06-17 | 1991-06-17 | Semiconductor package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3144713A JPH04368160A (en) | 1991-06-17 | 1991-06-17 | Semiconductor package |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04368160A true JPH04368160A (en) | 1992-12-21 |
Family
ID=15368565
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3144713A Pending JPH04368160A (en) | 1991-06-17 | 1991-06-17 | Semiconductor package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04368160A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100294912B1 (en) * | 1998-09-10 | 2001-07-12 | 이중구 | UFPL package and method for manufacturing the same |
-
1991
- 1991-06-17 JP JP3144713A patent/JPH04368160A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100294912B1 (en) * | 1998-09-10 | 2001-07-12 | 이중구 | UFPL package and method for manufacturing the same |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4917112B2 (en) | Semiconductor device | |
JPS63128736A (en) | Semiconductor element | |
JPH1084057A (en) | Bga semiconductor package with metal carrier frame and manufacture thereof | |
JP3837215B2 (en) | Individual semiconductor device and manufacturing method thereof | |
JPH06295939A (en) | Semiconductor device | |
JPH09321212A (en) | Semiconductor device and its manufacture | |
JP3633364B2 (en) | Manufacturing method of BGA type semiconductor device | |
JPH04368160A (en) | Semiconductor package | |
JPH02133942A (en) | Ceramic-chip carrier type semiconductor device | |
JP2885786B1 (en) | Semiconductor device manufacturing method and semiconductor device | |
JPH03163858A (en) | Resin-sealed semiconductor device | |
JP2001077279A (en) | Lead frame and manufacture of resin-sealed semiconductor device using the same | |
JP2001077275A (en) | Lead frame and manufacture of resin-sealed semiconductor device using the same | |
JPH0526761Y2 (en) | ||
JP2003297996A (en) | Lead frame and resin-sealing semiconductor device using the same | |
JPS63141329A (en) | Ic package | |
JPS63248155A (en) | Semiconductor device | |
JPH0366150A (en) | Semiconductor integrated circuit device | |
KR100370480B1 (en) | Lead frame for semiconductor package | |
KR100222294B1 (en) | Semiconductor package | |
KR950007011Y1 (en) | Plastic packaging type | |
JP2004200719A (en) | Semiconductor device | |
JPH01173747A (en) | Resin-sealed semiconductor device | |
JPH0645514A (en) | Hybrid integrated circuit | |
JP2003007953A (en) | Resin-sealing semiconductor device and manufacturing method therefor |