JPH05114671A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05114671A JPH05114671A JP3304129A JP30412991A JPH05114671A JP H05114671 A JPH05114671 A JP H05114671A JP 3304129 A JP3304129 A JP 3304129A JP 30412991 A JP30412991 A JP 30412991A JP H05114671 A JPH05114671 A JP H05114671A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- leads
- package
- semiconductor device
- led out
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子を一体封止
したパッケージから外部回路と接続するためのアウター
リードを多数導出させた半導体装置に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a large number of outer leads for connecting to an external circuit are led out from a package in which semiconductor elements are integrally sealed.
【０００２】[0002]
【従来の技術】半導体素子を一体封止しているパッケー
ジの外周には、半導体素子に接続されたリードがアウタ
ーリードとして複数導出されている。このリードの本数
は半導体素子の高集積化に伴い増加する傾向にあるた
め、パッケージの外周から高密度にアウターリードを導
出させる必要がある。従来、パッケージの外周からアウ
ターリードを導出させた半導体装置として図４の斜視図
に基づいて説明する。すなわち、この半導体装置１は半
導体素子１１とリード１５とをボンディングワイヤー
（図示せず）等により電気的に接続し、モールド樹脂等
のパッケージ１０にて一体封止したものである。この半
導体装置１はパッケージ１０の４か所の外周端面全部か
らリード１５がアウターリード１５ａとして複数導出さ
れる、いわゆるＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋ
ａｇｅ）構造のものである。このＱＦＰ構造の半導体装
置１は例えば０．３５ｍｍ幅のリード１５が０．８ｍｍ
ピッチで合計１２０本導出されており、このリード１５
のアウターリード１５ａとプリント配線板（図示せず）
とをハンダ付けして実装している。2. Description of the Related Art A plurality of leads connected to a semiconductor element are led out as outer leads on the outer periphery of a package in which a semiconductor element is integrally sealed. Since the number of leads tends to increase with the high integration of semiconductor elements, it is necessary to lead the outer leads at high density from the outer periphery of the package. Conventionally, a semiconductor device in which outer leads are led out from the outer periphery of a package will be described with reference to the perspective view of FIG. That is, in the semiconductor device 1, the semiconductor element 11 and the lead 15 are electrically connected by a bonding wire (not shown) or the like, and are integrally sealed with a package 10 such as a mold resin. In this semiconductor device 1, a plurality of leads 15 are led out as outer leads 15a from all four outer peripheral end surfaces of the package 10, so-called QFP (Quad Flat Pack).
age) structure. In the semiconductor device 1 having this QFP structure, for example, the lead 15 having a width of 0.35 mm is 0.8 mm.
A total of 120 pitches have been derived on the pitch, and this lead 15
Outer lead 15a and printed wiring board (not shown)
And are mounted by soldering.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記説
明した半導体装置には以下に示す問題がある。すなわ
ち、半導体素子の高集積化に対応して半導体装置のアウ
ターリードの本数を増加させるには、半導体装置のパッ
ケージを大型化するか、あるいはアウターリードの幅お
よびピッチを狭くすることが考えられる。しかし、この
ようにパッケージを大型化すると、この半導体装置を実
装するプリント配線板、さらにはこのプリント配線板を
使用する電子機器等の容積が大きくなってしまう。ま
た、アウターリードの幅およびピッチを狭くした半導体
装置をプリント配線板等にハンダ付けする場合、ハンダ
付け作業が行いにくいと同時に、隣合うアウターリード
とアウターリードが電気的にショートする危険性があ
る。よって本発明は、パッケージを大きくすることな
く、かつアウターリードの幅およびピッチを狭くするこ
となくアウターリードの本数を増加できる半導体装置を
提供することを目的とする。However, the above-described semiconductor device has the following problems. That is, in order to increase the number of outer leads of a semiconductor device in response to higher integration of semiconductor elements, it is conceivable to increase the size of the package of the semiconductor device or reduce the width and pitch of the outer leads. However, if the package is increased in size in this way, the volume of the printed wiring board on which the semiconductor device is mounted, and the electronic equipment or the like using the printed wiring board becomes large. Also, when soldering a semiconductor device with a narrow outer lead width and pitch to a printed wiring board, etc., it is difficult to perform the soldering work, and at the same time, there is a risk that the adjacent outer lead and the outer lead are electrically short-circuited. .. Therefore, an object of the present invention is to provide a semiconductor device capable of increasing the number of outer leads without increasing the size of the package and reducing the width and pitch of the outer leads.
【０００４】[0004]
【課題を解決するための手段】本発明は上記の課題を解
決するために成された半導体装置である。すなわち、リ
ードに配線された半導体素子を一体封止するパッケージ
と、このパッケージからリードが導出して成るアウター
リードとから構成される半導体装置において、このリー
ドは内側アウターリードと外側アウターリードとを交互
に並設したもので、この内側アウターリードをパッケー
ジ内に穿設した開口部の内側側面から導出させるととも
に、外側アウターリードをパッケージの外周端面から導
出させたものである。The present invention is a semiconductor device made to solve the above problems. That is, in a semiconductor device including a package for integrally encapsulating a semiconductor element wired in a lead and an outer lead formed by leading the lead out of the package, the lead alternates an inner outer lead and an outer outer lead. The inner outer leads are led out from the inner side surface of the opening formed in the package, and the outer outer leads are led out from the outer peripheral end surface of the package.
【０００５】[0005]
【作用】半導体素子を封止するパッケージの外周端面か
ら導出させた外側アウターリードにより、通常の本数の
アウターリードを設けることができる。さらに、外側ア
ウターリードと内側アウターリードとを交互に並設し、
かつ内側アウターリードをパッケージ内に穿設された開
口部の内側側面から導出させることで、パッケージの大
きさを変えることなく、かつ外側アウターリードのリー
ド幅およびピッチと同様のアウターリードを増加するこ
とができる。A normal number of outer leads can be provided by the outer outer leads led out from the outer peripheral end face of the package for sealing the semiconductor element. Furthermore, the outer outer leads and the inner outer leads are alternately arranged side by side,
In addition, the inner outer lead is led out from the inner side surface of the opening formed in the package to increase the outer lead having the same lead width and pitch as the outer outer lead without changing the size of the package. You can
【０００６】[0006]
【実施例】本発明の半導体装置の実施例を図に基づいて
説明する。図１は本発明の半導体装置を説明する斜視
図、図２（ａ）は本発明の半導体装置の平面図、図２
（ｂ）は（ａ）のＡ−Ａ線矢視断面図である。すなわ
ち、図１に示すように本発明の半導体装置１は、外側リ
ード１３および内側リード１４に配線された半導体素子
１１がモールド樹脂等のパッケージ１０により一体封止
されており、このパッケージ１０の４つの外周端面から
複数の外側アウターリード１３ａがそれぞれ導出され
る、いわゆるＱＦＰ構造のものである。このパッケージ
１０内には、例えば細長状の開口部１２が各パッケージ
１０外周端面と略平行に穿設されており、開口部１２の
内側側面から複数の内側アウターリード１４ａが導出さ
れている。この内側アウターリード１４ａにより半導体
装置１全体のアウターリードの本数を増加することがで
きる。Embodiments of the semiconductor device of the present invention will be described with reference to the drawings. 1 is a perspective view illustrating a semiconductor device of the present invention, FIG. 2A is a plan view of the semiconductor device of the present invention, and FIG.
(B) is a sectional view taken along the line AA of (a). That is, as shown in FIG. 1, in the semiconductor device 1 of the present invention, the semiconductor element 11 wired to the outer lead 13 and the inner lead 14 is integrally sealed by a package 10 such as a mold resin. This is a so-called QFP structure in which a plurality of outer outer leads 13a are respectively led out from one outer peripheral end face. In this package 10, for example, an elongated opening 12 is bored substantially parallel to the outer peripheral end surface of each package 10, and a plurality of inner outer leads 14a are led out from the inner side surface of the opening 12. The inner outer leads 14a can increase the number of outer leads of the entire semiconductor device 1.
【０００７】図２（ａ）に示すように、開口部１２は外
側リード１３および内側リード１４の半導体素子１１側
の端部からパッケージ１０の外周端面までのパッケージ
１０内、すなわち斜線領域Ｓ内に穿設されたものであ
る。内側リード１４は外側リード１３と外側リード１３
との間に並設されており、この開口部１２の内側側面か
ら内側アウターリード１４ａとして複数導出される。こ
の内側アウターリード１４ａの先端は、図２（ｂ）に示
すように略Ｌ型に折り曲げられている。また、外側アウ
ターリード１３ａの先端もこの内側アウターリード１４
ａの先端と同様にそれぞれ略Ｌ型に折り曲げられてお
り、外側アウターリード１３ａおよび内側アウターリー
ド１４ａの各先端下面が同一平面上となるようパッケー
ジ１０の底面から突出した状態に設けられている。As shown in FIG. 2A, the opening 12 is formed in the package 10 from the end of the outer lead 13 and the inner lead 14 on the semiconductor element 11 side to the outer peripheral end face of the package 10, that is, in the shaded area S. It has been drilled. The inner lead 14 includes the outer lead 13 and the outer lead 13.
And a plurality of inner outer leads 14a are led out from the inner side surface of the opening 12. The tips of the inner outer leads 14a are bent into a substantially L shape as shown in FIG. 2 (b). Further, the tips of the outer outer leads 13a are also connected to the inner outer leads 14
Like the tip of a, each is bent into a substantially L shape, and the outer outer leads 13a and the inner outer leads 14a are provided so as to project from the bottom surface of the package 10 so that the lower surfaces of the respective tips are flush with each other.
【０００８】このような構造により、例えば外側アウタ
ーリード１３ａを通常のＱＦＰ構造と同様に１２０本導
出させた場合、さらに４か所の開口部１２から最高６０
本の内側アウターリード１４ａを導出させることができ
る。なお、図２（ａ）のパッケージ１０内には４か所の
開口部１２が穿設されているが、内側アウターリード１
４ａの本数が少ない場合は４か所以下でもよい。With such a structure, for example, when 120 outer outer leads 13a are led out in the same manner as the normal QFP structure, a maximum of 60 from the four openings 12 is provided.
The inner outer lead 14a of the book can be led out. It should be noted that although four openings 12 are formed in the package 10 of FIG.
If the number of 4a is small, it may be 4 or less.
【０００９】次に、本発明の半導体装置１のリードにつ
いて図３に基づいて説明する。図３（ａ）は半導体装置
のリードの平面図、図３（ｂ）は（ａ）のＢ部拡大図で
ある。すなわち、外側リード１３と内側リード１４は、
パッケージ１０のほぼ中央に搭載される半導体素子１１
の周縁付近から交互に配置され、それぞれ外側方向に接
触することなく延びている。この外側リード１３は各対
応するパッケージ１０の外周端面から外側アウターリー
ド１３ａとして導出されることになる。一方、内側リー
ド１４は各対応する開口部１２の内側側面から内側アウ
ターリード１４ａとして導出されることになる。Next, the leads of the semiconductor device 1 of the present invention will be described with reference to FIG. FIG. 3A is a plan view of the leads of the semiconductor device, and FIG. 3B is an enlarged view of a B portion of FIG. That is, the outer lead 13 and the inner lead 14 are
A semiconductor element 11 mounted almost in the center of the package 10.
Are arranged alternately from the vicinity of the peripheral edge of each of them and extend in the outward direction without contacting each other. The outer leads 13 are led out as outer outer leads 13a from the outer peripheral end faces of the corresponding packages 10. On the other hand, the inner leads 14 are led out as inner outer leads 14a from the inner side surfaces of the corresponding openings 12.
【００１０】また、図３（ｂ）に示すように、外側リー
ド１３のリード幅は、外側アウターリード１３ａ側より
半導体素子１１側の方が細く形成されている。この細く
形成された外側リード１３と外側リード１３との間に内
側リード１４が並設されているため、内側アウターリー
ド１４ａを外側アウターリード１３ａの導出部分と等し
いリード幅およびピッチで配置することができる。As shown in FIG. 3B, the lead width of the outer lead 13 is smaller on the semiconductor element 11 side than on the outer outer lead 13a side. Since the inner leads 14 are juxtaposed between the thin outer leads 13 and the outer leads 13, it is possible to arrange the inner outer leads 14a with the same lead width and pitch as the lead portions of the outer outer leads 13a. it can.
【００１１】本発明の半導体装置１を製造するには、前
述のリードが複数形成されたリードフレームを用いる。
すなわち、リードフレームに形成された各リードのほぼ
中央に半導体素子１１をそれぞれ配置して、この半導体
素子１１の上面に形成された電極パッドと外側リード１
３および内側リード１４とをボンディングワイヤー等に
よりそれぞれ接続する。そして、半導体素子１１が搭載
されたリードフレームを所定形状のキャビティを有する
金型内に配置して、モールド樹脂等のパッケージ１０に
て一体封止する。なお、この一体封止の際、前述の開口
部１２を形成するため、開口部１２にモールド樹脂が充
填されないようなキャビティ形状を有する金型を用いれ
ば、パッケージ１０の形成と同時に開口部１２が穿設さ
れた半導体装置１を容易に製造することができる。To manufacture the semiconductor device 1 of the present invention, a lead frame having a plurality of the aforementioned leads is used.
That is, the semiconductor element 11 is arranged substantially at the center of each lead formed on the lead frame, and the electrode pad and the outer lead 1 formed on the upper surface of the semiconductor element 11 are arranged.
3 and the inner lead 14 are connected to each other by a bonding wire or the like. Then, the lead frame on which the semiconductor element 11 is mounted is placed in a mold having a cavity of a predetermined shape, and is integrally sealed with a package 10 such as a mold resin. Since the opening 12 is formed during this integral sealing, if a mold having a cavity shape such that the opening 12 is not filled with the molding resin is used, the opening 12 is formed simultaneously with the formation of the package 10. The punched semiconductor device 1 can be easily manufactured.
【００１２】[0012]
【発明の効果】以上説明したように本発明の半導体装置
によれば次のような効果がある。すなわち、外側リード
と外側リードとの間に内側リードが並設され、かつこの
内側リードがパッケージ内に穿設された開口部の内側側
面から内側アウターリードとして導出されているので、
パッケージの大きさを大きくすることなく、かつリード
幅およびピッチを狭くすることなく通常の１．５倍程度
のリード本数を設けることが可能となる。さらに、内側
アウターリードはパッケージ内の開口部の内側側面から
導出されているので、半導体装置をプリント配線板等に
ハンダ付けした場合、開口部の上方から内側アウターリ
ードのハンダ付け状態が容易に目視できる。As described above, the semiconductor device of the present invention has the following effects. That is, since the inner lead is juxtaposed between the outer lead and the outer lead, and the inner lead is led out as the inner outer lead from the inner side surface of the opening formed in the package,
It is possible to provide the number of leads that is about 1.5 times the normal number without increasing the package size and narrowing the lead width and pitch. Furthermore, since the inner outer lead is led out from the inner side surface of the opening inside the package, when soldering the semiconductor device to a printed wiring board etc., the soldering state of the inner outer lead can be easily viewed from above the opening. it can.
【図１】本発明の半導体装置を説明する斜視図である。FIG. 1 is a perspective view illustrating a semiconductor device of the present invention.
【図２】本発明の半導体装置を説明する図で、（ａ）は
平面図、（ｂ）は（ａ）のＡ−Ａ線矢視断面図である。2A and 2B are views illustrating a semiconductor device of the present invention, FIG. 2A is a plan view, and FIG. 2B is a sectional view taken along the line AA of FIG.
【図３】本発明の半導体装置のリードを説明する図で、
（ａ）は平面図、（ｂ）は（ａ）のＢ部拡大図である。FIG. 3 is a diagram illustrating leads of a semiconductor device of the present invention,
(A) is a plan view and (b) is an enlarged view of a portion B of (a).
【図４】従来の半導体装置を説明する斜視図である。FIG. 4 is a perspective view illustrating a conventional semiconductor device.
１ 半導体装置 １０ パッケージ １１ 半導体素子 １２ 開口部 １３ 外側リード １３ａ 外側アウターリード １４ 内側リード １４ａ 内側アウターリード 1 Semiconductor Device 10 Package 11 Semiconductor Element 12 Opening 13 Outer Lead 13a Outer Outer Lead 14 Inner Lead 14a Inner Outer Lead
Claims (1)
止するパッケージと、前記パッケージから前記リードが
導出して成るアウターリードとから構成される半導体装
置において、 前記アウターリードは内側アウターリードと外側アウタ
ーリードとを交互に並設したもので、前記パッケージ内
に穿設した開口部の内側側面から前記内側アウターリー
ドを導出させるとともに、前記パッケージの外周端面か
ら前記外側アウターリードを導出させたことを特徴とす
る半導体装置。1. A semiconductor device comprising a package integrally encapsulating a semiconductor element wired to a lead, and an outer lead formed by leading the lead from the package, wherein the outer lead is an inner outer lead and an outer side. Outer leads are alternately arranged side by side, and the inner outer leads are led out from the inner side surface of the opening formed in the package, and the outer outer leads are led out from the outer peripheral end surface of the package. Characteristic semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3304129A JPH05114671A (en) | 1991-10-22 | 1991-10-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3304129A JPH05114671A (en) | 1991-10-22 | 1991-10-22 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05114671A true JPH05114671A (en) | 1993-05-07 |
Family
ID=17929393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3304129A Pending JPH05114671A (en) | 1991-10-22 | 1991-10-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05114671A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09153569A (en) * | 1995-11-30 | 1997-06-10 | Nec Corp | Resin-encapsulated semiconductor device |
| KR100342812B1 (en) * | 1996-11-28 | 2002-11-18 | 앰코 테크놀로지 코리아 주식회사 | Area array bumped semiconductor package having ground and power lines |
| KR100342811B1 (en) * | 1996-11-28 | 2002-11-27 | 앰코 테크놀로지 코리아 주식회사 | Area array bumped semiconductor package with chips |
| KR100342813B1 (en) * | 1996-11-28 | 2002-11-30 | 앰코 테크놀로지 코리아 주식회사 | Area array bumped semiconductor package having ground and power lines |
| KR100379083B1 (en) * | 1996-11-28 | 2004-02-05 | 앰코 테크놀로지 코리아 주식회사 | Lead on chip(loc) area array bumped semiconductor package |
-
1991
- 1991-10-22 JP JP3304129A patent/JPH05114671A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09153569A (en) * | 1995-11-30 | 1997-06-10 | Nec Corp | Resin-encapsulated semiconductor device |
| KR100342812B1 (en) * | 1996-11-28 | 2002-11-18 | 앰코 테크놀로지 코리아 주식회사 | Area array bumped semiconductor package having ground and power lines |
| KR100342811B1 (en) * | 1996-11-28 | 2002-11-27 | 앰코 테크놀로지 코리아 주식회사 | Area array bumped semiconductor package with chips |
| KR100342813B1 (en) * | 1996-11-28 | 2002-11-30 | 앰코 테크놀로지 코리아 주식회사 | Area array bumped semiconductor package having ground and power lines |
| KR100379083B1 (en) * | 1996-11-28 | 2004-02-05 | 앰코 테크놀로지 코리아 주식회사 | Lead on chip(loc) area array bumped semiconductor package |
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