JPH01205456A - Multi-pin case for lsi - Google Patents
Multi-pin case for lsiInfo
- Publication number
- JPH01205456A JPH01205456A JP2939088A JP2939088A JPH01205456A JP H01205456 A JPH01205456 A JP H01205456A JP 2939088 A JP2939088 A JP 2939088A JP 2939088 A JP2939088 A JP 2939088A JP H01205456 A JPH01205456 A JP H01205456A
- Authority
- JP
- Japan
- Prior art keywords
- terminals
- lsi
- case
- main body
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000694 effects Effects 0.000 description 2
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野１
本発明は、ＬＳＩチップを実装するＬＳＩ用多ピンケー
スに関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a multi-pin case for an LSI in which an LSI chip is mounted.
「従来の技術］
従来、この種のＬＳＩ用多ピンケースは側面より１列に
端子を突出させた構造となっていた。その構造について
第２図（ａ）〜（Ｃ）に示す。"Prior Art" Conventionally, this type of multi-pin case for LSI has a structure in which terminals are projected in one row from the side surface.The structure is shown in FIGS. 2(a) to 2(C).
第２図（ａ）はＬＳＩ用多ピンケースの外観図である。FIG. 2(a) is an external view of a multi-pin case for LSI.
ＬＳＩ用多ピンケース２０の側面には端子２１が１列に
設けられている。第２図（ｂ）はＬＳＩ用多ピンケース
２００部分切欠図、第２図（Ｃ）は断面図である。ＬＳ
Ｉ用多ピンケース２０に設けられた端子２１は、ＬＳＩ
用多ピンケース２０内に実装されたＬＳＩチップ２２と
ボンデインクワイヤ２３によって接続されている。Terminals 21 are provided in one row on the side surface of the multi-pin case 20 for LSI. FIG. 2(b) is a partial cutaway view of the multi-pin case 200 for LSI, and FIG. 2(C) is a sectional view. L.S.
The terminal 21 provided in the I multi-pin case 20 is for LSI
It is connected to an LSI chip 22 mounted in a multi-pin case 20 by a bonding wire 23.
上記ＬＳＩ用多ピンケース２０は、その端子２１をプリ
ント基板上に接続することにより配線がなされる。The LSI multi-pin case 20 is wired by connecting its terminals 21 to a printed circuit board.
［発明が解決しようとする課題］
上述した従来のＬＳＩ用多ピンケース２０は、側面から
１列に端子２１を突出させているので、端子数が増加す
るに伴い各辺の寸法か犬きくなり、プリント基板に実装
する場合、実装面積の増加をまねくという欠点があった
。[Problems to be Solved by the Invention] Since the conventional LSI multi-pin case 20 described above has the terminals 21 protruding from the side in one row, the dimensions of each side become smaller as the number of terminals increases. However, when mounting on a printed circuit board, there is a drawback that the mounting area increases.
［課題を解決するための手段］
本発明は、上記従来の課題を解決し、実装面積を減少さ
せることかできるＬＳＩ用多ピンケースを提供すること
を目的としてなされたものである。[Means for Solving the Problems] The present invention has been made for the purpose of solving the above-mentioned conventional problems and providing a multi-pin case for LSI that can reduce the mounting area.
かかる目的を達成するため本発明は、ケース本体内部に
ＬＳＩチップを実装し、ケース本体の各側面から該ＬＳ
Ｔチップと接続した端子を突出させてなるＬＳＩ用多ピ
ンケースにおいて、ケース本体の各側面に突出長さの異
なる端子を上下２列に配置させた構成としている。In order to achieve this object, the present invention mounts an LSI chip inside the case body, and the LSI chip is mounted from each side of the case body.
A multi-pin case for an LSI having protruding terminals connected to a T-chip has a structure in which terminals with different protruding lengths are arranged in two rows, upper and lower, on each side of the case body.
［実施例］
次に、本発明の一実施例について図面を参照して詳細に
説明する。[Example] Next, an example of the present invention will be described in detail with reference to the drawings.
第１図（ａ） （ｂ） （ｃ）は各々本発明の一実施例
に係るＬＳＩ用多ピンケースの外観図、部分切欠図、断
面図である。本実施例のＬＳＩ用多ピンケース１は、ケ
ース本体１ａと端子２，３により構成されている。FIGS. 1(a), 1(b), and 1(c) are an external view, a partially cutaway view, and a sectional view of a multi-pin case for LSI according to an embodiment of the present invention. The multi-pin case 1 for LSI of this embodiment is composed of a case body 1a and terminals 2 and 3.
ケース本体１ａは、図示の如く薄い立方体形状に形成さ
れており、第１図（ｃ）に示す如くその内部にはＬＳＩ
チップ４か実装されている。The case body 1a is formed into a thin cubic shape as shown in the figure, and has an LSI inside as shown in FIG. 1(c).
Chip 4 is installed.
端子−２，３は、各々」−記ケース本体１ａの側面から
突出した状態で設けられている。端子２゜３は、互いに
接触しないように一定の間隔を介して上下２列に配列さ
れており、端子２が−に側、端子３か下側に位置してい
る。Terminals 2 and 3 are provided in a state in which they each protrude from the side surface of the case body 1a. The terminals 2 and 3 are arranged in two rows, upper and lower, at regular intervals so as not to contact each other, with terminal 2 being located on the negative side and terminal 3 being located on the lower side.
また、第１図（ｂ） （Ｃ）に示すように端子２゜３
のケース本体１ａ側面からの突出長さは、端子２の方が
端子３よりも長くなフている。これによって、端子２，
３を互いに接触させることなくプリント基板に接続する
ことかてきるものである。Also, as shown in Fig. 1(b)(C), the terminal 2゜3
The length of the terminal 2 protruding from the side surface of the case body 1a is longer than that of the terminal 3. As a result, terminal 2,
3 can be connected to a printed circuit board without making them contact each other.
また、このように上下２列に端子２，３を配列したこと
により、ケース本体１ａの側面に配置することのできる
端子数が従来の２倍となり、その分ケース本体１ａの寸
法を小さくすることができる。Furthermore, by arranging the terminals 2 and 3 in two rows above and below, the number of terminals that can be arranged on the side surface of the case body 1a is doubled compared to the conventional case, and the dimensions of the case body 1a can be reduced accordingly. Can be done.
なお、端子２，３の先端は、ケース本体１ａに対し互い
に同し高さに形成してあり、プリント基板に対し同時に
接触するようになっている。Note that the tips of the terminals 2 and 3 are formed at the same height with respect to the case body 1a, so that they contact the printed circuit board at the same time.
さらに、端子２，３はケース本体１ａ内において、ボン
デインクワイヤ５，６によって各々ＬＳＩチップ４と電
気的に接続されている。Furthermore, the terminals 2 and 3 are electrically connected to the LSI chip 4 by bonding wires 5 and 6, respectively, within the case body 1a.
［発明の効果］
以上説明したように本発明は、ケース本体内部にＬＳＩ
チップを実装し、ケース本体の各側面から該ＬＳＩチッ
プと接続した端子を突出させてなるＬＳＩ用多ピンケー
スにおいて、ケース本体の各側面に突出長さの異なる端
子を上下２列に配置させたことにより、従来のＬＳＩ用
多ピンケースと比較して２倍の密度で端子を設けること
かてきるのて、１辺当りの寸法を坏の長さとすることが
でき、プリント基板に実装した場合実装面積を減らすこ
とかできる効果がある。[Effects of the Invention] As explained above, the present invention has an LSI inside the case body.
In a multi-pin case for LSI in which a chip is mounted and terminals connected to the LSI chip protrude from each side of the case body, terminals with different protruding lengths are arranged in two rows above and below on each side of the case body. As a result, terminals can be provided at twice the density compared to conventional LSI multi-pin cases, and the dimension per side can be made equal to the length of a piece, and when mounted on a printed circuit board. This has the effect of reducing the mounting area.
第１図（ａ）は本発明の一実施例に係るＬＳＩ用多ピン
ケースの外観図、第１図（ｂ）は第１図（ａ）に示すＬ
ＳＩ用多ピンケースの部分切欠図、第１図（ｃ）は第１
図（ａ）に示すＬＳＩ用多ピンケースの断面図、第２図
（ａ）は従来のＬＳＩ用多ピンケースの外観図、第２図
（ｂ）はその部分切欠図、第２図（Ｃ）はその断面図で
ある。
１：ＬＳＩ用多ピンケース
１ａ：ケース本体
２．３：端子
４ ： ＬＳ Ｉチップ
５．６：ボンデインクワイヤFIG. 1(a) is an external view of a multi-pin case for LSI according to an embodiment of the present invention, and FIG. 1(b) is an external view of a multi-pin case for LSI according to an embodiment of the present invention.
Partial cutaway view of multi-pin case for SI, Figure 1(c) is the first
FIG. 2(a) is an external view of a conventional multi-pin LSI case, FIG. 2(b) is a partial cutaway view, and FIG. ) is its cross-sectional view. 1: Multi-pin case for LSI 1a: Case body 2.3: Terminal 4: LS I chip 5.6: Bond ink wire
Claims (1)
の各側面から該ＬＳＩチップと接続した端子を突出させ
てなるＬＳＩ用多ピンケースにおいて、 ケース本体の各側面に突出長さの異なる端子を上下２列
に配置させたことを特徴とするＬＳＩ用多ピンケース。[Claims] In a multi-pin case for an LSI, in which an LSI chip is mounted inside the case body and terminals connected to the LSI chip are protruded from each side of the case body, each side of the case body has a protruding length. A multi-pin case for LSI, characterized by having different terminals arranged in two rows, upper and lower.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2939088A JPH01205456A (en) | 1988-02-10 | 1988-02-10 | Multi-pin case for lsi |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2939088A JPH01205456A (en) | 1988-02-10 | 1988-02-10 | Multi-pin case for lsi |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01205456A true JPH01205456A (en) | 1989-08-17 |
Family
ID=12274815
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2939088A Pending JPH01205456A (en) | 1988-02-10 | 1988-02-10 | Multi-pin case for lsi |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01205456A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5821457A (en) * | 1994-03-11 | 1998-10-13 | The Panda Project | Semiconductor die carrier having a dielectric epoxy between adjacent leads |
| US5819403A (en) * | 1994-03-11 | 1998-10-13 | The Panda Project | Method of manufacturing a semiconductor chip carrier |
| US5824950A (en) * | 1994-03-11 | 1998-10-20 | The Panda Project | Low profile semiconductor die carrier |
| US6008530A (en) * | 1997-05-29 | 1999-12-28 | Nec Corporation | Polyhedral IC package for making three dimensionally expandable assemblies |
| US6141869A (en) * | 1998-10-26 | 2000-11-07 | Silicon Bandwidth, Inc. | Apparatus for and method of manufacturing a semiconductor die carrier |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60103652A (en) * | 1983-11-11 | 1985-06-07 | Hitachi Ltd | Semiconductor device and lead frame used therefor |
| JPS6113654A (en) * | 1984-06-29 | 1986-01-21 | Toshiba Corp | Electronic parts |
-
1988
- 1988-02-10 JP JP2939088A patent/JPH01205456A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60103652A (en) * | 1983-11-11 | 1985-06-07 | Hitachi Ltd | Semiconductor device and lead frame used therefor |
| JPS6113654A (en) * | 1984-06-29 | 1986-01-21 | Toshiba Corp | Electronic parts |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5821457A (en) * | 1994-03-11 | 1998-10-13 | The Panda Project | Semiconductor die carrier having a dielectric epoxy between adjacent leads |
| US5819403A (en) * | 1994-03-11 | 1998-10-13 | The Panda Project | Method of manufacturing a semiconductor chip carrier |
| US5824950A (en) * | 1994-03-11 | 1998-10-20 | The Panda Project | Low profile semiconductor die carrier |
| US6339191B1 (en) * | 1994-03-11 | 2002-01-15 | Silicon Bandwidth Inc. | Prefabricated semiconductor chip carrier |
| US6977432B2 (en) | 1994-03-11 | 2005-12-20 | Quantum Leap Packaging, Inc. | Prefabricated semiconductor chip carrier |
| US6008530A (en) * | 1997-05-29 | 1999-12-28 | Nec Corporation | Polyhedral IC package for making three dimensionally expandable assemblies |
| US6141869A (en) * | 1998-10-26 | 2000-11-07 | Silicon Bandwidth, Inc. | Apparatus for and method of manufacturing a semiconductor die carrier |
| US6857173B1 (en) | 1998-10-26 | 2005-02-22 | Silicon Bandwidth, Inc. | Apparatus for and method of manufacturing a semiconductor die carrier |
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