JPS60103652A - Semiconductor device and lead frame used therefor - Google Patents
Semiconductor device and lead frame used thereforInfo
- Publication number
- JPS60103652A JPS60103652A JP58210810A JP21081083A JPS60103652A JP S60103652 A JPS60103652 A JP S60103652A JP 58210810 A JP58210810 A JP 58210810A JP 21081083 A JP21081083 A JP 21081083A JP S60103652 A JPS60103652 A JP S60103652A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- leads
- semiconductor device
- lead frame
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
- H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置およびその製造において用いられる
リードフレームに関し、特に半導体装置の小型化が達成
できる技術に関する□
〔背景技術〕
半導体装置の高集積化、多機能化によって外部端子（リ
ード）の数は増大し、半導体装置は大型となる傾向にあ
るが、半導体装置を組み込む電子機器群の小型化に伴な
って半導体装置の小型化が強く望まれている。チップ等
の主要部をレジンパッケージで被ったレジンモールド型
半導体装置においても、たとえば電子材料１９８０年１
０月号１２１〜１２４頁「きニフラットＩＯＪにも記載
されているように、より小型化か図られている。[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor device and a lead frame used in its manufacture, and in particular relates to a technology that can achieve miniaturization of semiconductor devices. [Background Art] High integration and multiplication of semiconductor devices As semiconductor devices become more functional, the number of external terminals (leads) increases, and semiconductor devices tend to become larger. However, as the electronic devices into which semiconductor devices are incorporated become smaller, there is a strong desire for smaller semiconductor devices. . Even in resin molded semiconductor devices in which the main parts such as chips are covered with a resin package, electronic materials 1980 1
As described in the October issue, pages 121-124, "Kiniflat IOJ," efforts are being made to make it even more compact.
ところで、従来のレジンモールド型半導体装置は、たと
えば、電子材料１９８２年８月号６９〜７４頁「リード
フレーム」にも記載されているように、板状のリードフ
レームを用いて製造されている。By the way, conventional resin molded semiconductor devices are manufactured using plate-shaped lead frames, as described in "Lead Frame", pages 69-74 of Electronic Materials, August 1982, for example.
しかし、このようなリードフレームによる半導体装置の
製造では、リード数の多い製品群の小型化は、以下の理
由から離しいということが本発明者によってあきらかと
された。However, in manufacturing semiconductor devices using such lead frames, the inventors have found that it is difficult to downsize products with a large number of leads for the following reasons.
すなわち、リードフレームは一枚の平面板によって形成
されているため、リードは同一平面上忙並んでいる。リ
ード数の増大によってリードピッチはより小さく設計さ
れるが、シロート防止等の観点から限度がある。また、
リードフレームの小型化という点から考えれば、前記リ
ードピッチを小さくする以外に、リード幅を小さくする
ことが考えられる。しかし、リード数が多くなるにつれ
て、レジンパッケージの寸法が大きくなるため、レジン
パッケージ内ｌ延在するリード（インナーリード）の長
さが長くなり、リードの強度低下を引き起こす。この結
果、インナーリードの幅の縮小化にも限度があり、リー
ド数増加に伴なってパッケージ寸法は順次増大すること
になる。That is, since the lead frame is formed from a single plane plate, the leads are lined up on the same plane. The lead pitch is designed to be smaller as the number of leads increases, but there is a limit from the viewpoint of preventing whiteout. Also,
From the point of view of miniaturizing the lead frame, it is conceivable to reduce the lead width in addition to reducing the lead pitch. However, as the number of leads increases, the dimensions of the resin package increase, and the length of the leads (inner leads) extending inside the resin package increases, causing a decrease in the strength of the leads. As a result, there is a limit to the reduction in the width of the inner leads, and as the number of leads increases, the package dimensions gradually increase.
一方、レジンパッケージにおいてハ、パッケージが大き
くなるにつれて、レジンモールド時のモールド型のキャ
ビティ内へのレジンの流入が複雑となり、ボイド（気泡
）等の欠陥の発生が増大し易くなって製品品質の低下を
招くことも本発明者によってあきらかとされた。On the other hand, in the case of resin packages, as the size of the package increases, the flow of resin into the mold cavity during resin molding becomes more complicated, and defects such as voids (bubbles) are more likely to occur, resulting in a decline in product quality. The inventor has also found that this may lead to
本発明の目的は半導体装置の小型化を図ることにある。 An object of the present invention is to reduce the size of a semiconductor device.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、本発明はリードフレームを平行に重ね合わせ
た２枚の副リードフレームで構成しておき、このリード
フレームを用いて半導体装置を製造するものである。副
リードフレームのリードは他の副リードフレームのリー
ド間の上方あるいは下方に位置して千鳥状に２段に配列
され℃いる。That is, in the present invention, a lead frame is constructed of two sub-lead frames superimposed in parallel, and a semiconductor device is manufactured using these lead frames. The leads of the sub-lead frame are arranged in two stages in a staggered manner, located above or below the leads of other sub-lead frames.
また、リードは内端近傍部分で上方あるいは下方に一段
折れ曲がり、内端のワイヤ接続部分はすべて同一平面上
になっている。したがって、このようなリードフレーム
によって製造された半導体装置はリードがパッケージの
内外で千鳥状に二段となって配列されていることから、
従来のようにリードが一段に配列された半導体装置より
も小型となる。Further, the leads are bent one step upward or downward near the inner end, and the wire connection portions at the inner end are all on the same plane. Therefore, in a semiconductor device manufactured using such a lead frame, the leads are arranged in two stages in a staggered manner inside and outside the package.
It is smaller than a conventional semiconductor device in which leads are arranged in one row.
第１図は本発明の一実施例による半導体装置の正面図、
第２図は同じく平面図、第３図は同じく側面図、第４図
（ａ）、 （ｂ）は前記半導体装置の組立に用いるリー
ドフレームを構成する副リードフレームの平面図、第５
図（ａｌ、 （ｂ）は同じく一部の断面図、第６図は同
じくリードフレームの要部を示す斜視図である。FIG. 1 is a front view of a semiconductor device according to an embodiment of the present invention;
2 is a plan view, FIG. 3 is a side view, FIGS. 4(a) and 4(b) are plan views of a sub-lead frame constituting the lead frame used in the assembly of the semiconductor device, and
Figures (al and b) are partially sectional views, and FIG. 6 is a perspective view showing the main parts of the lead frame.
レジンモールド型の半導体装置１は第１図〜第３図で示
すようにレジンパッケージ２の両側面からリード３が千
鳥状に２段になって突出した構造となつ又いる。また、
各リード３は途中で階段状に一段折れ曲がり、先端部下
面はレジンパッケージ２の下面と略同−面となるように
形成され、いわゆる面実装構造となっている。各リード
３はその延在方向に垂直となる面における配列はいずれ
も千鳥状）ＩＣ２段となる配列となりている。これは、
後述するがレジンパッケージ２内においても、内端部を
除いて同様な配列となっている。なお、隣接するリード
相互のピッチ（リードピッチ）はリードを線材と考えた
場合ともにａと同一にすることにより、レジンパッケー
ジ２の平面方向およびこれに垂直となる高さ方向の寸法
を最小に抑えることができる。As shown in FIGS. 1 to 3, the resin mold type semiconductor device 1 has a structure in which leads 3 protrude from both sides of a resin package 2 in two stages in a staggered manner. Also,
Each lead 3 is bent one step in the middle, and the lower surface of the tip is formed to be approximately flush with the lower surface of the resin package 2, forming a so-called surface mount structure. Each lead 3 is arranged in a staggered pattern in a plane perpendicular to its extending direction, with two IC stages. this is,
As will be described later, the resin package 2 has a similar arrangement except for the inner end. In addition, by making the pitch between adjacent leads (lead pitch) the same as a when considering the leads as wire rods, the dimensions of the resin package 2 in the plane direction and the height direction perpendicular thereto are minimized. be able to.
このような半導体装置１はリード配列方向の寸法が従来
のリードが一列の半導体装置に比較して半分となる。し
たがって、レジンパッケージ２の両側からり−ド３を突
出させる本実施例の半導体装置ではレジンパッケージ２
の大きさく面積）が従来の半導体装置の半分となる。Such a semiconductor device 1 has a dimension in the lead arrangement direction that is half that of a conventional semiconductor device with a single line of leads. Therefore, in the semiconductor device of this embodiment in which the leads 3 protrude from both sides of the resin package 2, the resin package 2
The area (larger area) is half that of conventional semiconductor devices.
つぎに、このような半導体装置１の製造（組立）方法に
ついて説明し、あわせてレジンパッケージ２内部の説明
とする。半導体装置１の組立にあっては、第６図に示す
ようなリードフレーム４が用いられる。このリードフレ
ーム４は第４図（ａｌ、 （ｂｌで示すような２枚の副
リードフレーム５，６によって構成されている。副リー
ドフレーム５，６は平行に重ねられ、かつ両側リードフ
レーム５，６のフレーム枠７，８の突出した接続部９，
１００溶接によって固定され一体化構造となっている。Next, a method for manufacturing (assembling) such a semiconductor device 1 will be explained, and the inside of the resin package 2 will also be explained. In assembling the semiconductor device 1, a lead frame 4 as shown in FIG. 6 is used. This lead frame 4 is composed of two sub lead frames 5 and 6 as shown in FIGS. 6, the protruding connecting portions 9 of the frame frames 7, 8,
It is fixed by 100% welding and has an integrated structure.
副リードフレーム５，６の一方は第４図（ａ）に示すよ
うに、タブ１１．タブ１１をフレーム枠７に接続するタ
ブ吊りリード１２．タブ１１に内端を臨マせる複数のり
−ド３．リード３をフレーム枠７に支持するタイバー１
３．レジンモールド時のレジン流を止める役割を果たす
ダム１４とからなっている。また、このタブ有り副リー
ドフレーム５はタブ１１およびリード３の内端が第５図
（ａ）に示すように低くなっている。このため、タブ吊
りリード１２およびリード３は途中部分で一段階段状に
折れ曲がっている。なお、タブ１１の上面には半導体素
子（チップ）１５が固定され、チップ１５の電極とリー
ド３の内端のワイヤ接続部１６はワイヤ１７で接続され
る。この際、ワイヤ１７が垂れてチップ１５の縁に接触
して生じるショート不良が起き易い。そこで、この例で
はチップ１５の上面とり−ド３のワイヤ接続部１６の面
とが略一致するように、タブ１１はリード３の内端部よ
りもさらに低くなっている。As shown in FIG. 4(a), one of the sub lead frames 5 and 6 has a tab 11. A tab suspension lead 12 for connecting the tab 11 to the frame frame 7. A plurality of glue boards whose inner ends are facing the tab 11 3. Tie bar 1 supporting lead 3 to frame frame 7
3. It consists of a dam 14 that plays a role in stopping the flow of resin during resin molding. Further, in this sub-lead frame 5 with tabs, the inner ends of the tabs 11 and leads 3 are lowered as shown in FIG. 5(a). For this reason, the tab suspension lead 12 and the lead 3 are bent in one step in the middle. Note that a semiconductor element (chip) 15 is fixed on the upper surface of the tab 11, and the electrode of the chip 15 and the wire connection portion 16 at the inner end of the lead 3 are connected by a wire 17. At this time, the wire 17 is likely to hang down and come into contact with the edge of the chip 15, resulting in a short-circuit failure. Therefore, in this example, the tab 11 is lower than the inner end of the lead 3 so that the upper surface of the chip 15 is substantially aligned with the surface of the wire connection portion 16 of the lead 3.
一方、前記タブ有り副リードフレーム５の下側に位置す
る第４図（ｂｌで示すタブ無し副リードフレーム６はタ
ブ有り副リードフレーム５のフレーム枠７．タイバー１
３．ダム１４と対面するフレーム枠８．タイバー１８．
ダム１９を有している。On the other hand, the tab-less sub-lead frame 6 located below the tab-equipped sub-lead frame 5 shown in FIG.
3. Frame frame 8 facing the dam 14. Tie bar 18.
It has a dam 19.
しかし、タブ有り副す−ドブンーム５のようなタブ１１
およびタブリード１２は有していない。また、リード３
はタブ有り副リードフレーム５と同様に有しているが、
その位置は平面的に見てタブ有り副リードフレーム５の
各リード３の中間位置ＶＣ１本ずつ位置するように配設
されている。また、タブ無し副リードフレーム６は第５
図（ｂ）ＶＣ示すように、リード３の内端が上方に一段
階段状に折れ曲がっている。折れ曲がって水平となるリ
ード内端部分はワイヤ接続部２０となる。このワイヤ接
続”部２０は、タブ有り副リードフレーム５とタブ無し
副リードフレーム６’？！−重ねて一体化した際には、
タブ有り副リードフレーム５のワイヤ接続部１６と同一
平面上に位置するようになっている。However, if there is a tab, there is a tab 11 like Dobun Room 5.
And the tab lead 12 is not included. Also, lead 3
has the same structure as the tab-equipped sub-lead frame 5, but
The positions thereof are arranged such that one VC is located at the middle position of each lead 3 of the sub lead frame 5 with tabs when viewed from above. In addition, the sub lead frame 6 without tabs is the fifth
As shown in Figure (b) VC, the inner end of the lead 3 is bent upward in one step. The inner end portion of the lead that is bent and becomes horizontal becomes a wire connection portion 20 . When this wire connection section 20 is stacked and integrated with the sub lead frame 5 with tab and the sub lead frame 6' without tab,
It is positioned on the same plane as the wire connection portion 16 of the sub lead frame 5 with tabs.
これは、 ％Ｖｃ限定はされないが、ワイヤボンディン
グ時にリード側のワイヤ接続部の高さが高くなったり低
くなったりすると接続し難いことによる。This is because, although not limited to %Vc, it is difficult to connect if the height of the wire connection portion on the lead side becomes high or low during wire bonding.
したがって、リード側のワイヤ接続部高さが一定でなく
とも確実にワイヤ接続ができるワイヤボンディング装置
である場合には、両側リードフレーム５，６Ｖｃおゆる
リード内端部の同一平面化は必要ではなくなる。なお、
リード３が千鳥状に二段に配列されることによりてはじ
めてリードフレーム４およびレジンパッケージ２の小型
化か達成できる。これに対して、実施例ではリード内端
部分が一段となっているが、これはリード内端部はワイ
ヤ接続部１６．２０となることから、ワイヤ接続に必要
な面積（太さ）があればよく、他のＩｌ −ド部分のよ
うに大きな機械的強度を必要としないことによって他の
リード部分よりも細くできることによる。本発明はこの
点の着眼によって小型化が達成できたものである。Therefore, in the case of a wire bonding device that can reliably connect wires even if the height of the wire connection part on the lead side is not constant, it is not necessary to make the inner ends of the leads on both sides of the lead frame 5, 6Vc on the same plane. . In addition,
Only by arranging the leads 3 in two stages in a staggered manner can miniaturization of the lead frame 4 and the resin package 2 be achieved. On the other hand, in the embodiment, the inner end of the lead is one step, but this is because the inner end of the lead becomes the wire connection part 16.20, so if there is an area (thickness) necessary for wire connection, then This is often due to the fact that it does not require as much mechanical strength as other lead parts, and thus can be made thinner than other lead parts. The present invention has achieved miniaturization by focusing on this point.
このようなリードフレーム４はタブ１１上にチップ１５
が接続される。また、チップ１５の電極とこれに対応す
るリード３の内端のワイヤ接続部１６．２０はワイヤ１
７で電気的に接続される。Such a lead frame 4 has a chip 15 on the tab 11.
is connected. Further, the electrode of the chip 15 and the corresponding wire connection portion 16.20 of the inner end of the lead 3 are connected to the wire 1.
7 to be electrically connected.
つぎに、第６図で示すように、フレーム枠７，８および
ダム１４，１９によって取り囲まれる領域がレジンモー
ルドによるレジンパッケージ２によって被われる。その
後、不要となるリードフレーム部分は切断除去され、レ
ジンパッケージ２から突出するリード部分は成形されて
第１図〜第３図で示されるような半導体装置が製造され
る。Next, as shown in FIG. 6, the area surrounded by the frames 7, 8 and the dams 14, 19 is covered with a resin package 2 made of resin mold. Thereafter, the unnecessary lead frame portions are cut and removed, and the lead portions protruding from the resin package 2 are molded to produce a semiconductor device as shown in FIGS. 1 to 3.
（１）、本発明はレジンパッケージの内外に亘ってリー
ドが千鳥状に２段に配列されているため、半導体装置の
小型化が達成できる。(1) In the present invention, since the leads are arranged in two stages in a staggered manner both inside and outside the resin package, it is possible to achieve miniaturization of the semiconductor device.
（２）、本発明はリードフレームのリードはレジンモー
ルドされるインナーリード部分およびレジンモールドさ
れないアウターリード部分はともに千鳥状に２段となる
ように配列されている。この結果、レジンモールド領域
は大型化せず、大型化に伴なうレジンモールド時のレジ
ン流入状態の悪化が防とでき、たとえば、レジンパッケ
ージ内のボイド（気泡）の発生が低減でき、耐湿性の向
上が図れる。(2) In the present invention, the leads of the lead frame are arranged in two stages in a staggered manner, including an inner lead portion that is resin-molded and an outer lead portion that is not resin-molded. As a result, the resin mold area does not become large, and deterioration of the resin inflow condition during resin molding due to the increase in size can be prevented.For example, the generation of voids (bubbles) in the resin package can be reduced, and moisture resistance can be improved. can be improved.
（３）、本発明は組立加工設備の点から考えれば、リー
ド数の増大が図られてもリードフレームは大晦の大型化
とはならない。この結果１組立加工設備は大型化せず設
備費を安くできる。(3) Considering the present invention from the point of view of assembly processing equipment, even if the number of leads is increased, the lead frame will not become large on New Year's Eve. As a result, the equipment cost can be reduced without increasing the size of the single assembly processing equipment.
（４）、また、同様にリードフレームはリード数増大に
よつ又も大型とはなり難いことから取り扱いも容易で作
業性も萬くなる。(4) Similarly, the lead frame is easy to handle and workability is improved because it is difficult to increase the size even when the number of leads increases.
（５）、上記（１）〜（４）により、小型で品質が優れ
た半導体装置！安価に提供することができるという相乗
効果が得られる。(5) Due to (1) to (4) above, the semiconductor device is small and has excellent quality! A synergistic effect can be obtained in that it can be provided at a low price.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。たとえば、前記実施例
ではリード内端部を同一平面に揃えるために、両方の副
リードフレームのリードを折り曲げたが、これはどちら
か−万のみを折り曲げる構造としてもよい。第７図はタ
ブ有り副リードフレーム５はリード３ｙ！−折り曲げず
、タブ無し副リードフレーム６のリード３を折り曲げた
例を示す。この構造でも前記実施例と同様な効果が得ら
れる。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the embodiment described above, the leads of both sub-lead frames were bent in order to align the inner ends of the leads on the same plane, but this may be structured so that only one of the leads is bent. In FIG. 7, the sub lead frame 5 with tab has a lead 3y! - An example is shown in which the leads 3 of the sub-lead frame 6 without tabs are bent without being bent. Even with this structure, the same effects as in the above embodiment can be obtained.
また、本発明は第８図（ａｔ、 （ｂｌに示すように、
レジンパッケージ２の４側面からり−ド３を突出させた
半導体装置１、あるいは第１０図（ａｌｔ （ｂ）に示
すように、プーアルインライン構造の半導体装置１にも
同様に適用でき前記実施例と同様な効果が得られる。特
に４側面からり一部３を突出する半導体装置１の場合に
は、レジンパッケージ２は面積的な小型化が図れるので
小型化の効果は大きい。In addition, the present invention is as shown in FIG. 8 (at, (bl),
It can be similarly applied to the semiconductor device 1 in which the resin package 2 has the resin package 2 protruding from its four sides, or to the semiconductor device 1 having a pull-in-line structure as shown in FIG. 10 (alt (b)). A similar effect can be obtained.Particularly in the case of the semiconductor device 1 in which the portion 3 protrudes from the four side surfaces, the resin package 2 can be made smaller in area, so that the effect of miniaturization is large.
なお、第９図（ａｌｌ （ｂｌは第８図（ａｔｅ （ｂ
）に示す半導体装置１の組立に用いる副リードフレーム
５，６であるが、リード３が４方向からタブ１１に向か
って延在する点だけが第６図で示すリードフレーム４と
異なるだけで他は同じであることからその説明は省略す
る。In addition, Figure 9 (all (bl) is Figure 8 (ate (b
) The sub lead frames 5 and 6 used for assembling the semiconductor device 1 shown in FIG. 6 differ from the lead frame 4 shown in FIG. Since they are the same, their explanation will be omitted.
以上の説明では主として本発明者によってなされた発明
ｔその背景となった利用分野であるレジンモールド型半
導体装置製造技術に適用した場合について説明したが、
それに限定されるものではなく、たとえば、パッケージ
から多数の棒体な突出するような物品の製造技術におい
ても、物品の小型化という面で適用できる。The above explanation has mainly been about the case where the invention made by the present inventor is applied to the resin mold type semiconductor device manufacturing technology, which is the field of application that is the background of the invention.
The present invention is not limited thereto, and can be applied, for example, to manufacturing techniques for articles in which a large number of rods protrude from a package in terms of miniaturization of the article.
また、セラミック封止型半導体装置、又は、ガラス封止
型半導体装置にも適用できる。Furthermore, the present invention can also be applied to ceramic-sealed semiconductor devices or glass-sealed semiconductor devices.
第４図は本発明の一実施例による半導体装置の正面図、
第２図は同じく平面図、
第３図は同じく側面図、
第４図（ａｌ、 （ｂ）は前記半導体装置の組立に用い
るリードフレームを構成する副リードフレームの平面図
。
第５図（ａｌｔ （ｂ）は同じく一部の断面図、第６図
は同じくリードフレームの要部を示ス斜視図。
第７図は他の実施例による半導体装置の模式図、ｇｓ図
（ａｌ、 （ｂ）は他の実施例による半導体装置の正面
図および平面図、
第９図（ａｌ、 （ｂ）は同じく副リードフレームの要
部を示す模式的平面図、
第１０図（ａｌ、 （ｂｌは他の実施例による半導体装
置の正面図および平面図である。
１・・・半導体装置、２・・・レジンパッケージ、３・
・・リード、４・・・リードフレーム、５，６・・・副
リードフレーム、７．８・・・フレーム枠、９ｔｔｏ・
・・接続部、１１・・・タブ、１２・・・タブ吊りリー
ド、１３・・・タイ１＜−１１４・・・ダム、１５・・
・半導体素子（チップ）、１６・・・ワイヤ接続部、１
７・・・ワイヤ、１８・・・タイバー、１９・・・ダム
、２０・・・ワイヤ接続部。
第 １ 図
第 ３ 図FIG. 4 is a front view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view, FIG. 3 is a side view, and FIG. 4 (al) and (b) are used for assembling the semiconductor device. A plan view of the sub-lead frame constituting the lead frame. FIG. 5 (alt (b)) is a partial sectional view, and FIG. 6 is a perspective view showing the main parts of the lead frame. A schematic diagram of a semiconductor device according to an embodiment, a gs diagram (al), (b) is a front view and a plan view of a semiconductor device according to another embodiment, and FIG. 10 (al, (bl) are a front view and a plan view of a semiconductor device according to another embodiment. 1...Semiconductor device, 2...Resin package, 3.
...Lead, 4...Lead frame, 5,6...Sub-lead frame, 7.8...Frame frame, 9tto...
...Connection part, 11...Tab, 12...Tab suspension lead, 13...Tie 1<-114...Dam, 15...
・Semiconductor element (chip), 16...Wire connection part, 1
7... Wire, 18... Tie bar, 19... Dam, 20... Wire connection part. Figure 1 Figure 3
Claims (1)
亘って延在する複数のリードと、を有する半導体装置で
あって、前記リードはパッケージの内外にあって千鳥状
に二段に配列されていることを特徴とする半導体装置。 ２、前記リードの内端部分は同一平面上に位置している
ことを特徴とする特許請求の範囲第１項記載の半導体装
置。 ３、半導体装置におけるパッケージの内外部に亘って延
在するリードフレームの一部に有するリードフレームで
あっズ、前記リードフレームは相互に重ね合されかつ一
体化された２枚の副リード７ｖ−ムからなり、各副リー
ドフレームのリードは他の副リードフレームのリード間
の上方あるいは下方に位置し、リードフレームのリード
としては千鳥状に二段に配列されていることを特徴とす
るリードフレーム。 ４、前記リードフレームのリードの内端部分は同一平面
上に位置していること！特徴とする特許請求の範囲第３
項記載のリードフレーム。[Claims] 1. A semiconductor device having a package and a plurality of leads extending inside and outside the package, the leads being arranged in two stages in a staggered manner inside and outside the package. A semiconductor device characterized by being arranged in. 2. The semiconductor device according to claim 1, wherein inner end portions of the leads are located on the same plane. 3. A lead frame included in a part of a lead frame extending both inside and outside of a package in a semiconductor device. The leads of each sub-lead frame are located above or below the leads of other sub-lead frames, and the leads of the lead frame are arranged in two stages in a staggered manner. 4. The inner end portions of the leads of the lead frame must be located on the same plane! Characteristic Claim No. 3
Lead frame as described in section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58210810A JPS60103652A (en) | 1983-11-11 | 1983-11-11 | Semiconductor device and lead frame used therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58210810A JPS60103652A (en) | 1983-11-11 | 1983-11-11 | Semiconductor device and lead frame used therefor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60103652A true JPS60103652A (en) | 1985-06-07 |
Family
ID=16595503
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58210810A Pending JPS60103652A (en) | 1983-11-11 | 1983-11-11 | Semiconductor device and lead frame used therefor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60103652A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63137463A (en) * | 1986-11-28 | 1988-06-09 | Fujitsu Ltd | Semiconductor device |
| JPH01205456A (en) * | 1988-02-10 | 1989-08-17 | Nec Corp | Multi-pin case for lsi |
| US5023700A (en) * | 1988-06-17 | 1991-06-11 | Ngk Insulators, Ltd. | Minutely patterned structure |
| US5105261A (en) * | 1989-03-30 | 1992-04-14 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device package having particular lead structure for mounting multiple circuit boards |
| US5675884A (en) * | 1991-01-04 | 1997-10-14 | International Business Machines Corporation | Apparatus for multilayer conductor chip packaging |
-
1983
- 1983-11-11 JP JP58210810A patent/JPS60103652A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63137463A (en) * | 1986-11-28 | 1988-06-09 | Fujitsu Ltd | Semiconductor device |
| JPH01205456A (en) * | 1988-02-10 | 1989-08-17 | Nec Corp | Multi-pin case for lsi |
| US5023700A (en) * | 1988-06-17 | 1991-06-11 | Ngk Insulators, Ltd. | Minutely patterned structure |
| US5100498A (en) * | 1988-06-17 | 1992-03-31 | Ngk Insulators, Ltd. | Method of producing a minutely patterned structure |
| US5105261A (en) * | 1989-03-30 | 1992-04-14 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device package having particular lead structure for mounting multiple circuit boards |
| US5675884A (en) * | 1991-01-04 | 1997-10-14 | International Business Machines Corporation | Apparatus for multilayer conductor chip packaging |
| US5734196A (en) * | 1991-01-04 | 1998-03-31 | International Business Machines Corporation | Electronic packaging shaped beam lead fabrication |
| US5768770A (en) * | 1991-01-04 | 1998-06-23 | Horton; Raymond Robert | Electronic packaging shaped beam lead fabrication |
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