JPH05243467A - Lead frame of semiconductor device - Google Patents
Lead frame of semiconductor deviceInfo
- Publication number
- JPH05243467A JPH05243467A JP9898592A JP9898592A JPH05243467A JP H05243467 A JPH05243467 A JP H05243467A JP 9898592 A JP9898592 A JP 9898592A JP 9898592 A JP9898592 A JP 9898592A JP H05243467 A JPH05243467 A JP H05243467A
- Authority
- JP
- Japan
- Prior art keywords
- leads
- semiconductor device
- package
- lead frame
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置のリードの形
状に改良を施したリードフレームに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame having an improved lead shape of a semiconductor device.
【０００２】[0002]
【従来の技術】図４は従来の半導体装置のパッケージの
外形の一例を示す斜視図である。従来の半導体装置のパ
ッケージ１２の側面に有するリードフレームは一列にリ
ード２１が配列された構造となっている。2. Description of the Related Art FIG. 4 is a perspective view showing an example of the outer shape of a conventional semiconductor device package. The lead frame provided on the side surface of the package 12 of the conventional semiconductor device has a structure in which the leads 21 are arranged in a line.
【０００３】[0003]
【発明が解決しようとする課題】従来の半導体装置のリ
ードフレームはこのようにリード部が一例に並んでいる
ので、半導体装置の機能が増加し、多数のリードが必要
になった場合、同じ大きさのパッケージではリードの間
隔を狭くし、リード数を増加させなければならなかっ
た。このとき、リードの間隔を狭くしすぎると、リーク
やショートが発生するため、リードの数が制限される。
したがって、さらにリードの数を増加させるためにはパ
ッケージの形状を大きくする必要があった。本発明の目
的は半導体装置の機能の増加に伴いパッケージの形状を
大きくすることなくリードの数を増加させることができ
る半導体装置のリードフレームを提供することにある。In the lead frame of the conventional semiconductor device, the lead portions are arranged in this way as an example. Therefore, when the function of the semiconductor device is increased and a large number of leads are required, the same size is obtained. In this package, it was necessary to reduce the lead spacing and increase the number of leads. At this time, if the lead interval is too narrow, a leak or a short circuit occurs, so that the number of leads is limited.
Therefore, in order to further increase the number of leads, it is necessary to increase the size of the package. An object of the present invention is to provide a lead frame of a semiconductor device which can increase the number of leads without increasing the shape of the package as the function of the semiconductor device increases.
【０００４】[0004]
【課題を解決するための手段】前記目的を達成するため
に本発明による半導体装置のリードフレームは半導体素
子を封止したパッケージの側面に多数設けられた半導体
装置のリードフレームにおいて、前記パッケージの側面
に沿ってリードを側面の上下に互い違いになるように２
列に配列し、下の列のリードを上の列のリードよりパッ
ケージよりに曲げて下の列のリード群と上の列のリード
群の先端が接触しないように構成してある。In order to achieve the above-mentioned object, a lead frame of a semiconductor device according to the present invention is a lead frame of a semiconductor device in which a large number of semiconductor devices are provided on a side surface of a package. Stagger the leads along the top and bottom of the side 2
They are arranged in rows, and the leads of the lower row are bent more than the leads of the upper row toward the package so that the tips of the leads of the lower row and the leads of the upper row do not come into contact with each other.
【０００５】[0005]
【作用】上記構成によれば、パッケージの形状を大きく
しなくても、リードの先端部を互い違いの位置で基板に
半田付けできるので、半導体装置の機能の増加に伴いリ
ードの数を増加させることができる。According to the above structure, the tip ends of the leads can be soldered to the substrate at the staggered positions without increasing the size of the package. Therefore, the number of leads can be increased as the function of the semiconductor device increases. You can
【０００６】[0006]
【実施例】以下、図面を参照して本発明をさらに詳しく
説明する。図１は本発明による半導体装置のリードフレ
ームの実施例を示す図で、パッケージの一部を示す斜視
図である。図２はその断面図，図３はその平面図であ
る。パッケージ２の側面２ａの上下に互い違いに２列に
リード１，５が配列されている。上側の列のリード１と
下側の列のリード５が接触しないように下側の列のリー
ド５を上側の列のリード１よりパッケージよりに曲げた
構造にしてある。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail below with reference to the drawings. FIG. 1 is a view showing an embodiment of a lead frame of a semiconductor device according to the present invention, and is a perspective view showing a part of a package. 2 is a sectional view thereof, and FIG. 3 is a plan view thereof. Leads 1 and 5 are alternately arranged in two rows above and below the side surface 2a of the package 2. The lead 5 of the lower row is bent more than the lead 1 of the upper row from the package so that the lead 1 of the upper row and the lead 5 of the lower row do not contact each other.
【０００７】また、半導体チップ３とリードに導線４を
接続する際、上側と下側の列の導線が接触したり、導線
に負荷がかからないようにパッケージ２内部でも下側リ
ードが上側リードより内側に配置されている。上部から
見ると下側の列のリードと上側の列のリードとは一部重
なった位置関係に配置されている。Also, when connecting the conductor wire 4 to the semiconductor chip 3 and the lead, the lower lead is inside the upper lead inside the package 2 so that the conductors in the upper and lower rows do not come into contact with each other or the conductor is not loaded. It is located in. When viewed from above, the leads in the lower row and the leads in the upper row are arranged in a partially overlapping positional relationship.
【０００８】[0008]
【発明の効果】以上、説明したように本発明はリードフ
レームのパッケージの側面の上下に互い違いに２列に配
列されているので、半導体装置の機能が増加し、リード
の数が増加させたい場合に同じ大きさのパッケージでリ
ード同士のリークやショートを発生させることなく、２
倍近くリード数を増設できるという効果がある。As described above, the present invention is arranged in two rows above and below the side surface of the package of the lead frame in a staggered manner, so that the function of the semiconductor device is increased and the number of leads is increased. 2 in the same size package without causing leakage between leads or short circuit
The effect is that the number of leads can be increased almost twice.
【図１】本発明による半導体装置のリードフレームの実
施例を示す外形図である。FIG. 1 is an outline view showing an embodiment of a lead frame of a semiconductor device according to the present invention.
【図２】図１の半導体装置のリードフレーム部分の断面
図である。2 is a cross-sectional view of a lead frame portion of the semiconductor device of FIG.
【図３】図１の半導体装置のリードフレーム部分の平面
図である。3 is a plan view of a lead frame portion of the semiconductor device of FIG.
【図４】従来の半導体装置のリードフレームの一例を示
す外形図である。FIG. 4 is an outline view showing an example of a lead frame of a conventional semiconductor device.
１…リード ２…パッケージ ３…半導体チップ ４…導線 1 ... Lead 2 ... Package 3 ... Semiconductor chip 4 ... Conductor wire
Claims (1)
に多数設けられた半導体装置のリードフレームにおい
て、 前記パッケージの側面に沿ってリードを側面の上下に互
い違いになるように２列に配列し、下の列のリードを上
の列のリードよりパッケージよりに曲げて下の列のリー
ド群と上の列のリード群の先端が接触しないように構成
したことを特徴とする半導体装置のリードフレーム。1. A lead frame of a semiconductor device, wherein a plurality of side surfaces of a package encapsulating a semiconductor element are provided on a side surface of the package. A lead frame for a semiconductor device, characterized in that the leads of the lower row are bent more toward the package than the leads of the upper row so that the tips of the leads of the lower row and the leads of the upper row do not come into contact with each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9898592A JPH05243467A (en) | 1992-02-28 | 1992-02-28 | Lead frame of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9898592A JPH05243467A (en) | 1992-02-28 | 1992-02-28 | Lead frame of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05243467A true JPH05243467A (en) | 1993-09-21 |
Family
ID=14234299
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9898592A Pending JPH05243467A (en) | 1992-02-28 | 1992-02-28 | Lead frame of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05243467A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0778930A (en) * | 1993-07-15 | 1995-03-20 | Nec Corp | Semiconductor device and its outer lead |
-
1992
- 1992-02-28 JP JP9898592A patent/JPH05243467A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0778930A (en) * | 1993-07-15 | 1995-03-20 | Nec Corp | Semiconductor device and its outer lead |
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