JPS62188333A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPS62188333A JPS62188333A JP61031162A JP3116286A JPS62188333A JP S62188333 A JPS62188333 A JP S62188333A JP 61031162 A JP61031162 A JP 61031162A JP 3116286 A JP3116286 A JP 3116286A JP S62188333 A JPS62188333 A JP S62188333A
- Authority
- JP
- Japan
- Prior art keywords
- bumps
- connection bumps
- rows
- lsi chip
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002265 prevention Effects 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 230000002093 peripheral effect Effects 0.000 abstract description 4
- 241001060350 Acalypha Species 0.000 abstract 1
- 238000010276 construction Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に関し、特に多端子を有する集積
回路チップ（以下、ＬＳＩチップという。）のバンプ構
造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a bump structure of an integrated circuit chip (hereinafter referred to as an LSI chip) having multiple terminals.
従来、この種のＬＳＩチップの電気検査並びに端子接続
は、ＬＳＩチップの周辺部に単列の接続用バンプを形成
し、絶縁フィルム上に形成された配線と前記接続バンプ
を接続する周知のＴＡＢ（Ｔａｐｅ Ａｕｔｏｍａｔｅ
ｄ Ｂｏｎｄｉｎｇ）技術によシ行なわれていた。Conventionally, electrical inspection and terminal connection of this type of LSI chip have been carried out by forming a single row of connection bumps on the periphery of the LSI chip, and using the well-known TAB ( Tape Automate
d Bonding) technology.
すなわち、第３図及び第４図に示す構造となりていた。That is, the structure was as shown in FIGS. 3 and 4.
上述のように、従来のＬＳＩチップの接続バンプは、Ｌ
ＳＩチップの周辺部の単列に形成されているために、多
くの入出力端子を必要とする半導体装置において、必要
入出力端子を形成することが困難となるという欠点があ
った。As mentioned above, the connection bumps of conventional LSI chips are
Since they are formed in a single row at the periphery of the SI chip, there is a drawback that it is difficult to form the necessary input/output terminals in a semiconductor device that requires many input/output terminals.
また、ＬＳＩチップの端部（接続バンプとＬＳＩチップ
エッヂ間）において電気的ショートを起こす欠点をも合
せ持っていた。It also has the disadvantage of causing an electrical short at the end of the LSI chip (between the connection bump and the LSI chip edge).
一実施例によシその欠点を以下に説明する。The disadvantages of one embodiment will be explained below.
第３図、第４図は、一実施例の断面図及び平面図である
。3 and 4 are a sectional view and a plan view of one embodiment.
ｌは、周辺部に単列の接続バンプを有するＬＳＩチップ
であり、３５ｍｍ幅の絶縁フィルム７に形成された金メ
ッキされた端子４が接続バンプ２に接続される。第３図
に示す如く、金メッキされた端子４は、ＬＳＩチップと
の接続部では絶縁フィルム７の支持がない片持ち梁の状
態になっている。1 is an LSI chip having a single row of connection bumps on the periphery, and gold-plated terminals 4 formed on an insulating film 7 with a width of 35 mm are connected to the connection bumps 2. As shown in FIG. 3, the gold-plated terminal 4 is in the form of a cantilever without the support of the insulating film 7 at the connection portion with the LSI chip.
従って多端子接続の為、端子ピッチを狭くすると端子幅
も狭くしなければならない。その為、端子強度が弱くな
シ、又、変形してＬＳＩチップの端部において電気的シ
ョートを起こし安くなる。一方、第４図に示す如く接続
バンプ２をＬＳＩチップ周辺部に単列に形成する為に多
くの入出力端子を必要とするＬＳＩチップにおいては、
接続バンプ２の間隔を狭くしなければならない。その為
、多くの入出力端子を必要とするＬＳＩチップにおいて
、必要な接続用バンプ間距離を確保し、かつ、多くの接
続バンプをＬＳＩチップの周辺部に単列に形成しようと
する場合には、ＬＳＩチップサイズが大きくなシ、歩留
シが低下し、原価も高くなる。Therefore, for multi-terminal connections, if the terminal pitch is narrowed, the terminal width must also be narrowed. Therefore, the terminal strength is weak, and it is also easy to deform and cause electrical shorts at the ends of the LSI chip. On the other hand, in an LSI chip that requires many input/output terminals in order to form connection bumps 2 in a single row around the periphery of the LSI chip, as shown in FIG.
The spacing between the connection bumps 2 must be narrowed. Therefore, in an LSI chip that requires many input/output terminals, if you want to secure the necessary distance between connection bumps and form many connection bumps in a single row around the periphery of the LSI chip, However, if the LSI chip size becomes large, the yield will decrease and the cost will increase.
本発明は、上述した従来技術の欠点を解決し、多くの入
出力接続バンプとショート防止バンプとを有する半導体
装置を提供することにある。SUMMARY OF THE INVENTION The present invention solves the above-mentioned drawbacks of the prior art and provides a semiconductor device having a large number of input/output connection bumps and short-circuit prevention bumps.
本発明は、表面上の４辺の周辺部の各辺にそれぞれ設け
られた２列の複数個の接続バンプと前記接続バンプの外
側に設けられた複数個のショート防止バンプから成る集
積回路チップと絶縁フィルム上に複数個の試験用電極と
配線パターンと入出力端子とが設けられたテープとから
成シ、接続バンプと入出力端子とが接続して成る半導体
装置において、２列のバンプが列方向で相互に重ならな
い位置で千鳥状に配置されている。The present invention provides an integrated circuit chip comprising a plurality of connection bumps in two rows provided on each side of the periphery of four sides on a surface, and a plurality of short-circuit prevention bumps provided on the outside of the connection bumps. In a semiconductor device consisting of a plurality of test electrodes, a wiring pattern, and a tape provided with input/output terminals on an insulating film, and in which connection bumps and input/output terminals are connected, two rows of bumps are arranged in a row. They are arranged in a staggered manner so that they do not overlap each other in the direction.
次に、本発明について図面を参照して詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.
第１図は、本発明に係る半導体装置の一実施例を示す断
面図であシ、第２図は、前記一実施例を示す平面図であ
る。FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a plan view showing the embodiment.
第１図及び第２図に示されるように本発明は、ＬＳＩチ
ップ１の表面の４辺の周辺部に周知のメッキ技術によシ
金メッキされた接続バンプ２と、ショート防止バンプ３
を形成されている。As shown in FIGS. 1 and 2, the present invention includes connection bumps 2 and short-circuit prevention bumps 3, which are gold-plated on the four sides of the surface of an LSI chip 1 using a well-known plating technique.
is formed.
接続バンプ２は、前記各辺の周辺部において、複数個の
第１列及び第２列から成るものでなければならずさらに
それぞれの列は列方向に相互に重ならないよう外位置で
千鳥状に配置形成されている。The connection bumps 2 must consist of a plurality of first and second rows in the peripheral portion of each side, and the respective rows are staggered at outer positions so that they do not overlap with each other in the row direction. The arrangement is formed.
一方、絶縁フィルム７のＬＳＩチップ収納部８を前もっ
て打ち抜き、その絶縁フィルム７上に銅箔を密着させて
、所定の複数個の千鳥状の入出力端子４と配線パターン
５と試験用電極６とを周知のエツチング技術と金メツキ
技術によシ形成されている。前記、２列に配置形成され
た複数個の接続バンプ２と複数個の入出力端子４を１対
１に位置合せし両者を周知の接続技術（例えば熱圧着）
によシ接続する。また、前記ショート防止バンプは、前
記接続バンプとチップエッヂ間において前記入出力端子
下に少なくとも１個が形成（本実施例では１個）されて
いる。このようにして多くの入出力端子を有する半導体
装置を実現する。On the other hand, the LSI chip accommodating portion 8 of the insulating film 7 is punched out in advance, copper foil is closely attached to the insulating film 7, and predetermined plurality of staggered input/output terminals 4, wiring patterns 5, and test electrodes 6 are formed. It is formed using well-known etching and gold plating techniques. The plurality of connection bumps 2 arranged and formed in two rows and the plurality of input/output terminals 4 are aligned one-to-one and connected by a well-known technique (for example, thermocompression bonding).
Connect to. Furthermore, at least one short-circuit prevention bump (one in this embodiment) is formed below the input/output terminal between the connection bump and the chip edge. In this way, a semiconductor device having many input/output terminals is realized.
以上説明したように本発明は、第１に、ＬＳＩチップの
４辺の周辺部に形成された複数個の第１列及び第２列か
ら成る接続バンプを列方向にそれぞれが重ならない位置
で千鳥状に配置する事により、多くの入出力端子を必要
とするＬＳＩチップが実現でき、第２に前記接続バンプ
とチップエッヂ間にショート防止バンプをチップ表面で
、かつ接続バンプに接続されているそれぞれの入出力端
子下に少なくとも１個形成する事によシ、入出力端子が
ＬＳＩチップと接触して電気的にシ目−卜する事を防止
できる効果がある。As explained above, the present invention firstly provides a staggered arrangement of connection bumps formed on the periphery of the four sides of an LSI chip, each consisting of a plurality of first rows and second rows, at positions that do not overlap in the row direction. By arranging them in a shape, it is possible to realize an LSI chip that requires many input/output terminals.Secondly, short-circuit prevention bumps are provided on the chip surface between the connection bumps and the chip edge, and each terminal connected to the connection bumps is By forming at least one under the input/output terminal of the LSI chip, it is possible to prevent the input/output terminal from coming into contact with the LSI chip and causing electrical damage.
第１図は本発明に係わる実施例の断面図、第２図はその
平面図である。第３図は、従来技術による実施例の断面
図、第４図はその平面図である。
１・・・・・・ＬＳＩチップ、２・・間接続バンプ、３
・・・・・・ショート防止バンプ、４・・量大出力端子
、５・・・・・・配線パターン、６・・・・・・試験用
電極、７・・曲絶縁フィルム、８・・・・・・ＬＳＩチ
ップ収納部。FIG. 1 is a sectional view of an embodiment according to the present invention, and FIG. 2 is a plan view thereof. FIG. 3 is a sectional view of an embodiment according to the prior art, and FIG. 4 is a plan view thereof. 1... LSI chip, 2... connection bump, 3
... Short-circuit prevention bump, 4 ... Large output terminal, 5 ... Wiring pattern, 6 ... Test electrode, 7 ... Curved insulation film, 8 ... ...LSI chip storage section.
Claims (1)
列の複数個の接続バンプと前記接続バンプの外側に設け
られた複数個のシヨート防止バンプから成る集積回路チ
ップと、絶縁フィル上に複数個の試験用電極と配線パタ
ーンと入出力端子とが設けられたテープとから成り前記
接続バンプと入出力端子とが接続されて成る半導体装置
において、２列の接続バンプが列方向で相互に重ならな
い位置で千鳥状に配置されていることを特徴とする集積
回路装置。2 provided on each side of the periphery of the four sides on the surface.
An integrated circuit chip comprising a plurality of connection bumps in a column and a plurality of shot prevention bumps provided outside the connection bumps, and a plurality of test electrodes, wiring patterns, and input/output terminals provided on an insulating film. The semiconductor device is characterized in that the two rows of connection bumps are arranged in a staggered manner at positions that do not overlap each other in the column direction. Integrated circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61031162A JPS62188333A (en) | 1986-02-14 | 1986-02-14 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61031162A JPS62188333A (en) | 1986-02-14 | 1986-02-14 | Integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62188333A true JPS62188333A (en) | 1987-08-17 |
Family
ID=12323743
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61031162A Pending JPS62188333A (en) | 1986-02-14 | 1986-02-14 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62188333A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5117275A (en) * | 1990-10-24 | 1992-05-26 | International Business Machines Corporation | Electronic substrate multiple location conductor attachment technology |
| US5229328A (en) * | 1990-10-24 | 1993-07-20 | International Business Machines Corporation | Method for bonding dielectric mounted conductors to semiconductor chip contact pads |
| US5233221A (en) * | 1990-10-24 | 1993-08-03 | International Business Machines Corporation | Electronic substrate multiple location conductor attachment technology |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53123074A (en) * | 1977-04-01 | 1978-10-27 | Nec Corp | Semiconductor device |
| JPS5512791A (en) * | 1978-07-14 | 1980-01-29 | Nec Corp | Semiconductor device |
-
1986
- 1986-02-14 JP JP61031162A patent/JPS62188333A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53123074A (en) * | 1977-04-01 | 1978-10-27 | Nec Corp | Semiconductor device |
| JPS5512791A (en) * | 1978-07-14 | 1980-01-29 | Nec Corp | Semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5117275A (en) * | 1990-10-24 | 1992-05-26 | International Business Machines Corporation | Electronic substrate multiple location conductor attachment technology |
| US5229328A (en) * | 1990-10-24 | 1993-07-20 | International Business Machines Corporation | Method for bonding dielectric mounted conductors to semiconductor chip contact pads |
| US5233221A (en) * | 1990-10-24 | 1993-08-03 | International Business Machines Corporation | Electronic substrate multiple location conductor attachment technology |
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