US20090091019A1 - Memory Packages Having Stair Step Interconnection Layers - Google Patents

Memory Packages Having Stair Step Interconnection Layers Download PDF

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Publication number
US20090091019A1
US20090091019A1 US12/335,372 US33537208A US2009091019A1 US 20090091019 A1 US20090091019 A1 US 20090091019A1 US 33537208 A US33537208 A US 33537208A US 2009091019 A1 US2009091019 A1 US 2009091019A1
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Prior art keywords
die
memory
electrical assembly
plurality
dielectric layer
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Abandoned
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US12/335,372
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Joseph Charles Fjelstad
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Samsung Electronics Co Ltd
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Joseph Charles Fjelstad
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Priority to US51994503P priority Critical
Priority to US10/987,187 priority patent/US7388279B2/en
Priority to US67686305P priority
Priority to US11/381,357 priority patent/US7466021B2/en
Application filed by Joseph Charles Fjelstad filed Critical Joseph Charles Fjelstad
Priority to US12/335,372 priority patent/US20090091019A1/en
Assigned to TECHNOLOGY PROPERTIES LIMITED LLC reassignment TECHNOLOGY PROPERTIES LIMITED LLC LICENSE (SEE DOCUMENT FOR DETAILS). Assignors: INTERCONNECT PORTFOLIO LLC
Publication of US20090091019A1 publication Critical patent/US20090091019A1/en
Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TECHNOLOGY PROPERTIES LIMITED
Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTELLASYS BEC LIMITED, INTERCONNECT PORTFOLIO, LLC, TECHNOLOGY PROPERTIES LIMITED
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    • G11C5/04Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
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    • H01L2924/1903Structure including wave guides
    • H01L2924/19038Structure including wave guides being a hybrid line type
    • H01L2924/19039Structure including wave guides being a hybrid line type impedance transition between different types of wave guides
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0183Dielectric layers
    • H05K2201/0191Dielectric layers wherein the thickness of the dielectric plays an important role
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09145Edge details
    • H05K2201/09154Bevelled, chamferred or tapered edge
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09727Varying width along a single conductor; Conductors or pads having different widths

Abstract

Disclosed are IC package structures having stair stepped layers and which have no plated vias. Such structures can be fabricated either as discrete packages or as strips such as might be beneficial in for use with memory devices wherein critical or high speed signals can be routed along the length of the multi-chip strip package without having to have the signals ascend and descend from the interconnection substrate on which the assembly is mounted to the IC package termination and back as the signal transmits between devices.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation of U.S. patent application Ser. No. 11/381,357 filed on May 2, 2006, which is a continuation-in-part of U.S. patent application Ser. No. 10/987,187, filed on Nov. 12, 2004, now U.S. Pat. No. 7,388,279, which claims the benefit of U.S. Provisional Application 60/519, 945 filed Nov. 12, 2003, and of U.S. Provisional Application 60/676,863, filed May 2, 2005, all of which are incorporated by reference in their entirety herein.
  • FIELD OF THE INVENTION
  • The present invention relates to the field of high speed electronic interconnections for memory and the packaging of semiconductor integrated circuits for use therewith.
  • BACKGROUND
  • Memory integrated circuits “ICs” for use with most computers operate at speeds slower than current generation central processing unit “CPU” ICs creating a condition generally referred to as the “memory bottleneck”. In such condition, the CPU must remain in a wait state until the memory data is written or retrieved. The problem has been addressed, in part, by improved memory system designs. However as electronic systems move into the multi-gigabit per second data rate range, a significant gap remains between top-end operating rates of CPU ICs and memory ICs. Part of this ongoing disparity is due to the limits of current interconnection design, which often results, particularly at higher frequencies, in disturbances that contribute to signal distortion. For example, signal distortion can often be due, at least in part to so-called parasitic effects resulting from traditional interconnect designs. Because signal speed and signal integrity are two primary goals in digital signal transmission, interconnect designs that assure signal integrity during data transmission are key. Controlling signal integrity begins with the design of the circuit. Choices made in terms of circuit layout, and the materials used and the general architecture of the complete assembly, will all have impact of the quality if the signal transmission and its ultimate integrity.
  • Because parasitic effects and signal discontinuity are primary sources of signal disturbance, one of the major objectives in maintaining signal integrity is to eliminate or minimize the parasitic effects and electrical discontinuities impinging upon a signal. Parasitic effects and electrical discontinuities are caused by a number of factors such as sharp changes in direction, changes in material, circuit feature flaws and even interconnections, such as solder balls used to connect IC packages to next level interconnection substrates. All these can affect signal integrity by introducing undesirable changes in impedance and creating signal reflections. There is also concern about signal skew, cause by differing signal lengths, which is important in assuring proper signal timing.
  • The first place in an electronic system such parasitic effects are encountered, beyond those encountered within the IC structure itself, is the IC package which is used to connect the IC die to a next level interconnection system. While current generation IC packages are presently reasonably well suited to meeting current needs, as the electronics industry moving to ever higher data signaling rates, the formerly minor concerns associated with packages and interconnection paths have now reached a level of critical importance.
  • The net effect of this complex web of interactive elements is that they collectively combine to make it extremely difficult to predict and design for reliable high performance at higher processing speeds. Additionally, at higher processing speeds, parasitic effects and signal discontinuities and reflections can contribute to the thermal demands placed on a system. Thus, as memory circuit speeds climb, there is need for new approaches to design of memory package interconnections to overcome the looming and highly complex electrical and thermal problems associated with traditional approaches to IC memory packaging.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention is best illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which
  • FIG. 1 shows an example of prior art;
  • FIG. 2 shows an example of prior art;
  • FIG. 3 shows an example of prior art;
  • FIG. 4 shows an example of prior art;
  • FIG. 5 shows an embodiment of a memory chip package assembly having a stair stepped interconnection layer;
  • FIG. 6 shows an exploded perspective view of an embodiment of a multi-chip memory package assembly having a stair stepped interconnection layer;
  • FIG. 7 show an embodiment of a multi-chip memory package assembly in assembled form with a plurality of discrete base materials having conductor patterns with I/O contacts which are each bonded to a common and shared base conductor pattern having its own separate I/O contacts;
  • FIG. 8 show an embodiment of a multi-chip memory package assembly in assembled form with a continuous base material and having disposed on it a plurality of conductor patterns bonded to (or built up additively in a sequential process) a base conductor pattern and having I/O contacts having a joining material attached;
  • FIG. 9 shows an embodiment of memory module with multi-chip memory packages assembled to the surface of the memory module;
  • FIG. 10 shows an IC die with center bond pads and having selected I/O terminations redistributed to second locations to provide secondary terminations;
  • FIG. 11 shows a perspective view of and embodiment of a portion of a strip package with an enlarged area to provide greater detail;
  • FIGS. 12 A and B disclose assembled, enlarged, and exploded views of an embodiment of a strip package having bridge circuits which cross the bonding apertures to create a multi drop connection path; and
  • FIG. 13 A-D show in cross section, partial views of various IC package strips embodiments having different interconnection pathways constructions to meet alternative interconnection path requirements.
  • DETAILED DESCRIPTION
  • Disclosed herein using descriptions and figures are IC package structures having stair step connections for use with memory devices and which improve control of the quality of an electronic signal that passes though a memory chip package and between memory chips. Moreover, the nature of the memory package assembly disclosed offers a structure better suited to thermal management than current package designs.
  • The embodiments disclosed herein address the limitations of current design and manufacturing practices employed in the fabrication of electronic memory device and system interconnections and the present inability of those design and manufacturing practices to address fully and adequately the needs for improved electronic signal integrity as the electronic signal transitions between memory chips on an electronic memory module.
  • An objective of the present disclosure to describe memory package structures which provide direct and uniform controlled impedance across the surface of a memory package by routing high speed signals on a controlled impedance first layer.
  • Another objective is to describe a first layer having one or more signal paths which provides a substantially skew free address line for clocking signals on the package while routing other signals, such as power and ground, on a second stair stepped layer wherein both metal layers are interconnected to the IC memory die.
  • It is yet another objective of the present disclosure to describe memory package structures which reduce the number of I/O required on the package due to the package structure's ability to transmit data directly between chips within the package.
  • It is yet another objective of the present disclosure to describe memory package structures which provide for improved thermal dissipation.
  • The present embodiments offer novel alternative approaches to addressing and meeting the stated objectives thus solving certain problems associated with current design approaches. Throughout this disclosure, many specific details are recited which are not essential to make or use the embodiments described herein. Accordingly, these details are offered for purposes of clarity and enablement, and are not intended to limit the spirit and scope of the embodiments described herein, which includes variations and equivalent structures and processes. For example, the IC die (IC chip) is shown in the attached drawings as having two central rows of bond pads. The depiction of this detail is not intended to limit the scope or application of IC chips described herein. Alternative embodiments such as those comprising a single row of bond pads, or more than two rows of bond pads are fully intended as falling within the scope of the embodiments described herein. The advantages are best illustrated with figures as show herewith, wherein:
  • FIG. 1 depicts an embodiment previously disclosed in U.S. patent application Ser. No. 10/964,578 (Publication 20050093152). A single chip IC package structure having stair stepped electrical interconnections on more than one level and interconnected by means of wires.
  • FIG. 2 depicts an embodiment of a previously disclosed IC package structure for interconnecting stacked memory packages having electrical interconnections on two surfaces and interconnected to a common IC contact by means of wires, which each connect to a different level and eliminating electrical stubs.
  • FIG. 3 depicts an embodiment disclosed in U.S. Pat. No. 7,014,472. A memory module has high speed interconnections traversing the module assembly and disposed for interconnections at the distal ends of the assembly. Traditional interconnection(s) are displayed on the bottom of the memory module for interconnection to a connector such as a PC board mounted DIMM connector.
  • FIG. 4 depicts an embodiment disclosed in U.S. patent application Ser. No. 10/987,187 in the form of a multi chip memory IC package structure in strip form wherein all of the interconnections are disposed on a common monolithic interconnection substrate in a single metal layer.
  • FIG. 5 discloses a perspective view of a stair step memory IC package assembly 500 comprising a first dielectric material layer 502 disposed on top of an IC die 501. A first set of conductors and their respective terminations 504 a are arranged along the exposed surface of the first dielectric layer 502. A second dielectric material layer 503 is disposed on top of the first dielectric layer. A second set of conductors and their respective terminations 504 b are arranged along the exposed surface of the second dielectric layer. The conductors 504 a and 504 b include a narrow end 504 c for connection to the IC die by means of interconnecting bond wires 506, and a flat circular region 504 d for electrically engaging contact members (not shown) of a next level interconnection substrate (not shown). The first elongated aperture 505 a is formed in dielectric material layer 502, and a second elongated aperture 505 b is formed in dielectric layer 503. The two apertures 505 a, 505 b are aligned above each other to form a center access area providing egress for the bond wires 506 that electrically couple the conductors 504 a, 504 b to their respective termination contacts 507 in the IC die 501. The outer periphery of the second (upper) aperture 505 b is slightly larger than the outer periphery of the first (lower) aperture 505 a. The enlarged outer periphery of aperture in 505 b serves to expose circuit wire bond terminations on 505 a for wire bonding (or other suitable joining method) which are proximate to the inner edge of the aperture on dielectric material layer 502. Bond wires 506 are used to interconnect the IC die terminations 507 to the circuit terminations 504 a and 504 b on dielectric layers 502 and 503 respectively. While the structure is shown with only two layers of conductors, it is not so limited and more layers may be used if needed or desired. Those familiar with the art of PCB and IC package manufacture will know that an additional protective dielectric insulating layer, such as a solder mask or cover layer or by means of a build up polymer layer, is commonly applied to circuits leaving only the termination I/O exposed. For clarity of description this layer is omitted.
  • FIG. 6 discloses an exploded perspective view of the elements of construction for an embodiment of multi-chip memory IC package assembly, including a plurality of IC die 501 positioned above an assembly support base structure (i.e. carrier) 602 which may be either permanent or temporary. In embodiments wherein the support base structure is temporary, the IC die 501 are removed from the support base 602 at some time after the first dielectric material layer 502 is bonded to the plurality of IC die 501. In embodiments wherein the support base structure 602 is a permanent part of the circuit, the IC die 501 are advantageously bonded to the carrier base.
  • The support base structure 602 has a plurality of cavities 603 having an appropriate size and shape for receiving respective IC die 501. According to an alternative embodiment, an individual die may be abutted directly against an adjacent die within a single cavity formed in the support base (carrier) structure 602, thereby eliminating the need for individual cavities 603 sized to securely receive a respective die. The die terminations 507 are arranged in dual lines along the center of each IC die (501). The dual-path alignment of die terminations 507 shown in FIG. 6 is offered only for example, and more or fewer paths are envisioned, as well as alternative shapes and alignments of die terminations, which can include, without limitation, alignments forming circular or elliptical shapes, spirals, star-shapes, and polygons.
  • A first dielectric layer 601 has a plurality of apertures 604 (analogous to 505 a), each aperture forming an elongated linear shape configured to provide access to the dual line formation of the die terminations 507 formed on an upper surface of a respective die 501. The apertures, however, may be formed in any shape which will allow for exposure of and access to the die terminations 507. Conductors 605 disposed on the upper surface of the first dielectric layer include narrow conductive trace portions 606 b that either terminate at large circular surface region 606 a (analogous to 504 d of FIG. 5), or at the edge of a respective aperture 604 formed in the first dielectric layer. Some of the conductors 605 do not have either end terminating at a large circular surface region 606 a, but remain narrow conductive trace portions 606 b having each end terminating at a different aperture, thereby functioning to connect adjacent IC die that are assembled within a common IC package. The distal ends of each of the narrow conductive trace portions 606 b are oriented around the outer periphery of a respective aperture 604 in a predetermined arrangement configured to optimize direct connection between a conductor 605 and its respective die termination 507. Wire bonds are used couple the circuit ends of respective conductive trace portions to wire bond pads on a respective IC die, as illustrated in various figures herein, including FIGS. 5, 11, 12A and 13A. The large circular portions 606 a can be used to accept solder balls (not shown) to facilitate interconnection of at least some of the conductors 605 as arranged on the surface of the first (lower) dielectric layer 601 for to a next level electronic element in the completed IC package assembly. It is not essential, however, that every conductor 605 is coupled to a signal source. Embodiments are envisioned wherein some of the conductors are unused. Similarly, it is not essential that every conductor 504 b of the second dielectric layer (discussed below) be coupled to a signal source.
  • A plurality of second dielectric (insulating base material) layers 503 have elongated apertures 505 b conforming to a shape and location of the arrays of die terminations 507. By making the die terminations accessible through the aligned upper and lower apertures 505 b, 604, conductive bond wires can be coupled to respective die terminations during fabrication. A second plurality of electrical conductors 504 b are arranged on the surface of the second dielectric layer in a predetermined arrangement to facilitate direct connection between a conductor 504 b and its respective die termination 507. The conductors 504 b on the plurality of second dielectric layers are also depicted as having a large circular surface region 504 d and a narrow conductive trace 504 c, as described in FIG. 5. The narrow conductive trace portions of these conductor are oriented around the outer periphery of a respective aperture 505 b in a predetermined arrangement to facilitate direct connection between a conductor 504 b and its respective die termination 507.
  • These upper dielectric layers 503 with circuits 504 b are shown as individual and discrete circuit structures which are bonded to the base circuit layer 601. According to a first alternative embodiment, a single contiguous dielectric upper layer is disposed atop the lower dialectic layer 601 and secured by appropriate means. According to another alternative embodiment, the upper dielectric layer 503 could be fabricated on the base layer 601 using a build up layer or similar process. Moreover, while the structure of FIG. 6 is shown with only two conductive layers (i.e., dielectric layers 601, 503 having conductors 605, 504 b disposed thereon), FIG. 6 is offered for illustrative purposes, and is not intended to limit the appended claims, which envision embodiments incorporating any number of conductive layers. By way of example, in another embodiment, the dielectric layer 601 may have a second metal layer on the side opposite the circuits 605. The second metal layer can function as a voltage source layer, a ground reference layer, or may provide additional circuit traces for select circuit connections other than ground, providing a micro-strip structure or sequence of signal traces that are configured to exhibit a desired impedance value, and/or trace lengths configured to equalize signal path lengths for select signals, thereby reducing or eliminating signal skew for select signals.
  • When the assembly is complete, it may be desirable to remove the support base by a suitable means to reduce the height of the completed assembly at which time an optional thin overmold (not shown) may be applied.
  • FIG. 7 depicts a perspective view of the elements illustrated and defined in FIG. 6 in an assembled embodiment 700. The IC die (not visible) or a plurality of IC dies are disposed within the support base structure (carrier) 602. As discussed in conjunction with FIG. 6, the respective die may be disposed in individual cavity members, or abutted against each other in a single cavity. The first (lower) dielectric (i.e. insulator) layer 701 is bonded to the top of the IC memory die 501 (not shown in FIG. 7, visible in FIG. 6), to the peripheral edges of the carrier 602, or to both the die and the carrier. In embodiments wherein the die 501 are not permanently disposed within the carrier 602, the first (lower) dielectric layer 701 is bonded to the die only, and not to the carrier. A plurality of second (upper) dielectric layers 702 are bonded to or otherwise disposed or built up on the top surface of the first dielectric layer 701. In all embodiments disclosed herein, circuits of a lower dielectric layer can be coupled to respective IC terminals by bond wire prior to, or subsequent to, the bonding of the next upper dielectric layer(s) to a lower dielectric layer. Spatial limitations and manufacturing processes will inform the fabrication process of the most advantageous order for performing these respective steps. After all bond wires 506 from the various dielectric layers have been connected to their respective IC terminals 507 (FIG. 5), the apertures (FIG. 5) are filled with a suitable encapsulant 703. I/O terminations such as solder balls 704 are visible around the peripheries of the dielectric layers may be attached to the large circular surface regions (504 c in FIG. 5).
  • FIG. 8 depicts a perspective view of an IC package having a single upper dielectric layer 801 coupled across the top of the lower dielectric layer 701. A plurality of IC die 501 (visible in FIG. 6) are disposed within carrier 602. A lower dielectric strip (i.e. interconnection substrate) 701 is disposed above and coupled or attached to the top of the IC memory die, the periphery of the carrier, or both. In embodiments wherein the die 501 are not permanently disposed within the carrier 602, the first (lower) dielectric layer 701 is bonded to the die only, and not to the carrier. A second (upper) contiguous dielectric strip 801 bonded to the top of the first dielectric strip 701. The apertures (not visible) of the upper and lower dielectric strips are aligned during fabrication. After the bond wires 506 have been connected to their respective IC terminals 507 (FIG. 5), the apertures are filled with a suitable encapsulant 703. I/O terminations such as solder balls 704 visible around the peripheries of the dielectric layers may be attached to the large circular surface regions (504 d in FIG. 5). In the embodiment depicted in FIG. 8, the second (upper) strip 801 is shown as being a formed from separate piece that is distinct from, and bonded, to the lower dielectric strip. However, alternative embodiments are envisioned wherein the upper dielectric strip is built up on the base circuit strip using build up layer circuit manufacturing techniques. The structure is shown with two circuit layers, each layer having separate conductive circuit pathways on insulating base materials. However, the specific number of dielectric layers shown in FIG. 8 is intended only as an example, and any number of dielectric layers may be used in conjunction with the embodiments described herein.
  • FIG. 9 depicts a side elevational view of the assembled multi chip memory packages 700 of FIG. 7 mounted on and interconnected to a memory module 900 such as a DIMM memory card. Centrally located on the module is an advanced memory buffer (AMB) package 901 which accesses and addresses the memory IC packages 700 by way of lateral signal paths 904, while power, ground and other signals for both the memory and AMB chip are accessed in traditional manner by way of conductors 903 connected to edge card terminations 902 on the memory module. The construction of the memory chip packages can be modified as desired to provide direct access to the AMB.
  • FIG. 10 shows an embodiment of a complementary cross-path IC die 1000 having parallel complementary inner and outer rows of bond pads on the upper surface of a modified IC die. Two parallel inner rows 1001 of bond pads are disposed between two parallel outer rows 1002 of bond pads 1002. A conductor path 1003 coupled to a bond pad from the left hand row of the inner rows 1001 extends to the right, passing between two bond pads of the right hand row of the inner rows 1001, and is coupled to a complementary bond pad on the right hand row of the outer rows 1002. A conductor path 1003 coupled to a respective bond pad from the right hand row of the inner rows 1001 extends to the left, passing between two IC terminals in the left hand row of the inner rows 1001, and is coupled to a complementary bond pad on the left hand row of the outer rows 1002. Conductor paths 1003 can be etched, bonded, or otherwise coupled to the surface of the IC die. Referring to FIGS. 6 and 10, when IC terminals of adjacent first and second IC die 507 are to be connected by means of narrow signal paths 606 b, 605 of FIG. 6, the complementary cross-path embodiment of FIG. 10 allows any IC terminal on a first IC die to be connected to any IC terminal on an adjacent IC die. This complementary cross-path structure is therefore useful in IC die utilizing parallel IC terminal arrays. The bond pads 1001, 1002 are coupled to the signal paths 606 b, 605 by a suitable means such as wire bonding. The signal path provided through this embodiment can exhibit a variety of advantageous design characteristics, such as fewer electrical stubs, or a more optimal signal path length, thereby reducing signal reflection, skew, and other deleterious signal phenomena.
  • FIG. 11 provides a perspective view and enlargement of a portion of a strip package embodiment 1100 having conductors 1101 disposed along the package edges to interconnect directly to an adjacent IC die or IC chip in the strip package (not shown). In the enlargement, noncontiguous conductive traces 1101 are electrically coupled by bond wires 1102 a and 1002 b to form a contiguous circuit path 1103 suitable for multi drop interconnection to adjoining ICs in the strip package.
  • FIGS. 12A and 12B respectively show an assembled top plan view and an exploded view of an embodiment of a portion of an IC package structure 1200. The package assembly includes a first or interior dielectric layer 1201 (the lower dielectric layer in FIG. 12B), which is disposed in the interior of the IC package structure between the IC die 501 and the second (upper) dielectric layer 503. The interior dielectric layer has a left edge 1209, a right edge 1210, and a plurality of apertures 1204 arranged in a line along the center portion of the first dielectric layer. Adjacent apertures 1204 are separated by a dielectric bridge 1203, formed from a continuous portion of the first dielectric layer extending across the center portion of the first dielectric layer. According to the linear arrangement of the apertures 1204 on the interior dielectric layer, for “n” apertures, there are therefore “n−1” dielectric bridges. Conductive paths 1202 extend laterally across the first dielectric layer from the left edge 1209 to the right edge 1210 allowing connection to adjacent ICs on either side (not shown). Electrical continuity from edge to edge is maintained because each of the conductive paths 1202 crosses one of the dielectric bridges 1203, thereby traversing the center section the first dielectric layer. Multiple separate conductive paths, however, can traverse across a single dielectric path. As discussed in conjunction with the enlarged view, the apertures 1204 between the dielectric bridges allow access to bond pads 507 on the IC die 501 and other connective members during fabrication of the IC package 1200.
  • A second (upper) dielectric layer 503 is disposed above the interior dielectric layer, and has a single aperture 504 b extending down the center portion of the layer 530. As discussed above, the shape and location of apertures on the respective layers is according to the location of the bond pads and circuit connection points on an IC die to which the various dielectric layers are coupled. The size of the apertures is sufficient to grant access to the bond pads and connection points during fabrication, according to the size of the tools used in fabrication. Circuit paths 504 b are disposed on the upper surface of the upper layer 503. The circuit paths include rounded planar surface areas 504 d for interconnection with a next level electronic element, and narrow trace sections 504 c extending to the periphery of the aperture 504 b and oriented in predetermined positions for interconnection with respective terminals on the IC die.
  • The enlarged view above FIG. 12 A provides greater detail of certain structures in FIGS. 12A and B. The wire bond termination 1204 on dielectric layer 1201. The larger aperture 505 b of dielectric layer 503 is identified by peripheral edges 1207 a 1207 b. The two bond wires 506 in the upper portion of the enlarged view form wire bond connections from select IC die bond pads 507 to respective circuit terminations 504 d on the upper dielectric layer 503. The two bond wires 506 in the lower portion of the enlarged view form wire bond connections from select IC die bond pads 507 to conductive circuit terminations 1202 a on the lower dielectric layer 1201. The surface of dielectric layer 1201 is seen extending across the aperture from the right peripheral edge 1208A to the left peripheral edge 1208B to form a dielectric bridge 1203, and circuits 1202 disposed on the surface of dielectric layer 1201 are seen on the dielectric bridge 1203, thereby allowing these circuit paths to traverse the aperture 1204.
  • Returning briefly to FIG. 12A, an encapsulant 703 is disposed within the cavity formed by the aligned apertures. It is shown open at the upper end to expose detail for enlargement. According to a preferred fabrication embodiment, the encapsulant 703 is not deposited in the center cavity until the interior dielectric layer 1201 has been bonded to the IC die 501, the second dielectric layer 503 has been bonded to the interior dielectric layer 1201, and all required bond wires have been secured to their respective terminals and connection points.
  • FIGS. 13 A-13D show in cross section, partial views of various IC die package strip embodiments having different interconnection pathway constructions to meet alternative interconnection path requirements. While the various embodiments are all illustrated with two metal layers (conductive paths disposed on one surface of each of two layered dielectric substrates), this specific number of layers is offered only for example, and embodiments can be utilized with any number of metal layers. For example, an additional conductive layer, disposed either on the top or bottom side of the IC die as oriented in FIGS. 13A-13D, could be used as a ground layer with transmission paths having a predetermined impedance, or a predetermined path length, and thereby configured to reduce signal reflection, signal skew, or counter other transmission effects that erode signal integrity.
  • In FIG. 13A, an IC die 1301 is depicted with two circuit layers disposed thereupon. The first layer comprises a first dielectric (insulating) layer 1302 with a bottom surface bonded to the IC die. Conductive paths 1303 a, 1303 b are etched, or otherwise disposed upon the top surface of the first layer dielectric layer 1302 a. The second layer comprises a second dielectric layer 1302 b having a bottom surface affixed to the top surface of the first layer, and conductive paths 1304 a, 1304 b formed on the upper surface of the second dielectric layer 1302 b. The cross sectional view discloses IC terminations 1306 disposed on the surface of the IC die 1301 within the apertures a and a′ and more clearly shows the inner edges of the first (lower) dielectric layer 1302 extending horizontally further toward the center of the aperture than the inner edges of the second (upper) dielectric layer 1302 b, thereby creating a tapered or stair-step effect around the cavity formed by apertures a and a′ A wire bond 1305 is used to connect from wire bond terminations 1306 on the IC 1301 to the conductors. Phantom bond wires 1307 are illustrated to represent bond wires connected to other bond pads and other connections on other layers. The assembly is shown with an encapsulant 1308 to protect the wire bonds after assembly.
  • Owing to the limitations of space in FIGS. 13A-13D, many elements that are known to those skilled in the art have been omitted from these Figures, including, but not limited to, protective insulation on conductive paths 1304 a and 1304 b, or solder balls or other joining material used to electrically couple the bond wires to specific conductive terminals. The omission of these, and other elements from various Figures described herein has been done to reduce visual clutter and enhance illustrative clarity. Accordingly, the omission of such well known structural elements from select Figures is not intended to limit the scope of the embodiments described herein, or of the appended claims.
  • FIG. 13B shows in a cross section view substantially the embodiment shown in FIG. 11 wherein a conductive path 1309 is interconnected to a first termination point (i.e. bond pad) 1307 on the IC chip 1301 and to a second termination point (e.g bond pad) 1310 completing a circuit across the IC die between wire bonds to first layer circuits 1303 a and 1303 b.
  • FIG. 13C shows in a cross section view what is substantially the embodiment shown in FIG. 12, wherein a conductive circuit pathway 1311 is continuous and bridges and traverses above the chip but is also interconnected to the native chip termination 1307 to provide a multi drop connection path.
  • FIG. 13 D shows in a cross section a view of an embodiment wherein redistribution circuits 1312 a and 1312 b are provided on the surface of the IC die 1301 and are interconnected to a first termination point (i.e. bond pad) 1307 on the IC die 1301 disposed beneath the redistribution circuits, and interconnected to circuit paths 1314 a and 1314 b above the redistribution circuits by second termination members 1313 a and 1313 b representing any suitable connection means, such as any of several flip chip bonding methods.
  • Restating here for emphasis, while the structures illustrated in this disclosure have shown with wire bonds being made to two rows of central bond pads on the IC die, the structures are not so limited and could also be used for created using a single bond pad in the center of the IC die or at the edges of the IC die or combinations thereof.
  • Although the invention has been described briefly with reference to specific exemplary embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. Moreover, many specific details have been included herein which are not essential to make and use every embodiment of the invention. These details have been included to assist the reader in more easily understanding and comprehending the embodiments described herein. Accordingly, the specification and drawings of this disclosure should be regarded in an illustrative rather than a restrictive sense.

Claims (38)

1-10. (canceled)
11. An electrical assembly comprising:
a first IC memory package with a first plurality of memory dies including a first memory die, each memory die having an active surface with a plurality of die terminals disposed thereon, the first memory die having a first die terminal in electrical continuity with first and second die bond-pads formed on the active surface.
12. The electrical assembly of claim 11 wherein a surface region of the first die terminal is coextensive with at least part of a surface region of the first die bond-pad.
13. The electrical assembly of claim 11 wherein the first die bond-pad and second die-bond pad are electrically coupled, at least in part, by a signal trace.
14. The electrical assembly of claim 13 wherein the signal trace is formed on the active surface of the first memory die.
15. The electrical assembly of claim 11, the first IC memory package further comprising:
a first dielectric layer with an active surface having a first plurality of circuit traces disposed thereupon, including a first circuit trace, the first plurality of circuit traces having first and second terminal ends; and,
a first bond wire with a first end coupled to the first circuit trace and a second end coupled with the first die bond-pad.
16. The electrical assembly of claim 15 further comprising a second wire bond coupling the second die bond-pad to a second circuit trace.
17. The electrical assembly of claim 16 wherein the first dielectric layer comprises a back surface coupled to the active surfaces of the first plurality of memory dies.
18. The electrical assembly of claim 17, wherein the first dielectric layer comprises a first plurality of apertures configured to expose at least some of the die bond-pads on the active surfaces of the first plurality of memory dies.
19. The electrical assembly of claim 18 further comprising a second dielectric layer with an active surface and a back surface, the active surface having a second plurality of circuit traces disposed thereupon, each of the second plurality of circuit traces having first and second ends, wherein the back surface of the second dielectric layer is coupled to the active surface of the first dielectric layer.
20. The electrical assembly of claim 19 wherein the second dielectric layer covers at least a portion of some of the first plurality of signal traces, the second dielectric layer comprising a second plurality of apertures configured in a stair step arrangement with at least some of the first plurality of apertures, and wherein the second plurality of apertures are configured to expose the first end of at least some of the first plurality of circuit traces.
21. The electrical assembly of claim 20 wherein the second plurality of circuit traces includes the second circuit trace.
22. The electrical assembly of claim 20 wherein the first plurality of circuit traces includes the second circuit trace.
23. The electrical assembly of claim 11, wherein the first plurality of memory dies are disposed on a first carrier.
24. The electrical assembly of claim 23 wherein the first carrier comprises a plurality of cavities, and wherein the first memory die is disposed in a first cavity, and the second memory die is disposed in a second cavity.
25. The electrical assembly of claim 23 wherein an edge of a first memory die in the first IC memory package abuts an edge of a second memory die in the first IC memory package.
26. The electrical assembly of claim 11 further comprising:
a printed circuit board wherein said first IC memory package is mounted on the printed circuit board;
a plurality of edge connector terminals disposed along at least one edge of the printed circuit board;
a second IC memory package mounted on the printed circuit board, wherein the first and second IC memory packages are electrically coupled to the edge connector terminals on the printed circuit board.
27. The electrical assembly of claim 26 further comprising:
an advanced memory buffer mounted on the printed circuit board and electrically coupled to the first and second IC memory packages.
28. An electrical assembly with a first IC memory package, the first IC memory package comprising:
a first memory die having an active surface with a plurality of die bond pads disposed thereon, including first and second die bond pads
a first dielectric layer having a back surface disposed against the active surface of the first memory die, and an active surface with a first plurality of circuit traces disposed thereon, including a first circuit trace with first and second terminal ends configured to couple with corresponding conductive members; and,
a first bond wire with a first end coupled to the first die bond pad and a second end coupled to a first section of the first circuit trace between the first and second terminal ends.
29. The electrical assembly of claim 28, wherein the first dielectric layer comprises a first aperture exposing the first die bond pad and a second aperture exposing the second die bond pad, the first and second apertures being separated by a first dielectric bridge, wherein the first circuit trace spans the first dielectric bridge.
30. The electrical assembly of claim 29, wherein the first memory die comprises two parallel rows of die bond pads, including a third die bond pad adjacent the first die bond pad and exposed by the first aperture, and a fourth die bond pad adjacent the second die bond pad and exposed by the second aperture.
31. The electrical assembly of claim 30, wherein the first plurality of circuit traces further comprises a second circuit trace with first and second terminal ends, the first IC memory package further comprising a second bond wire with a first end coupled with the fourth die bond pad and a second end coupled with a first section of the second circuit trace between the first and second terminal ends.
32. The electrical assembly of claim 31, wherein the second circuit trace spans the first dielectric bridge abreast the first circuit trace.
33. The electrical assembly of claim 32, wherein the first dielectric layer further comprises third and fourth apertures separated by a second dielectric bridge, the third and fourth apertures exposing respective third and fourth die bond pads disposed on the active surface of the second memory die.
34. The electrical assembly of claim 33, wherein the first circuit trace further spans the second dielectric bridge.
35. The electrical assembly of claim 34, the first IC memory package further comprising a second bond wire with a first end coupled to the first circuit trace, and a second end coupled to the third die bond pad.
36. The electrical assembly of claim 29, the first IC memory package further comprising:
a second dielectric layer with a back surface disposed against the active surface of the first dielectric layer, and an active surface that has a second plurality of conductive circuit traces disposed thereon, including a second circuit trace; and,
a second bond wire electrically coupled from the second die bond pad to the second circuit trace.
37. The electrical assembly of claim 36, wherein the second dielectric surface comprises a third aperture disposed above, and in stair step relationship with the first and second apertures.
38. The electrical assembly of claim 34, the first IC memory package further comprising a third memory die with an active surface having a plurality of die bond pads, including a fifth die bond pad electrically coupled to the first circuit trace by a wire bond.
39. The electrical assembly of claim 26 wherein the first circuit trace has a first end engaging a first conductive member of a next level electrical component, a second end engaging a second conductive member of a next level electrical component, and wherein the first bond wire is coupled to the first circuit trace between the first and second ends.
40. The electrical assembly of claim 39 wherein the first IC memory package is mounted on a memory card having edge connection terminals, the electrical assembly further comprising:
an advanced memory buffer mounted on the memory card and electrically coupled with the first IC memory package; and,
a second IC memory package mounted on the memory card and electrically coupled with the advanced memory buffer.
41. An electrical assembly with a first IC memory package, the first IC memory package comprising:
a plurality of memory dies including first and second memory dies, each memory die having an active surface that has at least three parallel rows of die bond pads, including first and second outer rows, and a third inner row disposed between the outer rows;
a first dielectric layer with an active surface that has a first plurality of circuit traces disposed thereon, including first and second circuit traces, wherein the active surface of the first dielectric layer faces the active surface of the first memory die, and wherein a first die bond terminal in the first outer row is coupled to the first circuit trace by a conductive bump, and a second die bond terminal in the second outer row is coupled to the second circuit trace by a second conductive bump.
42. The electrical assembly of claim 41 further comprising a second dielectric layer with a back surface coupled to the first dielectric layer, and an active surface with a second plurality of circuit traces disposed thereon, including a third signal trace.
43. The electrical assembly of claim 42 further comprising a bond wire with a first end coupled to a die bond pad in the third row of die bond pads, and a second end coupled to the third signal trace.
44. The electrical assembly of claim 41 wherein the plurality of memory dies are disposed on a carrier.
45. The electrical assembly of claim 44 wherein the carrier comprises a plurality of cavities, and wherein the first memory die is disposed in a first cavity, and the second memory die is disposed in a second cavity.
46. The electrical assembly of claim 44 wherein an edge of a first memory die in the first IC memory package abuts an edge of the second memory die in the first IC memory package.
47. The electrical assembly of claim 41 wherein the first IC memory package is mounted on a memory card having edge connection terminals, the electrical assembly further comprising:
an advanced memory buffer mounted on the memory card and electrically coupled with the first IC memory package; and,
a second IC memory package mounted on the memory card and electrically coupled with the advanced memory buffer.
US12/335,372 2003-11-12 2008-12-15 Memory Packages Having Stair Step Interconnection Layers Abandoned US20090091019A1 (en)

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US51994503P true 2003-11-17 2003-11-17
US10/987,187 US7388279B2 (en) 2003-11-12 2004-11-12 Tapered dielectric and conductor structures and applications thereof
US67686305P true 2005-05-02 2005-05-02
US11/381,357 US7466021B2 (en) 2003-11-17 2006-05-02 Memory packages having stair step interconnection layers
US12/335,372 US20090091019A1 (en) 2003-11-17 2008-12-15 Memory Packages Having Stair Step Interconnection Layers

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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100950511B1 (en) 2009-09-22 2010-03-30 테세라 리써치 엘엘씨 Microelectronic assembly with impedance controlled wirebond and conductive reference element
KR100935854B1 (en) 2009-09-22 2010-01-08 테세라 리써치 엘엘씨 Microelectronic assembly with impedance controlled wirebond and reference wirebond
US8786083B2 (en) 2010-09-16 2014-07-22 Tessera, Inc. Impedance controlled packages with metal sheet or 2-layer RDL
US9136197B2 (en) 2010-09-16 2015-09-15 Tessera, Inc. Impedence controlled packages with metal sheet or 2-layer RDL
US8222725B2 (en) 2010-09-16 2012-07-17 Tessera, Inc. Metal can impedance control structure
US8581377B2 (en) 2010-09-16 2013-11-12 Tessera, Inc. TSOP with impedance control
US8853708B2 (en) 2010-09-16 2014-10-07 Tessera, Inc. Stacked multi-die packages with impedance control
WO2012071325A1 (en) 2010-11-24 2012-05-31 Tessera, Inc. Lead structures with vertical offsets

Citations (88)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2825876A (en) * 1954-01-14 1958-03-04 Itt Radio frequency transducers
US2979676A (en) * 1957-10-30 1961-04-11 Research Corp Waveguide to microstrip transition structure
US4072902A (en) * 1975-06-30 1978-02-07 Epsilon Lambda Electronics Corp. Receiver module and mixer thereof
US4514751A (en) * 1982-12-23 1985-04-30 International Business Machines Corporation Compressively stresses titanium metallurgy for contacting passivated semiconductor devices
US4654692A (en) * 1983-06-30 1987-03-31 Kabushiki Kaisha Toshiba Semiconductor device of resin-seal type
US4745377A (en) * 1987-06-08 1988-05-17 The United States Of America As Represented By The Secretary Of The Army Microstrip to dielectric waveguide transition
US4806886A (en) * 1988-03-01 1989-02-21 The United States Of America As Represented By The Secretary Of The Army Microstrip resonance isolator
US4827211A (en) * 1987-01-30 1989-05-02 Cascade Microtech, Inc. Wafer probe
US4894612A (en) * 1987-08-13 1990-01-16 Hypres, Incorporated Soft probe for providing high speed on-wafer connections to a circuit
US4991001A (en) * 1988-03-31 1991-02-05 Kabushiki Kaisha Toshiba IC packing device with impedance adjusting insulative layer
US5008734A (en) * 1989-12-20 1991-04-16 National Semiconductor Corporation Stadium-stepped package for an integrated circuit with air dielectric
US5101261A (en) * 1988-09-09 1992-03-31 Texas Instruments Incorporated Electronic circuit device with electronomigration-resistant metal conductors
US5107231A (en) * 1989-05-25 1992-04-21 Epsilon Lambda Electronics Corp. Dielectric waveguide to TEM transmission line signal launcher
US5119048A (en) * 1990-11-05 1992-06-02 Grunwell Randall L Pseudo tapered lines using modified ground planes
US5177456A (en) * 1992-05-22 1993-01-05 The United States Of America As Represented By The Secretary Of The Army Microstrip ferrite circulator for substrate transitioning
US5200719A (en) * 1989-12-07 1993-04-06 Telecommunicacoes Brasileiras S/A Impedance-matching coupler
US5227232A (en) * 1991-01-23 1993-07-13 Lim Thiam B Conductive tape for semiconductor package, a lead frame without power buses for lead on chip package, and a semiconductor device with conductive tape power distribution
US5280168A (en) * 1991-11-25 1994-01-18 The United States Of America As Represented By The Secretary Of The Army Tapered radial transmission line for an optically activated hybrid pulser
US5289036A (en) * 1991-01-22 1994-02-22 Nec Corporation Resin sealed semiconductor integrated circuit
US5382831A (en) * 1992-12-14 1995-01-17 Digital Equipment Corporation Integrated circuit metal film interconnect having enhanced resistance to electromigration
US5412247A (en) * 1989-07-28 1995-05-02 The Charles Stark Draper Laboratory, Inc. Protection and packaging system for semiconductor devices
US5627408A (en) * 1994-05-19 1997-05-06 Kabushiki Kaisha Toshiba Wire bonding structure for semiconductor devices
US5661336A (en) * 1994-05-03 1997-08-26 Phelps, Jr.; Douglas Wallace Tape application platform and processes therefor
US5712510A (en) * 1995-08-04 1998-01-27 Advanced Micro Devices, Inc. Reduced electromigration interconnection line
US5739587A (en) * 1995-02-21 1998-04-14 Seiko Epson Corporation Semiconductor device having a multi-latered wiring structure
US5760476A (en) * 1994-08-01 1998-06-02 Motorola, Inc. Interconnect run between a first point and a second point in a semiconductor device for reducing electromigration failure
US5773856A (en) * 1994-10-14 1998-06-30 International Business Machines Corporation Structure for connecting to integrated circuitry
US5858815A (en) * 1996-06-21 1999-01-12 Anam Semiconductor Inc. Semiconductor package and method for fabricating the same
US6014586A (en) * 1995-11-20 2000-01-11 Pacesetter, Inc. Vertically integrated semiconductor package for an implantable medical device
US6023100A (en) * 1997-07-23 2000-02-08 Advanced Micro Devices, Inc. Metallization stack structure to improve electromigration resistance and keep low resistivity of ULSI interconnects
US6043556A (en) * 1997-02-27 2000-03-28 Kyocera Corporation High-frequency input/output feedthrough and package for housing high-frequency semiconductor element using same
US6049129A (en) * 1997-12-19 2000-04-11 Texas Instruments Incorporated Chip size integrated circuit package
JP2000138317A (en) * 1998-10-31 2000-05-16 Anam Semiconductor Inc Semiconductor device and its manufacture
US6081036A (en) * 1996-04-19 2000-06-27 Matsushita Electronics Corp. Semiconductor device
US6169326B1 (en) * 1996-05-16 2001-01-02 Hyundai Electronics Industries Co., Ltd. Metal wire of semiconductor device and method for forming the same
US6177723B1 (en) * 1997-04-10 2001-01-23 Texas Instruments Incorporated Integrated circuit package and flat plate molding process for integrated circuit package
US6191481B1 (en) * 1998-12-18 2001-02-20 Philips Electronics North America Corp. Electromigration impeding composite metallization lines and methods for making the same
US6198163B1 (en) * 1999-10-18 2001-03-06 Amkor Technology, Inc. Thin leadframe-type semiconductor package having heat sink with recess and exposed surface
US6198284B1 (en) * 1997-04-14 2001-03-06 Doty Scientific Inc. High power flexible leads for DAS NMR
US6207477B1 (en) * 1997-08-06 2001-03-27 Fujitsu Limited Semiconductor device having a ball grid array and a fabrication process thereof
US6211576B1 (en) * 1998-09-18 2001-04-03 Hitachi, Ltd. Semiconductor device
US6218731B1 (en) * 1999-05-21 2001-04-17 Siliconware Precision Industries Co., Ltd. Tiny ball grid array package
US6268650B1 (en) * 1999-05-25 2001-07-31 Micron Technology, Inc. Semiconductor device, ball grid array connection system, and method of making
US6300165B2 (en) * 1999-11-15 2001-10-09 Substrate Technologies Incorporated Ball grid substrate for lead-on-chip semiconductor package
US6346749B1 (en) * 1999-04-09 2002-02-12 Oki Electric Industry Co., Ltd. Semiconductor device
US20020017397A1 (en) * 2000-06-26 2002-02-14 Ramey Samuel C. Vialess printed circuit board
US6384694B1 (en) * 1998-10-22 2002-05-07 Murata Manufacturing Co., Ltd. Dielectric line converter, dielectric line unit, directional coupler, high-frequency circuit mobile, and transmitter-receiver
US6388269B1 (en) * 1999-03-25 2002-05-14 Nec Corporation Metal interconnection structure for evaluation on electromigration
US20020075093A1 (en) * 2000-12-14 2002-06-20 Intel Corporation Signal transmission unit
US6462274B1 (en) * 1998-10-31 2002-10-08 Amkor Technology, Inc. Chip-scale semiconductor package of the fan-out type and method of manufacturing such packages
US20020172024A1 (en) * 2001-05-21 2002-11-21 Hui Chong Chin Method for encapsulating intermediate conductive elements connecting a semiconductor die to a substrate and semiconductor devices so packaged
US6517656B1 (en) * 1999-10-05 2003-02-11 Amkor Technology, Inc. Method of making an integrated circuit package using a batch step for curing a die attachment film and a tool system for performing the method
US6518663B1 (en) * 1999-08-30 2003-02-11 Texas Instruments Incorporated Constant impedance routing for high performance integrated circuit packaging
US6522021B2 (en) * 2000-06-29 2003-02-18 Kabushiki Kaisha Toshiba Semiconductor device
US6525631B1 (en) * 2001-09-21 2003-02-25 Anritsu Company System and method for improved microstrip termination
US20030046647A1 (en) * 2001-09-05 2003-03-06 Fujitsu Limited Wiring designing method
US6548902B2 (en) * 2000-12-27 2003-04-15 Fujitsu Limited Semiconductor integrated circuit device, circuit design apparatus, and circuit design method
US6556099B2 (en) * 2001-01-25 2003-04-29 Motorola, Inc. Multilayered tapered transmission line, device and method for making the same
US20030092420A1 (en) * 2001-10-09 2003-05-15 Noriyasu Sugimoto Dielectric antenna for high frequency wireless communication apparatus
US20030091258A1 (en) * 2001-11-01 2003-05-15 Opnext Japan, Inc. Optical transmission device
US6566758B1 (en) * 2001-11-27 2003-05-20 Sun Microsystems, Inc. Current crowding reduction technique for flip chip package technology
US6677219B2 (en) * 1998-08-20 2004-01-13 Oki Electric Industry Co., Ltd. Method of forming a ball grid array package
US20040012458A1 (en) * 2002-07-19 2004-01-22 Amparan Alfonso Benjamin Device interconnects and methods of making the same
US20040021232A1 (en) * 2002-08-05 2004-02-05 Senol Pekin Flip-chip ball grid array package for electromigration testing
US20040108592A1 (en) * 2002-12-05 2004-06-10 Taiwan Semiconductor Manufacturing Company Slot design for metal interconnects
US20040114868A1 (en) * 2002-12-17 2004-06-17 Mcnc Impedance control devices for use in the transition regions of electromagnetic and optical circuitry and methods for using the same
US20040119150A1 (en) * 2002-12-19 2004-06-24 Lih-Tyng Hwang Multiple dice package
US20050017368A1 (en) * 2002-12-20 2005-01-27 Atila Mertol Multi-level redistribution layer traces for reducing current crowding in flipchip solder bumps
US20050017342A1 (en) * 2002-08-28 2005-01-27 Morrison Michael W. Ball grid array structures having tape-based circuitry
US20050058388A1 (en) * 2001-01-22 2005-03-17 Takehiko Nomura Silicon platform for optical modules
US6876085B1 (en) * 2001-09-24 2005-04-05 Nortel Networks Limited Signal layer interconnect using tapered traces
US20050093152A1 (en) * 2003-10-10 2005-05-05 Fjelstad Joseph C. Multi-surface contact IC packaging structures and assemblies
US20050098870A1 (en) * 2003-08-27 2005-05-12 Jochen Thomas FBGA arrangement
US20050099191A1 (en) * 2003-05-23 2005-05-12 Gleason K. R. Probe for testing a device under test
US6897563B2 (en) * 2001-12-28 2005-05-24 Sun Microsystems, Inc. Current crowding reduction technique using selective current injection
US6910874B2 (en) * 2000-08-21 2005-06-28 Micron Technology, Inc. Apparatus for encapsulating a multi-chip substrate array
US6995041B2 (en) * 2002-07-10 2006-02-07 Micron Technology, Inc. Semiconductor package with circuit side polymer layer and wafer level fabrication method
US7014472B2 (en) * 2003-01-13 2006-03-21 Siliconpipe, Inc. System for making high-speed connections to board-mounted modules
US7025617B2 (en) * 2002-05-10 2006-04-11 Molex Incorporated Edge card connector assembly with tuned impedance terminals
US7065721B2 (en) * 2003-07-28 2006-06-20 Lsi Logic Corporation Optimized bond out method for flip chip wafers
US7078823B2 (en) * 2003-04-09 2006-07-18 Micron Technology, Inc. Semiconductor die configured for use with interposer substrates having reinforced interconnect slots
US7193320B2 (en) * 2002-05-30 2007-03-20 Fujitsu Limited Semiconductor device having a heat spreader exposed from a seal resin
US7233160B2 (en) * 2000-12-04 2007-06-19 Cascade Microtech, Inc. Wafer probe
US7233064B2 (en) * 2004-03-10 2007-06-19 Micron Technology, Inc. Semiconductor BGA package having a segmented voltage plane and method of making
US7348865B2 (en) * 2003-03-07 2008-03-25 Ericsson Telecommunicacoes S.A. Impedance-matching coupler
US7388279B2 (en) * 2003-11-12 2008-06-17 Interconnect Portfolio, Llc Tapered dielectric and conductor structures and applications thereof
US7919363B2 (en) * 2003-10-23 2011-04-05 Infineon Technologies Ag Integrated circuit with additional mini-pads connected by an under-bump metallization and method for production thereof
US7948093B2 (en) * 2006-12-28 2011-05-24 Samgsung Electronics Co., Ltd. Memory IC package assembly having stair step metal layer and apertures

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6121679A (en) * 1998-03-10 2000-09-19 Luvara; John J. Structure for printed circuit design
EP2100267A4 (en) * 2006-11-28 2012-05-16 Calgary Scient Inc Texture-based multi-dimensional medical image registration

Patent Citations (110)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2825876A (en) * 1954-01-14 1958-03-04 Itt Radio frequency transducers
US2979676A (en) * 1957-10-30 1961-04-11 Research Corp Waveguide to microstrip transition structure
US4072902A (en) * 1975-06-30 1978-02-07 Epsilon Lambda Electronics Corp. Receiver module and mixer thereof
US4514751A (en) * 1982-12-23 1985-04-30 International Business Machines Corporation Compressively stresses titanium metallurgy for contacting passivated semiconductor devices
US4654692A (en) * 1983-06-30 1987-03-31 Kabushiki Kaisha Toshiba Semiconductor device of resin-seal type
US4827211A (en) * 1987-01-30 1989-05-02 Cascade Microtech, Inc. Wafer probe
US4745377A (en) * 1987-06-08 1988-05-17 The United States Of America As Represented By The Secretary Of The Army Microstrip to dielectric waveguide transition
US4894612A (en) * 1987-08-13 1990-01-16 Hypres, Incorporated Soft probe for providing high speed on-wafer connections to a circuit
US4806886A (en) * 1988-03-01 1989-02-21 The United States Of America As Represented By The Secretary Of The Army Microstrip resonance isolator
US4991001A (en) * 1988-03-31 1991-02-05 Kabushiki Kaisha Toshiba IC packing device with impedance adjusting insulative layer
US5101261A (en) * 1988-09-09 1992-03-31 Texas Instruments Incorporated Electronic circuit device with electronomigration-resistant metal conductors
US5107231A (en) * 1989-05-25 1992-04-21 Epsilon Lambda Electronics Corp. Dielectric waveguide to TEM transmission line signal launcher
US5412247A (en) * 1989-07-28 1995-05-02 The Charles Stark Draper Laboratory, Inc. Protection and packaging system for semiconductor devices
US5200719A (en) * 1989-12-07 1993-04-06 Telecommunicacoes Brasileiras S/A Impedance-matching coupler
US5008734A (en) * 1989-12-20 1991-04-16 National Semiconductor Corporation Stadium-stepped package for an integrated circuit with air dielectric
US5119048A (en) * 1990-11-05 1992-06-02 Grunwell Randall L Pseudo tapered lines using modified ground planes
US5289036A (en) * 1991-01-22 1994-02-22 Nec Corporation Resin sealed semiconductor integrated circuit
US5319241A (en) * 1991-01-23 1994-06-07 Texas Instruments Incorporated Lead frame without power buses for lead on chip package, and a semiconductor device with conductive tape power distribution
US5227232A (en) * 1991-01-23 1993-07-13 Lim Thiam B Conductive tape for semiconductor package, a lead frame without power buses for lead on chip package, and a semiconductor device with conductive tape power distribution
US5280168A (en) * 1991-11-25 1994-01-18 The United States Of America As Represented By The Secretary Of The Army Tapered radial transmission line for an optically activated hybrid pulser
US5177456A (en) * 1992-05-22 1993-01-05 The United States Of America As Represented By The Secretary Of The Army Microstrip ferrite circulator for substrate transitioning
US5382831A (en) * 1992-12-14 1995-01-17 Digital Equipment Corporation Integrated circuit metal film interconnect having enhanced resistance to electromigration
US5889320A (en) * 1994-05-03 1999-03-30 Phelps, Jr.; Douglas Wallace Tape application platform and processes therefor
US5661336A (en) * 1994-05-03 1997-08-26 Phelps, Jr.; Douglas Wallace Tape application platform and processes therefor
US5696032A (en) * 1994-05-03 1997-12-09 Phelps, Jr.; Douglas Wallace Tape application platform and processes therefor
US6043557A (en) * 1994-05-03 2000-03-28 Phelps, Jr.; Douglas Wallace Tape application platform and processes therefor
US5627408A (en) * 1994-05-19 1997-05-06 Kabushiki Kaisha Toshiba Wire bonding structure for semiconductor devices
US5760476A (en) * 1994-08-01 1998-06-02 Motorola, Inc. Interconnect run between a first point and a second point in a semiconductor device for reducing electromigration failure
US5773856A (en) * 1994-10-14 1998-06-30 International Business Machines Corporation Structure for connecting to integrated circuitry
US5739587A (en) * 1995-02-21 1998-04-14 Seiko Epson Corporation Semiconductor device having a multi-latered wiring structure
US5712510A (en) * 1995-08-04 1998-01-27 Advanced Micro Devices, Inc. Reduced electromigration interconnection line
US6014586A (en) * 1995-11-20 2000-01-11 Pacesetter, Inc. Vertically integrated semiconductor package for an implantable medical device
US6081036A (en) * 1996-04-19 2000-06-27 Matsushita Electronics Corp. Semiconductor device
US6169326B1 (en) * 1996-05-16 2001-01-02 Hyundai Electronics Industries Co., Ltd. Metal wire of semiconductor device and method for forming the same
US5858815A (en) * 1996-06-21 1999-01-12 Anam Semiconductor Inc. Semiconductor package and method for fabricating the same
US6043556A (en) * 1997-02-27 2000-03-28 Kyocera Corporation High-frequency input/output feedthrough and package for housing high-frequency semiconductor element using same
US6177723B1 (en) * 1997-04-10 2001-01-23 Texas Instruments Incorporated Integrated circuit package and flat plate molding process for integrated circuit package
US6198284B1 (en) * 1997-04-14 2001-03-06 Doty Scientific Inc. High power flexible leads for DAS NMR
US6023100A (en) * 1997-07-23 2000-02-08 Advanced Micro Devices, Inc. Metallization stack structure to improve electromigration resistance and keep low resistivity of ULSI interconnects
US6207477B1 (en) * 1997-08-06 2001-03-27 Fujitsu Limited Semiconductor device having a ball grid array and a fabrication process thereof
US20010001714A1 (en) * 1997-08-06 2001-05-24 Fujitsu Limited Semiconductor device having a ball grid array and a fabrication process thereof
US6049129A (en) * 1997-12-19 2000-04-11 Texas Instruments Incorporated Chip size integrated circuit package
US6677219B2 (en) * 1998-08-20 2004-01-13 Oki Electric Industry Co., Ltd. Method of forming a ball grid array package
US20040094833A1 (en) * 1998-08-20 2004-05-20 Kiyoshi Hasegawa Semiconductor package
US6211576B1 (en) * 1998-09-18 2001-04-03 Hitachi, Ltd. Semiconductor device
US20020047179A1 (en) * 1998-09-18 2002-04-25 Hiroya Shimizu Semiconductor device
US6384694B1 (en) * 1998-10-22 2002-05-07 Murata Manufacturing Co., Ltd. Dielectric line converter, dielectric line unit, directional coupler, high-frequency circuit mobile, and transmitter-receiver
US6489667B1 (en) * 1998-10-31 2002-12-03 Amkor Technology, Inc. Semiconductor device and method of manufacturing such device
US6462274B1 (en) * 1998-10-31 2002-10-08 Amkor Technology, Inc. Chip-scale semiconductor package of the fan-out type and method of manufacturing such packages
JP2000138317A (en) * 1998-10-31 2000-05-16 Anam Semiconductor Inc Semiconductor device and its manufacture
US6191481B1 (en) * 1998-12-18 2001-02-20 Philips Electronics North America Corp. Electromigration impeding composite metallization lines and methods for making the same
US6388269B1 (en) * 1999-03-25 2002-05-14 Nec Corporation Metal interconnection structure for evaluation on electromigration
US6677236B2 (en) * 1999-04-09 2004-01-13 Oki Electric Industry Co., Ltd. Semiconductor device fabrication method for interconnects that suppresses loss of interconnect metal
US6346749B1 (en) * 1999-04-09 2002-02-12 Oki Electric Industry Co., Ltd. Semiconductor device
US6218731B1 (en) * 1999-05-21 2001-04-17 Siliconware Precision Industries Co., Ltd. Tiny ball grid array package
US6268650B1 (en) * 1999-05-25 2001-07-31 Micron Technology, Inc. Semiconductor device, ball grid array connection system, and method of making
US6372552B1 (en) * 1999-05-25 2002-04-16 Micron Technology, Inc. Semiconductor device, ball grid array connection system, and method of making
US6518663B1 (en) * 1999-08-30 2003-02-11 Texas Instruments Incorporated Constant impedance routing for high performance integrated circuit packaging
US6517656B1 (en) * 1999-10-05 2003-02-11 Amkor Technology, Inc. Method of making an integrated circuit package using a batch step for curing a die attachment film and a tool system for performing the method
US6198163B1 (en) * 1999-10-18 2001-03-06 Amkor Technology, Inc. Thin leadframe-type semiconductor package having heat sink with recess and exposed surface
US20030132518A1 (en) * 1999-11-15 2003-07-17 Castro Abram M. Ball grid substrate for lead-on-chip semiconductor package
US6300165B2 (en) * 1999-11-15 2001-10-09 Substrate Technologies Incorporated Ball grid substrate for lead-on-chip semiconductor package
US20020017397A1 (en) * 2000-06-26 2002-02-14 Ramey Samuel C. Vialess printed circuit board
US6522021B2 (en) * 2000-06-29 2003-02-18 Kabushiki Kaisha Toshiba Semiconductor device
US6910874B2 (en) * 2000-08-21 2005-06-28 Micron Technology, Inc. Apparatus for encapsulating a multi-chip substrate array
US7233160B2 (en) * 2000-12-04 2007-06-19 Cascade Microtech, Inc. Wafer probe
US20020075093A1 (en) * 2000-12-14 2002-06-20 Intel Corporation Signal transmission unit
US6548902B2 (en) * 2000-12-27 2003-04-15 Fujitsu Limited Semiconductor integrated circuit device, circuit design apparatus, and circuit design method
US20050058388A1 (en) * 2001-01-22 2005-03-17 Takehiko Nomura Silicon platform for optical modules
US6556099B2 (en) * 2001-01-25 2003-04-29 Motorola, Inc. Multilayered tapered transmission line, device and method for making the same
US20020172024A1 (en) * 2001-05-21 2002-11-21 Hui Chong Chin Method for encapsulating intermediate conductive elements connecting a semiconductor die to a substrate and semiconductor devices so packaged
US6745378B2 (en) * 2001-09-05 2004-06-01 Fujitsu Limited Wiring designing method
US20030046647A1 (en) * 2001-09-05 2003-03-06 Fujitsu Limited Wiring designing method
US6525631B1 (en) * 2001-09-21 2003-02-25 Anritsu Company System and method for improved microstrip termination
US6876085B1 (en) * 2001-09-24 2005-04-05 Nortel Networks Limited Signal layer interconnect using tapered traces
US20030092420A1 (en) * 2001-10-09 2003-05-15 Noriyasu Sugimoto Dielectric antenna for high frequency wireless communication apparatus
US20030091258A1 (en) * 2001-11-01 2003-05-15 Opnext Japan, Inc. Optical transmission device
US6856709B2 (en) * 2001-11-01 2005-02-15 Opnext Japan, Inc. Optical modulation device
US6566758B1 (en) * 2001-11-27 2003-05-20 Sun Microsystems, Inc. Current crowding reduction technique for flip chip package technology
US20030098510A1 (en) * 2001-11-27 2003-05-29 Pradeep Trivedi Current crowding reduction technique for flip chip package technology
US6897563B2 (en) * 2001-12-28 2005-05-24 Sun Microsystems, Inc. Current crowding reduction technique using selective current injection
US7025617B2 (en) * 2002-05-10 2006-04-11 Molex Incorporated Edge card connector assembly with tuned impedance terminals
US7193320B2 (en) * 2002-05-30 2007-03-20 Fujitsu Limited Semiconductor device having a heat spreader exposed from a seal resin
US7479413B2 (en) * 2002-07-10 2009-01-20 Micron Technology, Inc. Method for fabricating semiconductor package with circuit side polymer layer
US6995041B2 (en) * 2002-07-10 2006-02-07 Micron Technology, Inc. Semiconductor package with circuit side polymer layer and wafer level fabrication method
US7537966B2 (en) * 2002-07-10 2009-05-26 Micron Technology, Inc. Method for fabricating board on chip (BOC) semiconductor package with circuit side polymer layer
US20040012458A1 (en) * 2002-07-19 2004-01-22 Amparan Alfonso Benjamin Device interconnects and methods of making the same
US6737931B2 (en) * 2002-07-19 2004-05-18 Agilent Technologies, Inc. Device interconnects and methods of making the same
US20040021232A1 (en) * 2002-08-05 2004-02-05 Senol Pekin Flip-chip ball grid array package for electromigration testing
US6700207B2 (en) * 2002-08-05 2004-03-02 Lsi Logic Corporation Flip-chip ball grid array package for electromigration testing
US20050017342A1 (en) * 2002-08-28 2005-01-27 Morrison Michael W. Ball grid array structures having tape-based circuitry
US7323772B2 (en) * 2002-08-28 2008-01-29 Micron Technology, Inc. Ball grid array structures and tape-based method of manufacturing same
US20040108592A1 (en) * 2002-12-05 2004-06-10 Taiwan Semiconductor Manufacturing Company Slot design for metal interconnects
US20040114868A1 (en) * 2002-12-17 2004-06-17 Mcnc Impedance control devices for use in the transition regions of electromagnetic and optical circuitry and methods for using the same
US20040119150A1 (en) * 2002-12-19 2004-06-24 Lih-Tyng Hwang Multiple dice package
US20050017368A1 (en) * 2002-12-20 2005-01-27 Atila Mertol Multi-level redistribution layer traces for reducing current crowding in flipchip solder bumps
US7014472B2 (en) * 2003-01-13 2006-03-21 Siliconpipe, Inc. System for making high-speed connections to board-mounted modules
US7348865B2 (en) * 2003-03-07 2008-03-25 Ericsson Telecommunicacoes S.A. Impedance-matching coupler
US7078823B2 (en) * 2003-04-09 2006-07-18 Micron Technology, Inc. Semiconductor die configured for use with interposer substrates having reinforced interconnect slots
US7102217B2 (en) * 2003-04-09 2006-09-05 Micron Technology, Inc. Interposer substrates with reinforced interconnect slots, and semiconductor die packages including same
US20050099191A1 (en) * 2003-05-23 2005-05-12 Gleason K. R. Probe for testing a device under test
US7065721B2 (en) * 2003-07-28 2006-06-20 Lsi Logic Corporation Optimized bond out method for flip chip wafers
US20050098870A1 (en) * 2003-08-27 2005-05-12 Jochen Thomas FBGA arrangement
US7023097B2 (en) * 2003-08-27 2006-04-04 Infineon Technologies Ag FBGA arrangement
US20050093152A1 (en) * 2003-10-10 2005-05-05 Fjelstad Joseph C. Multi-surface contact IC packaging structures and assemblies
US7919363B2 (en) * 2003-10-23 2011-04-05 Infineon Technologies Ag Integrated circuit with additional mini-pads connected by an under-bump metallization and method for production thereof
US20090027137A1 (en) * 2003-11-12 2009-01-29 Fjelstad Joseph C Tapered dielectric and conductor structures and applications thereof
US7388279B2 (en) * 2003-11-12 2008-06-17 Interconnect Portfolio, Llc Tapered dielectric and conductor structures and applications thereof
US7233064B2 (en) * 2004-03-10 2007-06-19 Micron Technology, Inc. Semiconductor BGA package having a segmented voltage plane and method of making
US7948093B2 (en) * 2006-12-28 2011-05-24 Samgsung Electronics Co., Ltd. Memory IC package assembly having stair step metal layer and apertures

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