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JPS6347961A - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JPS6347961A
JPS6347961A JP19310586A JP19310586A JPS6347961A JP S6347961 A JPS6347961 A JP S6347961A JP 19310586 A JP19310586 A JP 19310586A JP 19310586 A JP19310586 A JP 19310586A JP S6347961 A JPS6347961 A JP S6347961A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
package
semiconductor
surface
element
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19310586A
Inventor
Shin Nakao
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Abstract

PURPOSE: To be able to improve the packaging density of semiconductor elements without increasing the size of a whole semiconductor package as the conventional one by leading out input/output leads for electrically connecting the semiconductor element to the exterior of the package from the side surface of the package.
CONSTITUTION: Input/output leads 17 led from the side surface of a semiconductor package which contains a semiconductor element 9 and has input/output pins 8 on the rear surface for electrically connecting the element 9 to the exterior of the semiconductor package are provided on the semiconductor package. For example, a step 16 is formed on the side surface of the periphery of a package substrate 15, and a plurality of the leads 17 for electrically connecting the element 9 contained in the substrate 15 to the exterior of the substrate 15 are led from the step 16 at predetermined pitches. A bonding pad 6 is electrically connected to the pins 8 and the leads 17 by wirings 7 in the substrate 15.
COPYRIGHT: (C)1988,JPO&Japio
JP19310586A 1986-08-18 1986-08-18 Semiconductor package Pending JPS6347961A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19310586A JPS6347961A (en) 1986-08-18 1986-08-18 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19310586A JPS6347961A (en) 1986-08-18 1986-08-18 Semiconductor package

Publications (1)

Publication Number Publication Date
JPS6347961A true true JPS6347961A (en) 1988-02-29

Family

ID=16302324

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19310586A Pending JPS6347961A (en) 1986-08-18 1986-08-18 Semiconductor package

Country Status (1)

Country Link
JP (1) JPS6347961A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63234552A (en) * 1987-03-24 1988-09-29 Shinko Electric Ind Co Ltd Semiconductor package
US5107329A (en) * 1988-02-26 1992-04-21 Hitachi, Ltd. Pin-grid array semiconductor device
WO2004077560A1 (en) * 2003-02-26 2004-09-10 Ibiden Co., Ltd. Multilayer printed wiring board
JP2004265956A (en) * 2003-02-26 2004-09-24 Ibiden Co Ltd Multi-layer printed wiring board
JP2011095439A (en) * 2009-10-29 2011-05-12 Iwaki Engineer:Kk Edge light panel

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63234552A (en) * 1987-03-24 1988-09-29 Shinko Electric Ind Co Ltd Semiconductor package
US5107329A (en) * 1988-02-26 1992-04-21 Hitachi, Ltd. Pin-grid array semiconductor device
WO2004077560A1 (en) * 2003-02-26 2004-09-10 Ibiden Co., Ltd. Multilayer printed wiring board
JP2004265956A (en) * 2003-02-26 2004-09-24 Ibiden Co Ltd Multi-layer printed wiring board
JP4493923B2 (en) * 2003-02-26 2010-06-30 イビデン株式会社 Printed wiring board
US7894203B2 (en) 2003-02-26 2011-02-22 Ibiden Co., Ltd. Multilayer printed wiring board
JP2011095439A (en) * 2009-10-29 2011-05-12 Iwaki Engineer:Kk Edge light panel

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