JPS62249464A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPS62249464A JPS62249464A JP61092040A JP9204086A JPS62249464A JP S62249464 A JPS62249464 A JP S62249464A JP 61092040 A JP61092040 A JP 61092040A JP 9204086 A JP9204086 A JP 9204086A JP S62249464 A JPS62249464 A JP S62249464A
- Authority
- JP
- Japan
- Prior art keywords
- package
- outer leads
- leads
- mounting
- bent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000000034 method Methods 0.000 abstract description 6
- 239000000758 substrate Substances 0.000 abstract description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910003271 Ni-Fe Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
- H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体パッケージに関し、特にその外部接続端
子であるアクタ−リードにおいてパッケージのコーナ一
部にも当該リードを配設することカテキ、パッケージ実
装面積当りのアクタ−リード本数を増加させることがで
きる技術に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor package, and particularly relates to a semiconductor package in which an actor lead, which is an external connection terminal, is provided also in a part of the corner of the package. The present invention relates to a technique that can increase the number of actor leads per area.
半導体パッケージの一つにフラットパックタイプと称さ
れるパッケージ（以下、ＰＰＰと称する）がある。これ
は、一般に、四方向にアウターリードと称される端子（
ピン）を出したパッケージであって、プリント基板など
の実装基板に、その孔にアウターリードを挿入するので
はなく、当該基板の導体パターンに直接平面付けするタ
イプのパッケージであって、その実装面積が従来の同ピ
ン数のＤＩＰ（デュアル・インライン・パッケージ）に
比べて１／２でよいなどの利点を有する。One type of semiconductor package is a package called a flat pack type (hereinafter referred to as PPP). This generally has terminals called outer leads (
This is a type of package in which the outer leads are attached directly to the conductor pattern of the printed circuit board, rather than by inserting the outer leads into the holes of the mounting board such as a printed circuit board. It has the advantage that it is only 1/2 the size of a conventional DIP (dual in-line package) with the same number of pins.
しかし、このパッケージ構造にあっては、アウターリー
ドがパッケージ側面から突出されている。However, in this package structure, the outer leads protrude from the side of the package.
そこで、このアウターリードの端部なパッケージの裏面
に折曲げするタイプのパッケージが提案された。これに
よれば、アウターリードの端部がパッケージ裏面に折曲
げされているので、前記ＰＰＰよりも、端子数が同じで
も、実装面積が小さく済むという利点がある。なお、こ
のＰＬＣＣ（プラスチック・リードレス・チップ・ギヤ
１ノア）と称されるパッケージは、ノくノケージ裏面に
折曲げられたリード部をプリント基板などの実装基板に
ハンダ付けなどにより、ＰＰＰと同様に面実装する０
しかし、このように、ＰＬＣＣではアウター１ノードを
パッケージ裏面に折曲げするので、リード間の短絡やノ
・ンダ実装時のノ・ンダ間短絡を避けるために、パッケ
ージのコーナ一部においてアウターリードを配置しない
ように、コーナ一部に空きを設けるようにしている。そ
の為、かかる空きを設ける必要から端子数を増加させる
ことができないという難点がある。Therefore, a type of package was proposed in which the ends of the outer leads are bent on the back side of the package. According to this, since the ends of the outer leads are bent to the back surface of the package, there is an advantage that the mounting area is smaller than the above-mentioned PPP even if the number of terminals is the same. This package called PLCC (Plastic Leadless Chip Gear 1 Noah) is similar to PPP by soldering the bent leads on the back of the cage to a mounting board such as a printed circuit board. However, in PLCC, the outer 1 node is bent to the back of the package, so in order to avoid short circuits between leads and between nodes when mounting nodes, it is necessary to A space is provided at a part of the corner so that no outer lead is placed in the section. Therefore, there is a problem in that the number of terminals cannot be increased because of the need to provide such space.
なお、フラット／シックタイジノくツケージやチップキ
ャリアタイプパッケージについて述べた文献の例として
、■工業調査会１９８０年１月１５日発行ｒＩＣ化実装
技術ＪＰ１４０〜１４４がある。Incidentally, an example of a document describing a flat/thick package and a chip carrier type package is ``IC Industry Research Group'' published January 15, 1980, RIIC Mounting Technology JP 140-144.
〔発明が解決しようとする問題点〕
本発明は、コーナ部にもアウターリードを配置でき、パ
ッケージ実装面積当りのアウター１７− ）’の本数を
増加できる技術を提供することを目的とする。[Problems to be Solved by the Invention] An object of the present invention is to provide a technique that allows outer leads to be arranged even in corner portions and increases the number of outer leads 17-)' per package mounting area.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、本発明では、例えば、四辺から出たアウター
リードのうち、相対する二辺のアウターリードは従来の
ＰＬＣＣと同様にその一部がパッケージ裏面に折曲げら
れたアウターリードとし、他の相対する二辺のアウター
リードをパッケージ側面から垂直ＫＤＩＰ様に実装基板
の孔に挿入できる形の７ウターリードとして成る。That is, in the present invention, for example, among the outer leads protruding from the four sides, the outer leads on two opposing sides are partially bent to the back surface of the package as in the conventional PLCC, and the other outer leads are bent on the back side of the package. It consists of 7 outer leads that can be inserted from the side of the package into the holes of the mounting board in a vertical KDIP manner.
これにより一方のアクタ−リードはパッケージ裏面に折
曲げられていても、他方のアウターリードは同様にパッ
ケージ裏面に折曲げするようにしていないので、リード
間が接触することがなく、パッケージのコーナ一部にも
アウターリードを配設することができ、アウターリード
の本数を増加させることができる。As a result, even if one of the actor leads is bent to the back of the package, the other outer lead is not bent to the back of the package, so there is no contact between the leads and the corner of the package is aligned. Outer leads can also be provided in the outer leads, and the number of outer leads can be increased.
次に、本発明を、図面に示す実施例に基づいて説明する
。Next, the present invention will be explained based on embodiments shown in the drawings.
〔実施例１〕
第１図は本発明の一実施例を示す底面図、第２図は第１
図Ｉ−Ｉ線断面図、第３図は第１図■−■線断面図、第
４図は全体概観図である。[Embodiment 1] Fig. 1 is a bottom view showing one embodiment of the present invention, and Fig. 2 is a bottom view showing an embodiment of the present invention.
FIG. 3 is a sectional view taken along the line I--I in FIG. 1, FIG. 4 is a sectional view taken along the line ■--■ in FIG.
これら図に示すように、パッケージ１の二辺（上下）の
アウターリード２を、第２図断面で示すように、パッケ
ージ１の裏面Ｋまで折曲げし、ＰＬＣＣ様に構成する。As shown in these figures, the outer leads 2 on the two sides (top and bottom) of the package 1 are bent to the back surface K of the package 1, as shown in cross section in FIG. 2, to form a PLCC-like structure.
一方、パッケージ１の二辺（左右）のアウターリード３
をパッケージ１の側面から、ＤＩＬ様に構成する。すな
わち、アクタ−リード２は面実装可能に、他方のアウタ
ーリード３は実装基板の孔に挿入可能に構成する。On the other hand, outer leads 3 on two sides (left and right) of package 1
is configured like DIL from the side of package 1. That is, the actor lead 2 is configured so that it can be surface mounted, and the other outer lead 3 is configured so that it can be inserted into a hole in a mounting board.
〔実施例２〕
第５図は本発明の他の実施例を示し、第６図は第５図■
−■線断面図、第７図は第５図に示すパッケージの実装
基板への実装の説明図である。[Embodiment 2] FIG. 5 shows another embodiment of the present invention, and FIG.
7 is an explanatory diagram of mounting the package shown in FIG. 5 on a mounting board.
この実施例は、パッケージ１の上下二辺のアクタ−リー
ド２は実施例と同様に、パッケージ１の裏面まで折曲げ
しである。従って、その断面は第２図に示すものと同様
となる。一方、パッケージ１の左右二辺のアクタ−リー
ド４は、実施例１とは異なり、ＰＰＰと同様の面実装可
能な構成としである（第５図参照）。実装基板例えばプ
リント基板５への実装に際しては、パッケージ裏面にま
で折曲げられたアウターリード２の当該電極部を半田付
けなどの実装方法により、プリント基板５に実装し、一
方、アウターリード４を、プリント基板５にＰＰＰと同
様にして実装する。なお、第７図にて、６はプリント基
板５に設けられた導体パターンを示す。In this embodiment, the actor leads 2 on the upper and lower sides of the package 1 are bent to the back surface of the package 1, as in the embodiment. Therefore, its cross section will be similar to that shown in FIG. On the other hand, unlike the first embodiment, the actor leads 4 on the left and right sides of the package 1 have a structure that allows surface mounting similar to PPP (see FIG. 5). When mounting on a mounting board, for example, a printed circuit board 5, the electrode portion of the outer lead 2, which has been bent to the back surface of the package, is mounted on the printed circuit board 5 by a mounting method such as soldering, while the outer lead 4 is It is mounted on the printed circuit board 5 in the same manner as the PPP. In addition, in FIG. 7, 6 indicates a conductor pattern provided on the printed circuit board 5.
〔実施例３〕
第８図に示す実施例は、アウターリード７の主要部分を
、従来のＰＬＣＣがそのアウターリードの全てをバクケ
ージ裏面周縁において、直角方向に配設していたのを、
同図に示すように、中心に向って斜行方向に配設したも
ので、同図は当該ＰＬＣＣの底面を模式的に示したもの
である。[Embodiment 3] In the embodiment shown in FIG. 8, the main part of the outer lead 7 is arranged perpendicularly at the periphery of the back cage in the conventional PLCC.
As shown in the figure, they are arranged obliquely toward the center, and the figure schematically shows the bottom surface of the PLCC.
〔実施例４〕
第９図は本発明のさらに他の実施例を示し、パンケージ
１の四辺から引出されたアウターリード８の全てを、パ
ッケージ側面に対し垂直方向に配設したものである。Ｄ
ＩＬＰでは二方向からアウターリード８を引出し、実装
基板の孔に挿入する形式であるが、本発明の実施例は四
方向にアウターリードを同様の形態で引出している。一
方、ＰＰＰでは四辺が面実装する形式でアクタ−リード
を引出しているが、本発明の実施例では四方向のアウタ
ーリードの全てが実装基板の孔に挿入する形である。[Embodiment 4] FIG. 9 shows still another embodiment of the present invention, in which all the outer leads 8 drawn out from the four sides of the pan cage 1 are disposed perpendicularly to the side surface of the package. D
In the ILP, the outer leads 8 are pulled out from two directions and inserted into holes in the mounting board, but in the embodiment of the present invention, the outer leads 8 are pulled out in the same manner in four directions. On the other hand, in PPP, the actor leads are drawn out in a manner that they are surface mounted on all four sides, but in the embodiment of the present invention, all of the outer leads in four directions are inserted into holes in the mounting board.
以上本発明の実施例について各種の態様を説明したが、
これら実施例に示すパッケージは、従来のＰＬＣＣ，Ｆ
ＰＰ、ＤＩＰに準拠して製造することができる。例えば
、第４図に示すノくツケージは、当該アウターリード２
，３を有するリードフレームのタブ９上に半導体素子１
０を固着させ、コネクタワイヤ１１により、当該素子１
０のポンディングパッド（図示せず）とリードフレーム
とをワイヤボンディング後、トランスファーモールド法
などにより樹脂をモールドして、樹脂モールド部１２を
形成し、アウターリード２をパンケージ１の側壁および
裏面側に設けられた溝にお〜・て折曲げし、一方、アウ
ターリード３をＤＩＬＰで実施されている方法で第３図
に例示するように折曲げする主要工程を経て得ることが
できる。Various aspects of the embodiments of the present invention have been described above, but
The packages shown in these examples are conventional PLCC, F
It can be manufactured in accordance with PP and DIP. For example, the socket cage shown in FIG.
, 3 on the tab 9 of the lead frame.
0 is fixed, and the corresponding element 1 is connected by the connector wire 11.
0 bonding pad (not shown) and the lead frame are wire-bonded, resin is molded by transfer molding or the like to form the resin molded part 12, and the outer lead 2 is attached to the side wall and back side of the pan cage 1. It can be obtained through the main steps of bending the outer lead 3 in the provided groove, and then bending the outer lead 3 as illustrated in FIG. 3 by the method practiced in DILP.
当該リードフレームは例えばＮｉ−Ｆｅ系合金やＣｕ系
合金により構成される。コネクタワイヤ１１は、例えば
Ａノ細線より成る。半導体素子（チップ）１０は、例え
ばシリコン単結晶基板から成り、周知の技術によってこ
のチップ内には多数の回路素子が形成され、１つの回路
機能が与えられている。回路素子の具体例は、例えばＭ
ＯＳトランジスタから成り、これらの回路素子によって
、例えば論理回路およびメモリの回路機能が形成されて
いる。他の第５図以下に示すパッケージも同様の構成よ
り成る。The lead frame is made of, for example, a Ni-Fe alloy or a Cu alloy. The connector wire 11 is made of, for example, an A-sized wire. A semiconductor element (chip) 10 is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed within this chip using well-known techniques to provide one circuit function. A specific example of the circuit element is, for example, M
It consists of OS transistors, and these circuit elements form, for example, logic circuits and memory circuit functions. Other packages shown in FIG. 5 and subsequent figures have similar configurations.
本発明によればアウターリード２が裏面側に折曲げられ
ているが、他方のアウターリード３は第１図および第５
図などに示すように、パッケージ側面に平行に垂設され
、あるいは、面実装可能に引出され、パッケージ四辺か
ら取出されたアウタ′−ＩＪ−ドが全て裏面側に折曲げ
するようにしていないので、アウターリード２と３は接
触することがなく、例えば、アウターリード３をコーナ
一部罠配設しても、このアウターリード３は、パッケー
ジ裏面側に折曲げず、ＤＩＬＰ様に折曲げしておくこと
Ｋより、これらアウターリード２とアウターリード３と
は接触することがない。従って、従来のＰＬＣＣでは全
て裏面側に折曲げするので、アウターリードの接触を回
避するためＫは、コーナ一部にはアウターリードを配設
せず、コーナ一部に空スペースを設ける必要があったが
、本発明ではかかる空スペースを設ける必要がなくなっ
た。According to the present invention, the outer lead 2 is bent toward the back side, but the other outer lead 3 is bent as shown in FIGS.
As shown in the figure, all the outer IJ-boards that are hung vertically parallel to the side of the package or pulled out for surface mounting and taken out from the four sides of the package are not bent to the back side. , the outer leads 2 and 3 do not come into contact with each other. For example, even if the outer leads 3 are placed in a trap at a corner, the outer leads 3 will not be bent toward the back of the package, but will be bent in a DILP-like manner. Due to the distance K, the outer leads 2 and 3 do not come into contact with each other. Therefore, in conventional PLCCs, everything is bent to the back side, so in order to avoid contact with the outer leads, it is necessary for K to provide empty space at some corners without providing any outer leads. However, in the present invention, it is no longer necessary to provide such empty space.
それ故、アウターリードの本数を増加することができる
。Therefore, the number of outer leads can be increased.
また、第５図に示すものを従来のＰＰＰと比較した場合
にあっても、アウターリード４はパッケージ外部に突出
していても、アウターリード２は裏面側にＰＬＣＣと同
様に折曲げされているので、実装面積を減少させること
ができる。Also, when comparing the one shown in Fig. 5 with the conventional PPP, even though the outer leads 4 protrude outside the package, the outer leads 2 are bent on the back side like in PLCC. , the mounting area can be reduced.
すなわち上記から、実装面積当りのアウターリードの本
数を、本発明では増加できることが判る。That is, from the above, it can be seen that the number of outer leads per mounting area can be increased in the present invention.
さらに、第８図に示すように、アウターリードが接触し
ないように、斜め放射状に配設することにより、コーナ
一部にもアウターリードを配設することができ、従来の
ＰＬＣＣに比して、アウターリード１の本数を増加させ
ることができた。Furthermore, as shown in FIG. 8, by arranging the outer leads diagonally and radially so that they do not come into contact with each other, the outer leads can also be arranged in a part of the corner. The number of outer leads 1 could be increased.
以上本発明者によりてなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on examples, it should be noted that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist of the invention. Not even.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるＰＬＣＣの改良面で
説明したが、本発明はリードをエツチングにより構成す
る各種のチップキャリアタイプパッケージなどにも適用
できる。In the above explanation, the invention made by the present inventor was mainly explained in terms of improvement of PLCC, which is the field of application behind the invention, but the present invention can also be applied to various chip carrier type packages in which leads are formed by etching. can.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとうりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
すなわち、本発明によればＰＬＣＣにおける多ビン化の
要請に答えることができ、コーナ一部にもアウターリー
ドを配設でき、その実装面積当りのアウターリードの本
数を増加させることができた。That is, according to the present invention, it is possible to meet the demand for increasing the number of bins in PLCC, and it is also possible to arrange outer leads in some corners, thereby increasing the number of outer leads per mounting area.
第１図は本発明の実施例を示す底面図、第２図は第１図
Ｉ−Ｉ線断面図、
第３図は第１図■−■線断面図、
第４図は同全体概観図、
第５図は本発明の他の実施例を示す底面図、第６図は第
５図■−■線断面図、
第７図は同パッケージの実装説明図、
第８図は本発明のさらに他の実施例を示す底面図、
第９図は本発明のさらに他の実施例を示す全体概観図で
ある。
１・・・パンケージ、２，３．４・・・アウターリード
、５・・・実装基板、６・・・導体パターン、７．８・
・・アウターリード、９・・・タブ、１ｏ・・・半導体
素子、１１・・・コネクタワイヤ、１２・・・樹脂モー
ルド部。
代理人 弁理士 小 川 勝 男 ２−・第 １
図
第 ２ 図
第 ３ 図
第 ４ 図
第 ５ 図
第 ６ 図
第 ７ 図
第 ９ 図Fig. 1 is a bottom view showing an embodiment of the present invention, Fig. 2 is a sectional view taken along the line I--I of Fig. 1, Fig. 3 is a sectional view taken along the line ■-■ of Fig. 1, and Fig. 4 is an overall overview of the same. , FIG. 5 is a bottom view showing another embodiment of the present invention, FIG. 6 is a cross-sectional view taken along the line 5 - FIG. 9 is a bottom view showing another embodiment of the present invention. FIG. 9 is an overall overview diagram showing still another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Pan cage, 2, 3. 4... Outer lead, 5... Mounting board, 6... Conductor pattern, 7.8.
... Outer lead, 9... Tab, 1o... Semiconductor element, 11... Connector wire, 12... Resin mold part. Agent Patent Attorney Katsuo Ogawa 2-1
Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 9
Claims (1)
おいて、その一部をパッケージ裏面に折曲げしたアウタ
ーリードと、その一部をパッケージ側面に垂直にまたは
面実装可能に折曲げしたアウターリードとの二つの異な
った組合せアウターリードを有して成ることを特徴とす
る半導体パッケージ。 ２、半導体パッケージがプラスチックリードレスチップ
キャリア型半導体パッケージである、特許請求の範囲第
１項記載の半導体パッケージ。[Claims] 1. In a semiconductor package having outer leads on all four sides, an outer lead having a portion thereof bent to the back surface of the package, and an outer lead having a portion thereof bent perpendicularly to the side surface of the package or to enable surface mounting. A semiconductor package comprising an outer lead and two different combinations of outer leads. 2. The semiconductor package according to claim 1, wherein the semiconductor package is a plastic leadless chip carrier type semiconductor package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61092040A JPS62249464A (en) | 1986-04-23 | 1986-04-23 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61092040A JPS62249464A (en) | 1986-04-23 | 1986-04-23 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62249464A true JPS62249464A (en) | 1987-10-30 |
Family
ID=14043414
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61092040A Pending JPS62249464A (en) | 1986-04-23 | 1986-04-23 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62249464A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4238646A1 (en) * | 1991-11-14 | 1993-06-03 | Gold Star Electronics | New encapsulated semiconductor memory chip - has chips with bonding pads on central region, lead frame with leads connected to bonding parts, insulating adhesive, metal wire for electrical connection etc. |
| US5224021A (en) * | 1989-10-20 | 1993-06-29 | Matsushita Electric Industrial Co., Ltd. | Surface-mount network device |
-
1986
- 1986-04-23 JP JP61092040A patent/JPS62249464A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5224021A (en) * | 1989-10-20 | 1993-06-29 | Matsushita Electric Industrial Co., Ltd. | Surface-mount network device |
| DE4238646A1 (en) * | 1991-11-14 | 1993-06-03 | Gold Star Electronics | New encapsulated semiconductor memory chip - has chips with bonding pads on central region, lead frame with leads connected to bonding parts, insulating adhesive, metal wire for electrical connection etc. |
| USRE36097E (en) * | 1991-11-14 | 1999-02-16 | Lg Semicon, Ltd. | Semiconductor package for a semiconductor chip having centrally located bottom bond pads |
| USRE37413E1 (en) | 1991-11-14 | 2001-10-16 | Hyundai Electronics Industries Co., Ltd. | Semiconductor package for a semiconductor chip having centrally located bottom bond pads |
| DE4238646B4 (en) * | 1991-11-14 | 2006-11-16 | Goldstar Electron Co., Ltd., Cheongju | Semiconductor device with special connection configuration |
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