JPS61194753A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61194753A
JPS61194753A JP60034324A JP3432485A JPS61194753A JP S61194753 A JPS61194753 A JP S61194753A JP 60034324 A JP60034324 A JP 60034324A JP 3432485 A JP3432485 A JP 3432485A JP S61194753 A JPS61194753 A JP S61194753A
Authority
JP
Japan
Prior art keywords
bonding
substrate
chip
wire
wires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60034324A
Other languages
Japanese (ja)
Inventor
Hiroshi Tsuneno
常野　宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60034324A priority Critical patent/JPS61194753A/en
Publication of JPS61194753A publication Critical patent/JPS61194753A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Abstract

PURPOSE:To obtain a semiconductor device, in which wires are bonded excellently and contacts among the wires can be prevented and whose package can be miniaturized, by forming stepped sections to a substrate so that each of bonding sections with the wires in the substrate mutually has the difference in its height. CONSTITUTION:A semiconductor chip 5 is die-bonded into a recess 2 in a substrate 1 by a joining material 6, and a plurality of chip-side bonding pads 7 disposed to the four sides of the chip 5 and head sections 8 in lead pins 9, one parts thereof are buried into the substrate 1 made of a resin, the head sections 8 thereof are exposed from said bonding sections 3, 4 for the substrate 1 and which are projected in the vertical direction from the back of the substrate 1, are wire-bonded by wires 10. Since stepped sections are formed to the bonding sections 3, 4 with several wire of the substrate 1, the wires 10 bonding the chip-side bonding pads 7 and the head sections 8 of the lead pins 9 in the bonding section 4 are positioned being higher than the wires 10 similarly bonding the chip-side bonding pads 7 and the head sections 8 of the lead pins 9 in the bonding section 3.

Description

【発明の詳細な説明】 本発明は半導体装置特にその高密度実装技術に関する。[Detailed description of the invention] TECHNICAL FIELD The present invention relates to semiconductor devices, particularly to high-density packaging techniques thereof.

（背景技術） ピングリッドアレイ形セラミックパッケージの周知構造
の一例としてセラミック基板の半導体チップ搭ｌｉ２部
（凹み）に、当該チップをダイボンディングし、チップ
側のボンディングパッドと前記基板に設けられたボンデ
ィングパッドとをワイヤによりボンティングし、接合材
料により基板上にキャップを取り付け、前記基板側ボン
ディングパッドと基板裏面から垂直に突出したリードピ
ンとを基板内に設げらねた導体配線により接続して成る
ものがある。(Background Art) As an example of a well-known structure of a pin grid array type ceramic package, the chip is die-bonded to the semiconductor chip mounting portion (recess) of a ceramic substrate, and bonding pads on the chip side and bonding pads provided on the substrate are bonded. are bonded with wire, a cap is attached to the board using a bonding material, and the board-side bonding pad and lead pins protruding perpendicularly from the back of the board are connected by conductive wiring provided within the board. There is.

このパッケージにおける基板側のボンディングパッドは
一般に半導体チップの周辺部に一列状態に複数配設され
ているが、場合により複数列に配設されていることもあ
るが、いずれにしても、これらハ・ノドは基板の同一平
面上に配置さ七ており、チップのボンディングパッドが
増加しいわゆる多ピン化の傾向に際し、ワイヤボンディ
ングが困難となったり、パッケージが大型化するという
欠点があった。なお、ピングリッドアレイ形パブケージ
について詳しく述べである例として、日経マグロウヒル
社発行［日経エレクトロニクス、別冊（マイクロデバイ
セズ）Ｊ１９８４年６月１１日、陽２　　ｐ１２９〜ｐ
１４７がある。In general, a plurality of bonding pads on the substrate side of this package are arranged in a line around the semiconductor chip, but in some cases they may be arranged in multiple lines, but in any case, these The nodes are arranged on the same plane of the substrate, and as the number of bonding pads on chips increases and the trend toward so-called multi-pins occurs, wire bonding becomes difficult and the package becomes larger. As an example of a detailed description of the pin grid array type pub cage, there is an example published by Nikkei McGraw-Hill [Nikkei Electronics, separate issue (Micro Devices) J June 11, 1984, Yang 2 p129-p.
There are 147.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、ワイヤボンディングが良好に行なえ、
ワイヤ間の接触が防止でき、パッケージの小型化が可能
な半導体装置を提供することにある。An object of the present invention is to enable wire bonding to be performed well;
An object of the present invention is to provide a semiconductor device in which contact between wires can be prevented and the package can be miniaturized.

本発明の他の目的は、コストが安く、しかも信頼性の高
い半導体装置を提供することにある。Another object of the present invention is to provide a semiconductor device that is low in cost and highly reliable.

本発明の前記ならびにそのほかの目的と新規な％徴は、
本明細書の記述および絵付図面からあきらかになるであ
ろう。The above and other objects and novel characteristics of the present invention are as follows:
It will become clear from the description of this specification and the illustrated drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.

すなわち、本発明では、ワイヤとのボンディングの各々
に段差を設けて成る基板を用い、チップのボンディング
パッドと前記ボンディング部のパッドとをワイヤにより
ワイヤボンディングすることＫより、同一平面上にボン
ディングパッドが配列された場合に比してワイヤボンデ
ィングが良好に行なえ、しかも、各ワイヤに高低差があ
り接触を防止し、かつ、同一平面上にある場合と異なり
各パッド間隔をつめることなくワイヤボンディングが可
能となるのでパッケージを小型化できるなどの利点を有
する半導体装置と成することができた。That is, in the present invention, the bonding pads are bonded on the same plane by wire bonding the bonding pads of the chip and the pads of the bonding part using wires using a substrate having a step for each bonding with the wire. Wire bonding can be performed better than when wires are arranged in an array, and each wire has a height difference to prevent contact, and wire bonding can be performed without narrowing the spacing between pads unlike when wires are on the same plane. Therefore, it was possible to create a semiconductor device having advantages such as the ability to downsize the package.

（実施例〕 次に本発明を実施例の一例を示す第１図および第２図を
参照しつつ説明する。(Example) Next, the present invention will be described with reference to FIGS. 1 and 2 showing an example of an example.

第１図は、本発明半導体装置の一例を示す断面図、第２
図はキャップを取除いて成る同装置の平面図である。FIG. 1 is a sectional view showing an example of the semiconductor device of the present invention, and FIG.
The figure is a plan view of the device with the cap removed.

基板１の中央部に半導体チップを搭載するための凹み２
を設け、その外側に、凹み２の縁の高さに一致した第１
段のワイヤとのボンディング部３を設け、さらに、該ボ
ンディング部３よりも高い位置に第２段のワイヤとのボ
ンディング部４を設ける。A recess 2 for mounting a semiconductor chip in the center of the substrate 1
and on the outside thereof, a first plate corresponding to the height of the edge of the recess 2.
A bonding portion 3 with the wire of the tier is provided, and a bonding portion 4 with the wire of the second tier is further provided at a higher position than the bonding portion 3.

基板１は例えば樹脂により構成する。The substrate 1 is made of resin, for example.

具体的には、例えばエポキシ樹脂やガラスエポキシ樹脂
により構成する。Specifically, it is made of, for example, epoxy resin or glass epoxy resin.

基板１の凹み２に半導体チップ５を接合材料６によりグ
イボンディングし、該チップ５の四辺に複数第２図に示
すように配設されたチップ側ボンディングパッド７と、
樹脂製基板１中にその一部が埋込まれ、その頭部８が基
板１の前記ボンディング部３．４から露出し、かつ、基
板１裏面から、垂直方向に突出したリードピン９の前記
頭部８とをワイヤ１０によりワイヤボンディングする。A semiconductor chip 5 is bonded to the recess 2 of the substrate 1 using a bonding material 6, and a plurality of chip-side bonding pads 7 are arranged on the four sides of the chip 5 as shown in FIG.
The head of the lead pin 9 is partially embedded in the resin substrate 1, the head 8 is exposed from the bonding portion 3.4 of the substrate 1, and projects vertically from the back surface of the substrate 1. 8 are wire-bonded using a wire 10.

基板１の各ワイヤとのボンディング部３．４に段差が設
けられている結果、チップ側ボンディングパッド７と上
記ボンディング部４のリードピン９頭部８とをボンディ
ングするワイヤ１ｏは、同様にチップ側ボンディングパ
ッド７と上記ボンディング部３のリードピン９頭部８と
をボンディングするワイヤ１０よりも高い位置にある。As a result of the step provided in the bonding portion 3.4 with each wire of the substrate 1, the wire 1o for bonding the chip-side bonding pad 7 and the lead pin 9 head 8 of the bonding portion 4 is similarly connected to the chip-side bonding portion 3.4. It is located at a higher position than the wire 10 that bonds the pad 7 and the head 8 of the lead pin 9 of the bonding section 3.

半導体チップ５は、例えはシリコン単結晶基板から取り
、周知の技術によ−てこのチップ内には多数の回路素子
が形成さね、１つの回路機能が与えられている。回路素
子の具体例は、例えばＭＯＳトランジスタから成り、こ
れらの回路素子によって、例えばメモリや論理回路の回
路機能が形成されている。The semiconductor chip 5 is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed within this chip using well-known techniques to provide one circuit function. A specific example of the circuit element is, for example, a MOS transistor, and these circuit elements form a circuit function such as a memory or a logic circuit.

該チップ５を基板１にダイボンディングする接合材料６
は例えば合成樹脂系接着剤により構成される。Bonding material 6 for die bonding the chip 5 to the substrate 1
is made of, for example, a synthetic resin adhesive.

リードピン９は例えば、金属より構成される。The lead pin 9 is made of metal, for example.

適宜径の、一般にピングリッドアレイパッケージに用い
られているような金属ビンなどにより構成される。ワイ
ヤボンディングに使用さねているようなＡ＃嶽により構
成されていてもよい。リードフレーム材料として使用さ
れているコバール合金（Ｆｅ−Ｎｉ系合金）でもよいが
、銅系合金材料により構成することにより、メッキなど
を省略して直接ワイヤボンディングができるようにする
ことが好ましい。It is composed of a metal bottle or the like of a suitable diameter, such as the one commonly used in pin grid array packages. It may also be constructed from an A# mount, such as that used for wire bonding. Although Kovar alloy (Fe-Ni alloy) used as a lead frame material may be used, it is preferable to use a copper alloy material so that direct wire bonding can be performed without plating or the like.

リードピン９の樹脂基板１中への埋込みは、各種の方法
によって可能であり、例えば多段に形成さ第１たワイヤ
とのボンディング部３．４を有する基板１に穴（図示せ
ず）を穿設し、当該穴にり−ドピン９の一部を差込み固
着してもよいし、また、複数本のリードピンを成形型中
に立設しておき、当該型内に樹脂を流し込み硬化させて
もよい。さらに、本発明者が先に提案した多心ケーブル
の合成樹脂による押田し核種方法を採用してもよい。The lead pins 9 can be embedded in the resin substrate 1 by various methods, for example, by drilling holes (not shown) in the substrate 1 having bonding portions 3.4 with the first wire formed in multiple stages. However, a part of the lead pin 9 may be inserted into the hole and fixed, or a plurality of lead pins may be set upright in the mold, and resin may be poured into the mold and cured. . Furthermore, the nuclide pressing method using synthetic resin for multi-core cables, which was previously proposed by the present inventor, may be employed.

ワイヤｌＯは例えば２ｕ細線により構成される。The wire IO is composed of, for example, a 2u thin wire.

チップ５内の内部配線がワイヤ１０、リードピン９を経
て外部に取り出しすることができ、外部との導通をとる
ことができる。The internal wiring inside the chip 5 can be taken out to the outside via the wire 10 and the lead pin 9, and conduction with the outside can be established.

かかるワイヤボンディングによる電気的、物理的接続後
に、基板１上にキャップ１１を接着剤１２により取付す
る。After the electrical and physical connection by wire bonding, the cap 11 is attached to the substrate 1 using an adhesive 12.

キャップ１１は樹脂製のものとすることがコストの低減
になる。Making the cap 11 made of resin reduces costs.

接着剤１２は例えば合成樹脂系の接着剤により構成され
る。The adhesive 12 is made of, for example, a synthetic resin adhesive.

〔効果〕〔effect〕

ｆｉｌ　　本発明によれば、基板のワイヤとのボンディ
ング部の各々相互に高低差を生じるようＫ、基板に段差
が設けられ、したがって、ワイヤとのボンディングパッ
ド部も複数列に構成され、ワイヤには高低差がつけられ
ているので、ワイヤ相互の接触も防止でき、高信頼性の
半導体装置を提供できた。・ （２１本発明によれば、ビン数が増大しても多段の基板
側ボンディングパッドによりワイヤボンディングが可能
で、同一平面上忙バッドを配設する場合に比してキャビ
ティを不必要に大きくする必要がなく、パッケージを小
型化できる。fil According to the present invention, steps are provided on the substrate so as to create a height difference between the bonding portions of the substrate with the wires, and therefore the bonding pad portions with the wires are also arranged in multiple rows. Since there is a difference in height, it is possible to prevent the wires from coming into contact with each other, making it possible to provide a highly reliable semiconductor device. (21) According to the present invention, even if the number of bins increases, wire bonding is possible using multi-stage board-side bonding pads, making the cavity unnecessarily large compared to the case where busy pads are arranged on the same plane. This is not necessary and the package can be made smaller.

複数例のパッドの存在により、かつ、多段のパッドの存
在により、ワイヤを段の異なる各パッド忙対応させて打
つことができ、リードピッチをつめることなしにワイヤ
ボンディングが可能となり、ワイヤボンディングが容易
となった。Due to the presence of multiple pads and the presence of multi-stage pads, the wire can be applied to each pad in different stages, making wire bonding possible without narrowing the lead pitch, making wire bonding easy. It became.

（３１本発明によれば基板を樹脂製とし、リードピンを
当該樹脂中に埋込みすることにより、製法上も又構造上
も簡単でかつ安価な基板となすことができ、従来のヌル
−ホールによる導体配線も必要がなく、従来のビーグリ
ッドアレイのごとく基板に半田付けなどでピンを立設す
る必要もなく、また、リードピンが樹脂中に埋込まれて
いるので放熱特性が良く、さらにリードピンの材料を選
択することにより直接ワイヤボンディングも可能となる
各種利点を奏することができた。(31 According to the present invention, by making the board made of resin and embedding the lead pins in the resin, it is possible to create a board that is simple and inexpensive in terms of manufacturing method and structure, and it is possible to create a board that is simple and inexpensive in terms of manufacturing method and structure. There is no need for wiring, and there is no need to erect pins on the board by soldering, etc., as with conventional B-Grid arrays.In addition, the lead pins are embedded in resin, which has good heat dissipation characteristics, and the material of the lead pins By selecting , we were able to achieve various advantages by making direct wire bonding possible.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

Ｌ弁憧→≠瞬り用分野〕 本発明はピングリッドアレイ形パッケージノ他各種のパ
ッケージ全般に適用できる。L-valve design→≠blink field] The present invention can be applied to pin grid array packages and other types of packages in general.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の実施例を示す断面図で、第２図は本発
明の実施例を示すキャップを取去った平面図である。 １・・・基板、２・・・凹み、３・・・ボンディング、
４・・・ボンディング、５・・・半導体チップ、６・・
・接合材料、７・・・ボンディングパッド、８・・・頭
部、９・・・リードピン、１０・・・ワイヤ、１１・・
・キャップ、１２・・・接着剤。FIG. 1 is a cross-sectional view showing an embodiment of the present invention, and FIG. 2 is a plan view with the cap removed, showing the embodiment of the present invention. 1... Board, 2... Recess, 3... Bonding,
4... Bonding, 5... Semiconductor chip, 6...
- Bonding material, 7... Bonding pad, 8... Head, 9... Lead pin, 10... Wire, 11...
・Cap, 12...Adhesive.

Claims (1)

【特許請求の範囲】 １、ワイヤとのボンディング部の各々に段差を設けて成
る基板により構成されたことを特徴とする半導体装置。 ２、基板が、樹脂製基板より成る、請求の範囲第１項記
載の半導体装置。 ３、ワイヤとのボンディング部が、基板に埋込まれたリ
ードピンを有して成る、請求の範囲第１項又は第２項記
載の半導体装置。 ４、半導体装置が、基板上中心部に半導体チップを固着
し、該チップとリードピンより成るボンディングパッド
部とをワイヤにより接続し、基板裏面よりリードピンを
垂直方向に出したピングリッドアレイ形パッケージであ
る、請求の範囲第１項〜第４項いずれか一項に記載の半
導体装置。[Scope of Claims] 1. A semiconductor device comprising a substrate having a step provided at each bonding portion with a wire. 2. The semiconductor device according to claim 1, wherein the substrate is made of a resin substrate. 3. The semiconductor device according to claim 1 or 2, wherein the bonding portion with the wire has a lead pin embedded in the substrate. 4. The semiconductor device is a pin grid array type package in which a semiconductor chip is fixed to the center of the substrate, the chip is connected to a bonding pad portion consisting of lead pins by wire, and the lead pins are vertically protruded from the back side of the substrate. , a semiconductor device according to any one of claims 1 to 4.
JP60034324A 1985-02-25 1985-02-25 Semiconductor device Pending JPS61194753A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60034324A JPS61194753A (en) 1985-02-25 1985-02-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60034324A JPS61194753A (en) 1985-02-25 1985-02-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61194753A true JPS61194753A (en) 1986-08-29

Family

ID=12410971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60034324A Pending JPS61194753A (en) 1985-02-25 1985-02-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61194753A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63234552A (en) * 1987-03-24 1988-09-29 Shinko Electric Ind Co Ltd Semiconductor package
KR19990056764A (en) * 1997-12-29 1999-07-15 김영환 Ball grid array package
CN117038646A (en) * 2023-10-08 2023-11-10 之江实验室 Ceramic packaging structure and design method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63234552A (en) * 1987-03-24 1988-09-29 Shinko Electric Ind Co Ltd Semiconductor package
KR19990056764A (en) * 1997-12-29 1999-07-15 김영환 Ball grid array package
CN117038646A (en) * 2023-10-08 2023-11-10 之江实验室 Ceramic packaging structure and design method thereof
CN117038646B (en) * 2023-10-08 2024-01-26 之江实验室 Ceramic packaging structure and design method thereof

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