JPS6159860A - Manufacture of semiconductor integrated circuit device - Google Patents

Manufacture of semiconductor integrated circuit device

Info

Publication number
JPS6159860A
JPS6159860A JP59181908A JP18190884A JPS6159860A JP S6159860 A JPS6159860 A JP S6159860A JP 59181908 A JP59181908 A JP 59181908A JP 18190884 A JP18190884 A JP 18190884A JP S6159860 A JPS6159860 A JP S6159860A
Authority
JP
Japan
Prior art keywords
electrodes
integrated circuit
semiconductor integrated
circuit device
manufacture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59181908A
Other languages
Japanese (ja)
Other versions
JPH0221139B2 (en
Inventor
Nobuhiko Aneba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59181908A priority Critical patent/JPH0221139B2/ja
Publication of JPS6159860A publication Critical patent/JPS6159860A/en
Publication of JPH0221139B2 publication Critical patent/JPH0221139B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/041Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction having no base used as a mounting for the semiconductor body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05553Shape in top view being rectangular
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4918Disposition being disposed on at least two different sides of the body, e.g. dual array
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Abstract

PURPOSE:To increase the integration of a semiconductor integrated circuit device by bonding chips formed with devices on both side surfaces to a hollow module formed with electrodes on the stepped portions of the both side surfaces to seal in a package. CONSTITUTION:Electrodes 4a, 4b are formed on the upper and lower surfaces of a module 1, and a chip 2 is bonded to the upper surface. Then, electrodes 3a, 4a are connected via wirings 5a on the upper surface, and electrodes 3b, 4b are connected via wirings 5b on the lower surface. Then, the module 1 is bonded to a package 6, and a cap 7 is eventually bonded to the package 6.
JP59181908A 1984-08-31 1984-08-31 Expired - Lifetime JPH0221139B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59181908A JPH0221139B2 (en) 1984-08-31 1984-08-31

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59181908A JPH0221139B2 (en) 1984-08-31 1984-08-31

Publications (2)

Publication Number Publication Date
JPS6159860A true JPS6159860A (en) 1986-03-27
JPH0221139B2 JPH0221139B2 (en) 1990-05-11

Family

ID=16108994

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59181908A Expired - Lifetime JPH0221139B2 (en) 1984-08-31 1984-08-31

Country Status (1)

Country Link
JP (1) JPH0221139B2 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0392242A2 (en) * 1989-04-10 1990-10-17 International Business Machines Corporation Module assembly with intergrated semiconductor chip and chip carrier
EP0631691A4 (en) * 1992-03-16 1997-05-07 Dense Pac Microsystems Inc Ic chip package and method of making same.
US5833407A (en) * 1996-02-19 1998-11-10 Okuma Corporation Method for estimating heat-included displacment in a machine tool
EP1353374A1 (en) * 1990-09-24 2003-10-15 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
DE102007058870A1 (en) 2006-12-18 2008-07-24 Okuma Corporation Method for detecting the abnormality of a temperature sensor in a machine tool
DE102007058871A1 (en) 2006-12-11 2008-08-28 Okuma Corporation Method for detecting the abnormality of a temperature sensor in a machine tool
IT201900009660A1 (en) * 2019-06-20 2020-12-20 St Microelectronics Srl SEMICONDUCTOR INTEGRATED DEVICE AND PROCEDURE FOR MANUFACTURING AN INTEGRATED SEMICONDUCTOR DEVICE
WO2022090731A1 (en) * 2020-10-30 2022-05-05 Npl Management Limited Ion microtrap assembly and method of making of making such an assembly
US11389886B2 (en) 2018-10-19 2022-07-19 Sodick Co., Ltd. Electric discharge machining apparatus

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0392242A2 (en) * 1989-04-10 1990-10-17 International Business Machines Corporation Module assembly with intergrated semiconductor chip and chip carrier
EP0392242A3 (en) * 1989-04-10 1991-12-11 International Business Machines Corporation Module assembly with intergrated semiconductor chip and chip carrier
EP1353374A1 (en) * 1990-09-24 2003-10-15 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
EP0631691A4 (en) * 1992-03-16 1997-05-07 Dense Pac Microsystems Inc Ic chip package and method of making same.
US5833407A (en) * 1996-02-19 1998-11-10 Okuma Corporation Method for estimating heat-included displacment in a machine tool
DE102007058871A1 (en) 2006-12-11 2008-08-28 Okuma Corporation Method for detecting the abnormality of a temperature sensor in a machine tool
DE102007058870A1 (en) 2006-12-18 2008-07-24 Okuma Corporation Method for detecting the abnormality of a temperature sensor in a machine tool
US11389886B2 (en) 2018-10-19 2022-07-19 Sodick Co., Ltd. Electric discharge machining apparatus
IT201900009660A1 (en) * 2019-06-20 2020-12-20 St Microelectronics Srl SEMICONDUCTOR INTEGRATED DEVICE AND PROCEDURE FOR MANUFACTURING AN INTEGRATED SEMICONDUCTOR DEVICE
US11069587B2 (en) 2019-06-20 2021-07-20 Stmicroelectronics S.R.L. Integrated semiconductor device and process for manufacturing an integrated semiconductor device
WO2022090731A1 (en) * 2020-10-30 2022-05-05 Npl Management Limited Ion microtrap assembly and method of making of making such an assembly

Also Published As

Publication number Publication date
JPH0221139B2 (en) 1990-05-11

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