JPH06224537A - Lead pitch changing board for surface mounting - Google Patents

Lead pitch changing board for surface mounting

Info

Publication number
JPH06224537A
JPH06224537A JP5028607A JP2860793A JPH06224537A JP H06224537 A JPH06224537 A JP H06224537A JP 5028607 A JP5028607 A JP 5028607A JP 2860793 A JP2860793 A JP 2860793A JP H06224537 A JPH06224537 A JP H06224537A
Authority
JP
Japan
Prior art keywords
sopic
board
package
pads
standard
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5028607A
Other languages
Japanese (ja)
Inventor
Yuzo Ichiyama
雄三 市山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kaijo Corp
Original Assignee
Kaijo Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kaijo Corp filed Critical Kaijo Corp
Priority to JP5028607A priority Critical patent/JPH06224537A/en
Publication of JPH06224537A publication Critical patent/JPH06224537A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components

Landscapes

  • Multi-Conductor Connections (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To easily change the pitch of leads at the time of mounting SOPICs having a shorter lead-to-lead pitch on a printed board on which pads for longer pitches are set. CONSTITUTION:The title changing board 1 is a printed board having a surface peripheral shape similar to the peripheral shape of an SOPIC 2 meeting the EIAJ package standard, with the size of the board 1 being slightly larger than that of the SOPIC 2. The width of the board 1 is nearly equal to the width- direction lead-to-lead pitch of the SOPIC meeting the JEDEC package standard. The board 1 is provided with pads 1a for SOPIC 2 on the surface and recessed sections 1b respectively counterposed to the pads 1a on both side faces in the width direction and conductor foil formed in the sections 1b are connected to their corresponding pads 1a on the surface. The sections 1b are soldered to pads 3 for SOPIC meeting the JEDEC package standard. In addition, the sections 1b has semicircular or semiellipse shapes.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、ＪＥＤＥＣパッケージ
規格に基づくデュアルインラインパッケージＳＯＰ（Su
rface Small Outline Package)ＩＣ用のパットにＥＩＡ
Ｊパッケージ規格に基づくデュアルインラインパッケー
ジＳＯＰＩＣのリードを半田付けする際に用いる表面実
装用リードピッチ変換基板に関する。The present invention relates to a dual in-line package SOP (Su
rface Small Outline Package) EIA as a pad for IC
The present invention relates to a surface mounting lead pitch conversion substrate used when soldering the leads of a dual in-line package SOPIC based on the J package standard.

【０００２】[0002]

【従来の技術】周知のように、ＳＯＰＩＣは、ＪＥＤＥ
ＣとＥＩＡＪの２種類のパッケージ規格によりそれぞれ
製造され使用されており、デュアルインラインパッケー
ジＳＯＰＩＣのプリント基板への実装は、例えば図５に
示すように、図示しないプリント基板面に、実装するＳ
ＯＰＩＣ５１のパッケージ規格に従ってパット５２を設
定し、それにＳＯＰＩＣ５１のリードを半田付けするこ
とにより行われる。つまり、パット５２はＳＯＰＩＣ５
１の幅方向のリード間ピッチＡとほぼ等しい間隔Ｂで設
定されるのが通例である。2. Description of the Related Art As is well known, SOPIC is based on JEDE.
The dual in-line package SOPIC, which is manufactured and used in accordance with two types of package standards of C and EIAJ, is mounted on a printed circuit board surface (not shown), for example, as shown in FIG.
The pad 52 is set according to the package standard of the OPIC 51, and the leads of the SOPIC 51 are soldered to the pad 52. That is, the pad 52 is the SOPIC 5
It is customary to set an interval B that is substantially equal to the lead pitch A in the width direction of 1.

【０００３】ところが、幅方向のリード間ピッチは、Ｊ
ＥＤＥＣパッケージ規格に基づくものがＥＩＡＪパッケ
ージ規格に基づくものよりも大きいので、ＪＥＤＥＣパ
ッケージ規格に基づくＳＯＰＩＣを実装するため用意し
たプリント基板にＥＩＡＪパッケージ規格に基づくＳＯ
ＰＩＣを実装する場合、例えば図６に示すように、図示
しないプリント基板面に設定してあるパット６１はＪＥ
ＤＥＣパッケージ規格に基づくものであるので、その間
隔Ｗ1 は実装しようとするＥＩＡＪパッケージ規格に基
づくＳＯＰＩＣ６２の幅方向のリード間ピッチＷ2 より
も大きく、両者間に隙間が生じ半田付けができないこと
となる。However, the lead pitch in the width direction is J
Since the one based on the EDEC package standard is larger than the one based on the EIAJ package standard, an SO based on the EIAJ package standard is mounted on the printed circuit board prepared for mounting the SOPIC based on the JEDEC package standard.
When the PIC is mounted, for example, as shown in FIG. 6, the pad 61 set on the surface of a printed circuit board (not shown) is JE.
Since it is based on the DEC package standard, the distance W 1 is larger than the lead-to-lead pitch W 2 in the width direction of the SOPIC 62 based on the EIAJ package standard to be mounted, and there is a gap between the two to prevent soldering. Become.

【０００４】そこで、従来では、例えば図７に示すよう
に、ＪＥＤＥＣパッケージ規格に基づくＳＯＰＩＣを実
装するため用意したプリント基板７１の他に、ＥＩＡＪ
パッケージ規格に基づくＳＯＰＩＣ７２を実装するプリ
ント基板７３を用意し、このプリント基板７３を連結用
ピン７４によりプリント基板７１の上面の上方に適宜間
隔持ち上げて設定することが行われている。Therefore, in the past, as shown in FIG. 7, for example, in addition to the printed board 71 prepared for mounting the SOPIC based on the JEDEC package standard, EIAJ
A printed circuit board 73 on which the SOPIC 72 based on the package standard is mounted is prepared, and the printed circuit board 73 is set above the upper surface of the printed circuit board 71 by an appropriate interval with a connecting pin 74.

【０００５】[0005]

【発明が解決しようとする課題】しかし、図７に示すよ
うな２階建て構造では、実装作業が面倒であるだけでな
く実装スペースの確保が困難な場合があり、またコスト
アップの要因となるという問題がある。However, in the two-story structure as shown in FIG. 7, not only the mounting work is troublesome, but also the mounting space may be difficult to secure, which causes a cost increase. There is a problem.

【０００６】本発明は、このような従来の問題に鑑みな
されたもので、その目的は、実装スペースの問題を生じ
させず簡単にリードピッチの変換をなし得る表面実装用
リードピッチ変換基板を提供することにある。The present invention has been made in view of such conventional problems, and an object thereof is to provide a lead pitch conversion substrate for surface mounting which can easily convert the lead pitch without causing a problem of mounting space. To do.

【０００７】[0007]

【課題を解決するための手段】前記目的を達成するため
に、本発明の表面実装用リードピッチ変換基板は次の如
き構成を有する。即ち、本発明の表面実装用リードピッ
チ変換基板は、表面周形状がＥＩＡＪパッケージ規格に
基づくデュアルインラインパッケージＳＯＰＩＣの周形
状よりも若干大き目の相似形であって幅がＪＥＤＥＣパ
ッケージ規格に基づくデュアルインラインパッケージＳ
ＯＰＩＣの幅方向のリード間ピッチと少なくともほぼ等
しい大きさに形成されてなり； その表面にＥＩＡＪパ
ッケージ規格に基づくＳＯＰＩＣ用のパットが設定さ
れ； その短手方向両側の側面の前記各パットに対応し
た位置に半円状または半長円状の凹部がそれぞれ形成さ
れ； 前記側面の凹部に形成される導体箔と表面の対応
するパットとを連結してなる； ことを特徴とするもの
である。In order to achieve the above object, the surface mounting lead pitch conversion substrate of the present invention has the following constitution. That is, the surface mounting lead pitch conversion substrate of the present invention is a dual in-line package whose surface peripheral shape is slightly larger than the peripheral shape of the dual in-line package SOPIC based on the EIAJ package standard and whose width is based on the JEDEC package standard. S
It is formed to have a size at least approximately equal to the pitch between leads in the width direction of the OPIC; a pad for SOPIC based on the EIAJ package standard is set on its surface; A semi-circular or semi-elliptical concave portion is formed at each position, and the conductor foil formed in the concave portion on the side surface and the corresponding pad on the surface are connected to each other.

【０００８】[0008]

【作用】次に、前記の如く構成される本発明の表面実装
用リードピッチ変換基板の作用を説明する。本発明で
は、当該変換基板の表面にパットを設けＥＩＡＪパッケ
ージ規格に基づくデュアルインラインパッケージＳＯＰ
ＩＣを半田付け実装できるようにし、また当該変換基板
の側面に凹部を形成しＪＥＤＥＣパッケージ規格に基づ
くデュアルインラインパッケージＳＯＰＩＣを実装する
プリント基板に設定してあるパットに半田付けできるよ
うにしてある。Next, the operation of the surface mounting lead pitch conversion substrate of the present invention constructed as described above will be described. In the present invention, a pad is provided on the surface of the conversion board, and a dual in-line package SOP based on the EIAJ package standard is provided.
The IC can be mounted by soldering, and a recess is formed on the side surface of the conversion substrate so that the IC can be soldered to a pad set on a printed board on which a dual in-line package SOPIC based on the JEDEC package standard is mounted.

【０００９】従って、繁雑な実装作業を要さずに簡単に
リードピッチの変換が行えることになり、幅方向のリー
ド間ピッチが大きい方のＳＯＰＩＣ用に設定してあるプ
リント基板に幅方向のリード間ピッチが小さい方のＳＯ
ＰＩＣを実装スペースの問題を生じさせずに支障なく実
装できる表面実装用リードピッチ変換基板を提供でき
る。Therefore, the lead pitch can be easily converted without requiring a complicated mounting work, and the lead in the width direction is provided on the printed circuit board set for the SOPIC having a larger lead-to-lead pitch in the width direction. SO with smaller pitch
It is possible to provide a surface-mounting lead pitch conversion substrate on which the PIC can be mounted without causing a problem in the mounting space.

【００１０】なお、側面に形成する凹部は、基板に一列
に丸穴または長穴を穿設しその丸穴または長穴を列方向
に切断して形成すれば、簡単に所望の凹部が得られる。
半長円の場合は半円の場合よりも半田付けの信頼性確保
の点が優れている。The recesses formed on the side surfaces can be easily obtained by forming round holes or elongated holes in a row in the substrate and cutting the round holes or elongated holes in the row direction. .
In the case of a semi-oval, the reliability of soldering is better than in the case of a semi-circle.

【００１１】[0011]

【実施例】以下、本発明の実施例を図面を参照して説明
する。図１は、本発明の一実施例に係る表面実装用リー
ドピッチ変換基板を示す。図１において、表面実装用リ
ードピッチ変換基板１は、実際の使い勝手を考慮して表
面周形状がＥＩＡＪパッケージ規格に基づくデュアルイ
ンラインパッケージのＳＯＰＩＣ２の周形状よりも若干
大き目の相似形プリント基板である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a surface mounting lead pitch conversion substrate according to an embodiment of the present invention. In FIG. 1, the surface mounting lead pitch conversion substrate 1 is a similar printed circuit board whose surface peripheral shape is slightly larger than the peripheral shape of the SOPIC 2 of the dual in-line package based on the EIAJ package standard in consideration of actual usability.

【００１２】そして、その幅は、ＪＥＤＥＣパッケージ
規格に基づくデュアルインラインパッケージのＳＯＰＩ
Ｃの幅方向のリード間ピッチと少なくともほぼ等しい大
きさに形成してある。具体的には例えば図示するように
そのＳＯＰＩＣを半田付けするパット３と重なる程度に
してある。The width of the dual in-line package based on the JEDEC package standard
It is formed to have a size at least approximately equal to the pitch between leads in the width direction of C. Specifically, for example, as shown in the figure, the SOPIC is overlapped with the pad 3 for soldering.

【００１３】さらに、その表面にはＳＯＰＩＣ２用のパ
ット１ａを設定し、その短手方向両側の側面の前記パッ
ト１ａのそれぞれに対応した位置に凹部１ｂをそれぞれ
形成してあり、凹部１ｂに形成される導体箔と表面の対
応するパット１ａとを連結してある。Further, a pad 1a for the SOPIC 2 is set on the surface thereof, and recesses 1b are formed at positions corresponding to the pads 1a on both sides in the lateral direction of the pad 1a, respectively. The conductive foil and the corresponding pad 1a on the surface are connected.

【００１４】従って、図２に示すように、何れを先に半
田付けするかは任意であるが、当該変換基板１の表面に
設けたパット１ａにＥＩＡＪパッケージ規格に基づくデ
ュアルインラインパッケージのＳＯＰＩＣ２のリードを
半田付けし、また当該変換基板１の側面に形成してある
凹部１ｂをＪＥＤＥＣパッケージ規格に基づくデュアル
インラインパッケージＳＯＰＩＣを実装するプリント基
板に設定してあるパット３に半田付けする（図３のＢ）
という簡単な作業でＳＯＰＩＣ２を規格が異なるプリン
ト基板に実装できる。当該変換基板１も通常使用される
プリント基板であるので、従来のようなスペース確保に
対する考慮は不要であることが解る。Therefore, as shown in FIG. 2, it is arbitrary which one is soldered first, but the pad 1a provided on the surface of the conversion board 1 is provided with leads of the SOPIC 2 of the dual in-line package based on the EIAJ package standard. And the concave portion 1b formed on the side surface of the conversion board 1 is soldered to the pad 3 which is set on the printed board on which the dual in-line package SOPIC based on the JEDEC package standard is mounted (B in FIG. 3). )
The SOPIC 2 can be mounted on a printed circuit board having a different standard by such a simple operation. Since the conversion board 1 is also a normally used printed board, it can be understood that the conventional consideration for securing a space is unnecessary.

【００１５】次に、当該変換基板１の製造方法、特に幅
の設定及び側面の凹部１ｂの形成方法を説明する。図３
に示すように、当該変換基板１の幅は、ＪＥＤＥＣパッ
ケージ規格に基づくデュアルインラインパッケージＳＯ
ＰＩＣを実装するプリント基板４に設定してあるパット
３と重なる程度の大きさであるが、これはＪＥＤＥＣパ
ッケージ規格で定まる。Next, a method of manufacturing the conversion substrate 1, particularly a method of setting the width and forming the concave portion 1b on the side surface will be described. Figure 3
As shown in, the width of the conversion board 1 is a dual in-line package SO based on the JEDEC package standard.
The size is such that it overlaps with the pad 3 set on the printed circuit board 4 on which the PIC is mounted, but this is determined by the JEDEC package standard.

【００１６】そこで、図４に示すように、適宜な大きさ
のプリント基板に、前記幅の両側のラインを線引きし、
同図（ａ）中矢印Ｃで示すように、その線引きに沿って
前記パット１ａの間隔でスルーホール５を穿設し、同図
（ｂ）に示すようにその穿引きに沿って切断する。その
結果、側面に半円状の凹部が形成される。Therefore, as shown in FIG. 4, lines on both sides of the width are drawn on a printed circuit board of an appropriate size,
As shown by an arrow C in FIG. 3A, through holes 5 are formed at intervals of the pads 1a along the line drawing, and cut along the line as shown in FIG. As a result, a semicircular recess is formed on the side surface.

【００１７】同様の方法で、線引き方向に長径がある長
穴を穿設し、その穿引きに沿って切断すれば、側面に半
長円状の凹部が形成される。If a long hole having a long diameter is bored in the wire drawing direction in the same manner and cutting is performed along the hole, a semi-elliptical recess is formed on the side surface.

【００１８】半田付けの信頼性から言えば半長円状の凹
部が優れていると考えられる。半田付け面積が半円状凹
部よりも増えるからである。From the reliability of soldering, it is considered that the semi-elliptical recess is excellent. This is because the soldering area is larger than that of the semicircular recess.

【００１９】[0019]

【発明の効果】以上説明したように、本発明の表面実装
用リードピッチ変換基板によれば、表面にパットを設け
ＥＩＡＪパッケージ規格に基づくデュアルインラインパ
ッケージＳＯＰＩＣを半田付け実装できるようにし、ま
た側面に凹部を形成しＪＥＤＥＣパッケージ規格に基づ
くデュアルインラインパッケージＳＯＰＩＣを実装する
プリント基板に設定してあるパットに半田付けできるよ
うにしてあるので、繁雑な実装作業を要さずに簡単にリ
ードピッチの変換が行え、幅方向のリード間ピッチが大
きい方のＳＯＰＩＣ用に設定してあるプリント基板に幅
方向のリード間ピッチが小さい方のＳＯＰＩＣを実装ス
ペースの問題を生じさせずに支障なく実装できる効果が
ある。As described above, according to the lead pitch conversion substrate for surface mounting of the present invention, the pad is provided on the surface so that the dual in-line package SOPIC based on the EIAJ package standard can be mounted by soldering, and the side surface is provided. The lead pitch can be easily converted without the need for complicated mounting work because the recess is formed and it can be soldered to the pad that is set on the printed circuit board on which the dual in-line package SOPIC based on the JEDEC package standard is mounted. There is an effect that the SOPIC having a smaller lead pitch in the width direction can be mounted on the printed circuit board set for the SOPIC having a larger lead pitch in the width direction without causing a problem of the mounting space. .

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例に係る表面実装用リードピッ
チ変換基板を実装するＳＯＰＩＣと半田付けするパット
との関係で示す概略斜視図である。FIG. 1 is a schematic perspective view showing a relationship between a SOPIC mounting a surface mounting lead pitch conversion substrate according to an embodiment of the present invention and a soldering pad.

【図２】実装状態を示す概略斜視図である。FIG. 2 is a schematic perspective view showing a mounted state.

【図３】図２中のＡ−Ａ線矢視側面断面図である。FIG. 3 is a side sectional view taken along the line AA in FIG.

【図４】幅の設定及び凹部の形成方法の説明図であり、
（ａ）は線引きに沿ってスルーホールを穿設する工程
図、（ｂ）は穿引きに沿って切断する工程図である。FIG. 4 is an explanatory diagram of a method of setting a width and forming a recess,
(A) is a process drawing of forming a through hole along a line drawing, and (b) is a process drawing of cutting along a drawing.

【図５】ＳＯＰＩＣの一般的な実装状態の説明図であ
る。FIG. 5 is an explanatory diagram of a general mounting state of a SOPIC.

【図６】幅方向のリード間ピッチが異なる場合の実装の
説明図である。FIG. 6 is an explanatory diagram of mounting when the pitch between leads in the width direction is different.

【図７】幅方向のリード間ピッチが異なる場合の従来の
実装方法の説明図である。FIG. 7 is an explanatory diagram of a conventional mounting method when the pitch between leads in the width direction is different.

【符号の説明】[Explanation of symbols]

１ 表面実装用リードピッチ変換基板 １ａ パット １ｂ 凹部 ２ ＳＯＰＩＣ ３ パット ４ プリント基板 ５ スルーホール 1 Surface Mount Lead Pitch Conversion Board 1a Pad 1b Recess 2 SOPIC 3 Pad 4 Printed Circuit Board 5 Through Hole

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 表面周形状がＥＩＡＪパッケージ規格に
基づくデュアルインラインパッケージＳＯＰＩＣの周形
状よりも若干大き目の相似形であって幅がＪＥＤＥＣパ
ッケージ規格に基づくデュアルインラインパッケージＳ
ＯＰＩＣの幅方向のリード間ピッチと少なくともほぼ等
しい大きさに形成されてなり； その表面にＥＩＡＪパ
ッケージ規格に基づくＳＯＰＩＣ用のパットが設定さ
れ； その短手方向両側の側面の前記各パットに対応し
た位置に半円状または半長円状の凹部がそれぞれ形成さ
れ； 前記側面の凹部に形成される導体箔と表面の対応
するパットとを連結してなる； ことを特徴とする表面
実装用リードピッチ変換基板。1. A dual in-line package S whose surface peripheral shape is a similar shape slightly larger than the peripheral shape of a dual in-line package SOPIC based on the EIAJ package standard and whose width is based on the JEDEC package standard.
It is formed to have a size at least approximately equal to the pitch between leads in the width direction of the OPIC; a SOPIC pad based on the EIAJ package standard is set on its surface; corresponding to each of the pads on both sides in the lateral direction A semi-circular or semi-elliptical concave portion is formed at each position; and a conductor foil formed in the concave portion on the side surface and a corresponding pad on the surface are connected to each other; Conversion board.
JP5028607A 1993-01-25 1993-01-25 Lead pitch changing board for surface mounting Pending JPH06224537A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5028607A JPH06224537A (en) 1993-01-25 1993-01-25 Lead pitch changing board for surface mounting

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5028607A JPH06224537A (en) 1993-01-25 1993-01-25 Lead pitch changing board for surface mounting

Publications (1)

Publication Number Publication Date
JPH06224537A true JPH06224537A (en) 1994-08-12

Family

ID=12253266

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5028607A Pending JPH06224537A (en) 1993-01-25 1993-01-25 Lead pitch changing board for surface mounting

Country Status (1)

Country Link
JP (1) JPH06224537A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09298351A (en) * 1996-05-01 1997-11-18 Nec Corp Circuit pattern converting subprinted board
FR2772998A1 (en) * 1997-12-23 1999-06-25 Aerospatiale DEVICE AND METHOD FOR INTERCONNECTING BETWEEN TWO ELECTRONIC DEVICES
WO2002069680A2 (en) * 2001-01-17 2002-09-06 Honeywell International Inc. Adapter for plastic-leaded chip carrier (plcc) and other surface mount technology (smt) chip carriers

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09298351A (en) * 1996-05-01 1997-11-18 Nec Corp Circuit pattern converting subprinted board
FR2772998A1 (en) * 1997-12-23 1999-06-25 Aerospatiale DEVICE AND METHOD FOR INTERCONNECTING BETWEEN TWO ELECTRONIC DEVICES
EP0926935A1 (en) * 1997-12-23 1999-06-30 Aerospatiale Societe Nationale Industrielle Device and process for interconnecting between two electronic devices
WO2002069680A2 (en) * 2001-01-17 2002-09-06 Honeywell International Inc. Adapter for plastic-leaded chip carrier (plcc) and other surface mount technology (smt) chip carriers
WO2002069680A3 (en) * 2001-01-17 2002-11-21 Honeywell Int Inc Adapter for plastic-leaded chip carrier (plcc) and other surface mount technology (smt) chip carriers
US6862190B2 (en) 2001-01-17 2005-03-01 Honeywell International, Inc. Adapter for plastic-leaded chip carrier (PLCC) and other surface mount technology (SMT) chip carriers

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