JPH09298351A - Circuit pattern converting subprinted board - Google Patents

Circuit pattern converting subprinted board

Info

Publication number
JPH09298351A
JPH09298351A JP8110798A JP11079896A JPH09298351A JP H09298351 A JPH09298351 A JP H09298351A JP 8110798 A JP8110798 A JP 8110798A JP 11079896 A JP11079896 A JP 11079896A JP H09298351 A JPH09298351 A JP H09298351A
Authority
JP
Japan
Prior art keywords
circuit board
board
connection
sub
electronic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8110798A
Other languages
Japanese (ja)
Inventor
Toshiyuki Tada
俊幸 多田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP8110798A priority Critical patent/JPH09298351A/en
Publication of JPH09298351A publication Critical patent/JPH09298351A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/141One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/225Correcting or repairing of printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Landscapes

  • Combinations Of Printed Boards (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a circuit pattern converting subprinted board wherein mismatching of a circuit wiring which is generated relative to the connection between an electronic circuit board and a mounted IC is easily corrected, and correction to a surface mount type flat package IC having different terminal arrangement is also easily enabled. SOLUTION: A subprinted board 11 is used in order to mediate electrical connection between connection pads 13a of an electronic circuit board 13 for surface mounting and connection leads 12a of a flat package IC 12 for surface mounting which is mounted on the board. A circuit pattern which connects the pads 13a and the leads 12a in a specified relation, in order to convert an initial circuit pattern built in the electronic circuit board 13, is formed in the subprinted board 11.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は電子回路基板におけ
る回路の補正技術に関し、特にサーフェィスマウントデ
バイス(以下SMDという)形状のフラットパッケージ
IC(以下FICという)の回路補正用サブプリント基
板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit correction technique for an electronic circuit board, and more particularly to a circuit correction sub-printed circuit board of a surface mount device (hereinafter referred to as SMD) flat package IC (hereinafter referred to as FIC).

【0002】[0002]

【従来の技術】従来用いられていたこの種の電子回路基
板とその電子回路基板に実装される半導体装置との接続
に関連して発生する回路配線の不整合を補正する方法と
しては、第1には再設計を行なって補正すべき電子回路
基板を製作し直す方法があり、第2には電子回路基板上
もしくは内部に存在する補正すべき回路の一部又は全体
の除去加工を機械的方法等で行なって電気的接続を切断
後、ストラップワイヤ等を使用してFICの電極と正常
な回路間とをはんだ付けにより接続させ正しい回路に補
正して再生させる方法等がある。
2. Description of the Related Art The first method is a method for correcting the mismatch of circuit wiring that occurs in connection with the connection between this type of electronic circuit board and the semiconductor device mounted on the electronic circuit board which has been conventionally used. There is a method of redesigning and remanufacturing an electronic circuit board to be corrected. Secondly, a mechanical method is used for removing a part or the whole of a circuit to be corrected existing on or inside the electronic circuit board. After disconnecting the electrical connection by means such as the above, the electrodes of the FIC and the normal circuit are connected by soldering using a strap wire or the like to correct the circuit and reproduce it.

【0003】図4は従来例の機械的除去により補正を行
なった電子回路基板とFICとを示す模式的斜視図であ
り、符号42はFICを、42aはリード(接続端
子)、43は補正すべき電子回路基板、43aはパッ
ド、43bは回路、43cは機械的除去後の回路の間
隙、44aはストラップワイヤである。
FIG. 4 is a schematic perspective view showing an FIC and an electronic circuit board corrected by mechanical removal in a conventional example. Reference numeral 42 is an FIC, 42a is a lead (connection terminal), and 43 is a correction. Electronic circuit board, 43a is a pad, 43b is a circuit, 43c is a circuit gap after mechanical removal, and 44a is a strap wire.

【0004】電子回路基板43の回路43aと実装され
るFIC42のリード42aとの回路上の不整合を補正
するために、電子回路基板43の回路43bの一部43
cが機械的方法等で除去され、FIC43は裏返しに電
子回路基板43に固定され、電子回路基板43の表面を
離れたリード42aから整合する電子回路基板43のパ
ッド43aや部品の端子にストラップワイヤ44で配線
されている。この他にFIC42を裏返さないでパッド
43aとの電気的接続が切断されたリード42aを上側
に折り曲げてストラップワイヤ44等で所定のパッド4
3aに接続配線後、接着剤により改造部を固定する方法
もある。
In order to correct the circuit mismatch between the circuit 43a of the electronic circuit board 43 and the lead 42a of the mounted FIC 42, a part 43 of the circuit 43b of the electronic circuit board 43.
c is removed by a mechanical method or the like, the FIC 43 is turned upside down and fixed to the electronic circuit board 43, and the pads 43a of the electronic circuit board 43 aligned from the leads 42a separated from the surface of the electronic circuit board 43 and the strap wire to the terminal of the component. Wired at 44. In addition to this, the FIC 42 is not turned upside down, the lead 42a whose electrical connection to the pad 43a is cut off is bent upward, and a predetermined pad 4 is formed by a strap wire 44 or the like.
There is also a method of fixing the modified portion with an adhesive after connection wiring to 3a.

【0005】[0005]

【発明が解決しようとする課題】上述の従来例の第1の
電子回路基板の再設計を行なう方法では、電子回路基板
の回路補正のための再設計期間と再製作期間を必要と
し、また再製作費用が掛かるために製品コストが増大す
るという問題点がある。
SUMMARY OF THE INVENTION The above-mentioned first method for redesigning an electronic circuit board of the prior art requires a redesign period and a remanufacturing period for circuit correction of the electronic circuit board, and There is a problem in that the product cost increases because of the manufacturing cost.

【0006】また、第2の機械的除去によって電気的接
続を切断し、新たにストラップワイヤで所定のパッドと
接続配線を行なう方法では、上述の作業は作業者の手作
業となり、作業者のスキルに依存する度合が高く、切断
の不確実性や再接続の加熱による電子回路基板への影響
等品質の低下を生ずるという問題点がある。
Further, in the method of disconnecting the electrical connection by the second mechanical removal and newly connecting a predetermined pad and connection wiring with a strap wire, the above-mentioned work becomes a manual work of the worker, and the skill of the worker is required. However, there is a problem that the quality is deteriorated due to the uncertainties of disconnection and the influence of heating of reconnection on the electronic circuit board.

【0007】本発明の目的は、電子回路基板と実装する
ICとの接続に関連して発生する回路配線の不整合を容
易に補正し、異なった端子配置のSMDに対する補正も
容易に行なえる回路パターン変換サブプリント基板を提
供することにある。
It is an object of the present invention to easily correct a mismatch of circuit wiring caused by connection between an electronic circuit board and an IC to be mounted, and to easily correct SMD having different terminal arrangements. It is to provide a pattern conversion sub-printed circuit board.

【0008】[0008]

【課題を解決するための手段】本発明の回路パターン変
換サブプリント基板は、表面実装用電子基板の接続パッ
ドと該基板に実装される表面実装用フラットパッケージ
ICの接続端子との電気的接続を仲介するサブプリント
基板であって、表面実装用電子基板に組み込まれている
当初の回路パターンを変換するために、接続パッドと接
続端子とを所定の関係で接続する回路パターンをサブプ
リント基板の内部に備えている。
A circuit pattern conversion sub-printed circuit board of the present invention provides electrical connection between connection pads of a surface mounting electronic board and connection terminals of a surface mounting flat package IC mounted on the board. An intermediary sub-printed circuit board, in which a circuit pattern for connecting the connection pad and the connection terminal in a predetermined relationship is converted inside the sub-printed circuit board in order to convert the initial circuit pattern incorporated in the surface mounting electronic board. Be prepared for.

【0009】また、サブプリント基板の表面実装用フラ
ットパッケージICとの当接面には該ICの接続端子の
それぞれと当接するランドを有し、反対面には表面実装
用電子基板の接続パッドのそれぞれと当接するランドを
有し、ランド間には接続すべき接続端子と接続パッドと
を接続するためのの配線とスルーホールを有することが
好ましい。
[0009] Further, the contact surface of the sub-printed board with the surface mounting flat package IC has lands for contacting each of the connection terminals of the IC, and the opposite surface of the connection pad of the surface mounting electronic board. It is preferable to have lands that come into contact with each other, and to have a wiring and a through hole for connecting a connection terminal to be connected and a connection pad between the lands.

【0010】さらに、サブプリント基板の側面には、接
続パッドと当接するランドと連接する半割形状のスルー
ホールが設けられ、位置的に対応する接続端子と接続パ
ッドとが接続すべき関係にあるときには、対応するIC
に当接するパッドと、同一位置にある半割形状のスルー
ホールとが接続されていてもよい。
Furthermore, on the side surface of the sub-printed circuit board, a through hole having a half-divided shape is provided so as to be connected to the land contacting the connection pad, and the connection terminal and the connection pad corresponding to each other in position are to be connected. Sometimes the corresponding IC
The pad that abuts on and the through hole having a half-divided shape at the same position may be connected.

【0011】本発明のサブプリント基板では、実装され
たFICのリードと接続するランドと、電子回路基板の
パッドと接続するランドとをサブプリント基板内で任意
の関係で接続できるので、所望の接続回路を有するサブ
プリント基板を電子回路基板とFICとの間に挟んでリ
ードやパッドを接続ランドにはんだ付けすることによ
り、不整合の電子回路基板の回路切断やFICリードと
パッド間のストラップワイヤによる回路接続を行なうこ
となく電気回路の補正が可能となる。
In the sub-printed circuit board of the present invention, the lands connected to the leads of the mounted FIC and the lands connected to the pads of the electronic circuit board can be connected in any desired relationship within the sub-printed circuit board. By sandwiching the sub-printed circuit board having the circuit between the electronic circuit board and the FIC and soldering the leads and pads to the connection lands, the circuit of the mismatched electronic circuit board is cut or the strap wire between the FIC lead and the pad is used. The electric circuit can be corrected without making circuit connection.

【0012】実装されるFICのリードと接続するラン
ドと、電子回路基板のパッドと接続するランドとを、実
装されるFICのリードと電子回路基板のパッドとの位
置に整合させて設けることにより容易に組立て(はんだ
付け)ができる。
The land for connecting to the lead of the mounted FIC and the land for connecting to the pad of the electronic circuit board can be easily provided by aligning the lead of the mounted FIC and the pad of the electronic circuit board. Can be assembled (soldered).

【0013】[0013]

【発明の実施の形態】次に、本発明の実施の形態につい
て図面を参照して説明する。図1は本発明の実施の形態
のサブプリント基板と、FICと、電子回路基板との関
係を示す模式的斜視図であり、図2はサブプリント基板
の構造を示す模式的部分斜視図であり、図3はサブプリ
ント基板の接続ランド部の詳細を示す模式的部分斜視図
である。図中符号11はサブプリント基板、11aはF
ICリード接続用ランド、11bは電子回路基板パッド
接続用ランド、11cは電子回路基板パッド接続用ラン
ドのスルーホール部、11dは配線、11eはスルーホ
ール、12はFIC、12aはリード、12bはFIC
の1番ピンを示すマーク、13は電子回路基板、13a
はパッド、13bはパッドの1番ピンを示すマークであ
る。
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic perspective view showing the relationship among a sub-printed circuit board, an FIC, and an electronic circuit board according to an embodiment of the present invention, and FIG. 2 is a schematic partial perspective view showing the structure of the sub-printed circuit board. 3 is a schematic partial perspective view showing details of the connection land portion of the sub-printed circuit board. In the figure, reference numeral 11 is a sub-printed circuit board, and 11a is F.
IC lead connection land, 11b electronic circuit board pad connection land, 11c through hole portion of electronic circuit board pad connection land, 11d wiring, 11e through hole, 12 FIC, 12a lead, 12b FIC
Mark indicating the 1st pin, 13 is an electronic circuit board, 13a
Is a pad, and 13b is a mark indicating the first pin of the pad.

【0014】サブプリント基板11には、図2に示され
るように、片面にFICリード接続用ランド11aがF
IC12のリード12aと直接はんだ接続可能な位置に
配接されており、反対面には電子回路基板パッド接続用
ランド11bが電子回路基板13のパッド13aと直接
はんだ接続可能な位置に配接されており、図3に示すご
とく電子回路基板パッド接続用ランド11bはサブプリ
ント基板11の側面に設けられた半割り形状のスルーホ
ール部11cと連接している。
As shown in FIG. 2, the sub-printed circuit board 11 has an FIC lead connection land 11a on one side.
The lead 12a of the IC 12 is disposed at a position where it can be directly soldered to the lead 12a, and the electronic circuit board pad connecting land 11b is disposed at a position where it can be directly soldered to the pad 13a of the electronic circuit substrate 13 on the opposite surface. As shown in FIG. 3, the electronic circuit board pad connecting land 11b is connected to the through hole portion 11c of the half-divided shape provided on the side surface of the sub print board 11.

【0015】FICリード接続用ランド11aと電子回
路基板パッド接続用ランド11bとは、同位置のFIC
リード接続用ランド11aと電子回路基板パッド接続用
ランド11bとが整合する場合には側面の半割り形状の
スルーホール部11cを経由し、不整合の場合には配線
11d及びサブプリント基板内のスルーホール11eを
経由して整合する相手と相互に接続されることにより、
正しい回路パターンに変換される。
The FIC lead connecting land 11a and the electronic circuit board pad connecting land 11b are at the same position of the FIC.
When the lead connection lands 11a and the electronic circuit board pad connection lands 11b are aligned with each other, they are routed through the side half-hole through holes 11c, and when they are not aligned, the wiring 11d and the through holes in the sub-printed board are formed. By mutually connecting with the matching partner via the hole 11e,
Converted to the correct circuit pattern.

【0016】例えば図1において、電子回路基板13の
1番ピンを示すマーク13bはパッド列の端部に示され
ている。この電子回路基板13に、組立図面の指示によ
り1番ピンを示すマークがパッド列の中央にあるFIC
12が与えられたものと仮定する。この電子回路基板1
3の回路は、このFIC12が指示された図面とは異な
るために、このまま直接接続したのでは組立後も電子回
路は動作しない。
For example, in FIG. 1, the mark 13b indicating the 1st pin of the electronic circuit board 13 is shown at the end of the pad row. On this electronic circuit board 13, a mark indicating the 1st pin is located in the center of the pad row according to the instruction of the assembly drawing.
Suppose 12 is given. This electronic circuit board 1
Since the circuit of No. 3 is different from the drawing in which the FIC 12 is indicated, if it is directly connected as it is, the electronic circuit does not operate even after assembly.

【0017】そこで、整合するFICリード接続用ラン
ド11aと電子回路基板パッド接続用ランド11bとを
内部の配線11dとスルーホール11c、11eで接続
し、回路パターンを変換したサブプリント基板11を電
子回路基板13とFIC12との間に挿入してはんだ付
けによって接続することにより、正常な電子回路が得ら
れる。
Therefore, the matching FIC lead connecting lands 11a and electronic circuit board pad connecting lands 11b are connected to the internal wiring 11d and through holes 11c and 11e, and the sub-printed circuit board 11 having the converted circuit pattern is converted into an electronic circuit. A normal electronic circuit can be obtained by inserting the board 13 and the FIC 12 and connecting them by soldering.

【0018】このように本発明のサブプリント基板はL
CC(Leadless ChipCarrier リ
ードのない小型高密度用パッケージ)形状となっている
ので従来のはんだ付け基準がそのまま利用できるなど、
他の電子部品と同様な外観検査性やはんだ付け性を有し
ている。
Thus, the sub-printed circuit board of the present invention is L
Since it has a CC (Leadless ChipCarrier, small size and high density package without leads), the conventional soldering standard can be used as it is.
It has the same visual inspection and solderability as other electronic components.

【0019】[0019]

【発明の効果】以上説明したように本発明は、回路変換
機能を有するサブプリント基板を、回路パターンの不整
合なFICと電子回路基板との間に挿入接続することに
より、容易に、かつ安定した回路の補正ができ、機械的
除去加工のような人手による作業が不要になるという効
果がある。
As described above, according to the present invention, a sub-printed circuit board having a circuit conversion function is inserted and connected between an FIC having an inconsistent circuit pattern and an electronic circuit board, thereby easily and stably. The effect is that the circuit can be corrected, and manual work such as mechanical removal processing becomes unnecessary.

【0020】また、本発明のサブプリント基板は、FI
Cと類似した大きさであり、回路の接続位置も整合させ
ることができるので、電子回路基板を変更せずに使用で
き、電子回路基板の再製作が必要なく、設計変更費用が
節減でき、製品の納期が短縮できるという効果がある。
Further, the sub-printed circuit board of the present invention is FI
Since the size is similar to C and the connection position of the circuit can be matched, it can be used without changing the electronic circuit board, there is no need to remanufacture the electronic circuit board, the design change cost can be reduced, and the product The effect is that the delivery time of can be shortened.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施の形態のサブプリント基板と、F
ICと、電子回路基板との関係を示す模式的斜視図であ
る。
1 is a sub-printed circuit board according to an embodiment of the present invention;
It is a typical perspective view which shows the relationship between IC and an electronic circuit board.

【図2】サブプリント基板の構造を示す模式的部分斜視
図である。
FIG. 2 is a schematic partial perspective view showing the structure of a sub-printed circuit board.

【図3】サブプリント基板の接続ランド部の詳細を示す
模式的部分斜視図である。
FIG. 3 is a schematic partial perspective view showing details of a connection land portion of a sub-printed circuit board.

【図4】従来例の機械的除去により補正を行なった電子
回路基板とFICとを示す模式的斜視図である。
FIG. 4 is a schematic perspective view showing an FIC and an electronic circuit board corrected by mechanical removal in a conventional example.

【符号の説明】[Explanation of symbols]

11 サブプリント基板 11a FICリード接続用ランド 11b 電子回路基板パッド接続用ランド 11c 電子回路基板パッド接続用ランドのスルーホ
ール部 11d 配線 11e スルーホール 12、42 FIC 12a、42a リード 12b FICの1番ピンを示すマーク 13 電子回路基板 13a、43a パッド 13b パッドの1番ピンを示すマーク 43 補正すべき電子回路基板 43b 回路 43c 機械的除去後の回路の間隙 44a ストラップワイヤ
11 Sub Printed Circuit Board 11a FIC Lead Connection Land 11b Electronic Circuit Board Pad Connection Land 11c Electronic Circuit Board Pad Connection Land Through Hole 11d Wiring 11e Through Hole 12, 42 FIC 12a, 42a Lead 12b FIC Pin 1 Pin Mark 13 Electronic circuit board 13a, 43a Pad 13b Mark showing pin 1 of pad 43 Electronic circuit board to be corrected 43b Circuit 43c Circuit gap after mechanical removal 44a Strap wire

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 表面実装用電子基板の接続パッドと該基
板に実装される表面実装用フラットパッケージICの接
続端子との電気的接続を仲介するサブプリント基板であ
って、 前記表面実装用電子基板に組み込まれている当初の回路
パターンを変換するために、前記接続パッドと前記接続
端子とを所定の関係で接続する回路パターンを前記サブ
プリント基板の内部に備えたことを特徴とする回路パタ
ーン変換サブプリント基板。
1. A sub-printed board for mediating electrical connection between a connection pad of a surface mounting electronic substrate and a connection terminal of a surface mounting flat package IC mounted on the substrate, the surface mounting electronic substrate In order to convert the original circuit pattern incorporated in the sub-circuit board, a circuit pattern for connecting the connection pad and the connection terminal in a predetermined relationship is provided inside the sub-printed circuit board. Sub printed circuit board.
【請求項2】 前記サブプリント基板の前記表面実装用
フラットパッケージICとの当接面には該ICの接続端
子のそれぞれと当接するランドを有し、反対面には前記
表面実装用電子基板の前記接続パッドのそれぞれと当接
するランドを有し、前記ランド間には接続すべき前記接
続端子と前記接続パッドとを接続するためのの配線とス
ルーホールを有する請求項1に記載の回路パターン変換
サブプリント基板。
2. The surface of the sub-printed board, which comes into contact with the surface-mounting flat package IC, has lands that come into contact with the respective connection terminals of the IC, and the opposite surface has the land of the electronic board for surface-mounting. The circuit pattern conversion according to claim 1, further comprising a land that contacts each of the connection pads, and a wiring and a through hole for connecting the connection terminal to be connected to the connection pad and a land between the lands. Sub printed circuit board.
【請求項3】 前記サブプリント基板の側面には、接続
パッドと当接する前記ランドと連接する半割形状のスル
ーホールが設けられ、位置的に対応する前記接続端子と
前記接続パッドとが接続すべき関係にあるときには、対
応するICに当接する前記パッドと、同一位置にある半
割形状の前記スルーホールとが接続されている請求項2
に記載の回路パターン変換サブプリント基板。
3. A side surface of the sub-printed circuit board is provided with a through hole having a half-divided shape that is connected to the land contacting the connection pad, and the connection terminal and the connection pad corresponding to each other in position are connected to each other. 3. When in a power relationship, the pad that abuts a corresponding IC is connected to the half-hole shaped through hole located at the same position.
The circuit pattern conversion sub-printed circuit board according to.
JP8110798A 1996-05-01 1996-05-01 Circuit pattern converting subprinted board Pending JPH09298351A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8110798A JPH09298351A (en) 1996-05-01 1996-05-01 Circuit pattern converting subprinted board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8110798A JPH09298351A (en) 1996-05-01 1996-05-01 Circuit pattern converting subprinted board

Publications (1)

Publication Number Publication Date
JPH09298351A true JPH09298351A (en) 1997-11-18

Family

ID=14544921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8110798A Pending JPH09298351A (en) 1996-05-01 1996-05-01 Circuit pattern converting subprinted board

Country Status (1)

Country Link
JP (1) JPH09298351A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002069680A2 (en) * 2001-01-17 2002-09-06 Honeywell International Inc. Adapter for plastic-leaded chip carrier (plcc) and other surface mount technology (smt) chip carriers
JP2008505498A (en) * 2004-06-30 2008-02-21 ハネウェル・インターナショナル・インコーポレーテッド Interposer with micro-castellation
JP2015126093A (en) * 2013-12-26 2015-07-06 株式会社メガチップス Component mounting module and component mounting method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05327170A (en) * 1992-05-19 1993-12-10 Nippon Avionics Co Ltd Mounting of component and printed-wiring board for terminal connection conversion use
JPH06224537A (en) * 1993-01-25 1994-08-12 Kaijo Corp Lead pitch changing board for surface mounting
JPH0817867A (en) * 1994-07-04 1996-01-19 Sony Corp Wiring board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05327170A (en) * 1992-05-19 1993-12-10 Nippon Avionics Co Ltd Mounting of component and printed-wiring board for terminal connection conversion use
JPH06224537A (en) * 1993-01-25 1994-08-12 Kaijo Corp Lead pitch changing board for surface mounting
JPH0817867A (en) * 1994-07-04 1996-01-19 Sony Corp Wiring board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002069680A2 (en) * 2001-01-17 2002-09-06 Honeywell International Inc. Adapter for plastic-leaded chip carrier (plcc) and other surface mount technology (smt) chip carriers
WO2002069680A3 (en) * 2001-01-17 2002-11-21 Honeywell Int Inc Adapter for plastic-leaded chip carrier (plcc) and other surface mount technology (smt) chip carriers
US6862190B2 (en) 2001-01-17 2005-03-01 Honeywell International, Inc. Adapter for plastic-leaded chip carrier (PLCC) and other surface mount technology (SMT) chip carriers
JP2008505498A (en) * 2004-06-30 2008-02-21 ハネウェル・インターナショナル・インコーポレーテッド Interposer with micro-castellation
JP2015126093A (en) * 2013-12-26 2015-07-06 株式会社メガチップス Component mounting module and component mounting method

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