JP2565079B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2565079B2
JP2565079B2 JP5133759A JP13375993A JP2565079B2 JP 2565079 B2 JP2565079 B2 JP 2565079B2 JP 5133759 A JP5133759 A JP 5133759A JP 13375993 A JP13375993 A JP 13375993A JP 2565079 B2 JP2565079 B2 JP 2565079B2
Authority
JP
Japan
Prior art keywords
semiconductor device
package
piece portion
lead
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5133759A
Other languages
Japanese (ja)
Other versions
JPH06350004A (en
Inventor
尊浩 江口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP5133759A priority Critical patent/JP2565079B2/en
Publication of JPH06350004A publication Critical patent/JPH06350004A/en
Application granted granted Critical
Publication of JP2565079B2 publication Critical patent/JP2565079B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置に関し、特
に半導体素子を封止したパッケージから外部リードを導
出した縦型表面実装の半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a vertical surface mount semiconductor device in which external leads are led out from a package in which a semiconductor element is sealed.

【0002】[0002]

【従来の技術】従来の半導体装置、特に汎用メモリチッ
プを封止した半導体装置は、これら半導体装置を大量に
電子機器に使用する場合にあっては、プリント基板上の
単位体積当たりの実装密度を高めるため、縦型に実装す
る形態であった。一方、汎用メモリチップを封止した半
導体装置を大量に必要としない小型電子機器に使用する
場合にあっては、周辺の電子部品の実装高さをより低く
するため、横型に実装する形態が望ましく、同一のチッ
プを使用していながら半導体装置の実装形態に応じてこ
れらの半導体装置を選択する必要があった。
2. Description of the Related Art Conventional semiconductor devices, particularly semiconductor devices in which general-purpose memory chips are encapsulated, require a mounting density per unit volume on a printed circuit board when these semiconductor devices are used in large quantities in electronic equipment. In order to increase the height, it was mounted vertically. On the other hand, when the semiconductor device encapsulating a general-purpose memory chip is used in a small electronic device that does not require a large amount, horizontal mounting is desirable in order to lower the mounting height of peripheral electronic components. It is necessary to select these semiconductor devices according to the mounting form of the semiconductor devices while using the same chip.

【0003】この従来の半導体装置の技術に関するもの
としては、例えば、特開昭63−16650号公報、特
開平2−33958号公報、または特開昭62−104
148号公報等がある。図7は、従来の縦型実装半導体
装置の一例を示す構成図であり、樹脂封止部7の下面よ
り突出た外部リード8はL字型になっており、かつ外部
リード8a,8bは交互に向きを変えている。これによ
り狭ピッチ化を実現している。
Regarding the technology of this conventional semiconductor device, for example, JP-A-63-16650, JP-A-2-33958, or JP-A-62-104 is known.
No. 148, etc. FIG. 7 is a configuration diagram showing an example of a conventional vertical mounting semiconductor device. The external leads 8 protruding from the lower surface of the resin sealing portion 7 are L-shaped, and the external leads 8a and 8b are alternately arranged. Is turning to. This has achieved a narrow pitch.

【0004】図8および図9は従来の縦型実装半導体装
置の他の例を示す構成図であり、樹脂封止部7の下面よ
り突出た外部リード9を2度曲げることにより凹型を形
成している。外部リード9a,9bは交互に向きを変え
ることにより、図7に示す外部リード8a,8bと同
様、半導体装置の狭ピッチ化に役立てている。
FIG. 8 and FIG. 9 are configuration diagrams showing another example of a conventional vertical mounting semiconductor device, in which the external lead 9 protruding from the lower surface of the resin sealing portion 7 is bent twice to form a concave shape. ing. By alternately changing the directions of the external leads 9a and 9b, like the external leads 8a and 8b shown in FIG. 7, it is useful for narrowing the pitch of the semiconductor device.

【0005】図7,図8および図9に示すそれぞれの外
部リード8a,8b,9a及び9bはいずれも樹脂封止
部7の平面領域内で構成されている。
The external leads 8a, 8b, 9a and 9b shown in FIGS. 7, 8 and 9 are all formed within the plane area of the resin sealing portion 7.

【0006】図10および図11は従来の縦型実装半導
体装置のさらに他の例を示す構成図であり、樹脂封止部
10の側面より突出た外部リード11が3回曲げられる
ことにより凹型を形成し、かつ、この外部リード11は
樹脂封止部10を取り囲む様に構成されている。
10 and 11 are configuration diagrams showing still another example of the conventional vertical mounting semiconductor device, in which the external lead 11 protruding from the side surface of the resin sealing portion 10 is bent three times to form a concave shape. The external lead 11 is formed so as to surround the resin sealing portion 10.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、これら
従来技術では、樹脂封止部下面より突出たリードの方向
が交互になっているため横型に実装する時に、上向きに
存在するリードがあり、全リードを同一平面上に実装で
きない問題があった。また、横型に実装した場合、外部
リードが樹脂封止部の平面領域内にて構成されているた
め、プリント基板には樹脂封止部のみが接触し、外部リ
ードがプリント基板と接触できず、半田付が十分に行な
われないという問題もあった。
However, in these prior arts, since the directions of the leads projecting from the lower surface of the resin encapsulation portion are alternated, there is a lead existing upward when mounted in a horizontal type, and There was a problem that they could not be mounted on the same plane. Further, when mounted in a horizontal type, since the external leads are configured within the plane area of the resin sealing portion, only the resin sealing portion contacts the printed circuit board, and the external leads cannot contact the printed circuit board. There was also a problem that soldering was not performed sufficiently.

【0008】[0008]

【課題を解決するための手段】本発明の半導体装置は、
下面および前記下面に対向した上面と前記上面および前
記下面のそれぞれに垂直な4つの側面とを具備し、半導
体素子を封止したパッケージの前記下面からほぼ垂直に
突出し前記パッケージの下面と平行な底片部とその先端
を前記パッケージ下面と直角方向に曲げて形成する側
片部とを有する凹字形の第1の外部リードを備える縦型
表面実装の半導体装置において、前記パッケージの下面
と対向する前記上面からほぼ垂直に突出し前記上面と平
行な底片部とその先端を前記上面と直角方向に曲げて形
成する側片部とを有し前記側面の1つを基板面に対向さ
せて実装する横型表面実装の際に前記半導体装置を支持
第2の外部リードを備える構成である。
According to the present invention, there is provided a semiconductor device comprising:
Lower surface and upper surface facing the lower surface and the upper surface and front
Provided with four side surfaces perpendicular to each serial underside, a lower surface and perpendicular to the lower surface parallel to the bottom piece portion and the package its tip almost vertically projecting the package of the semiconductor device from the lower surface of the sealed package A vertical surface-mounting semiconductor device having a concave first external lead having a side piece portion formed by bending into a bottom piece, the bottom piece protruding substantially vertically from the upper surface facing the lower surface of the package and parallel to the upper surface. parts and opposite of one the substrate surface of the side possess a side piece portion of the tip is formed by bending the upper surface perpendicular to the direction
It was a structure comprising the second outer leads of the semiconductor device you support <br/> during horizontal surface mounting be implemented.

【0009】また、本発明の他の半導体装置は、下面お
よび前記下面に対向した上面と前記上面および前記下面
のそれぞれに垂直な4つの側面とを具備し、半導体素子
を封止したパッケージの前記下面からほぼ垂直に突出し
前記パッケージの下面と平行な底片部を有するL字形の
第1の外部リードを備える縦型表面実装の半導体装置に
おいて、前記パッケージの下面と対向する前記上面から
ほぼ垂直に突出し前記上面と平行な底片部とその先端を
前記上面と直角方向に曲げて形成する側片部とを有し前
記側面の1つを基板面に対向させて実装する横型表面実
装の際に前記半導体装置を支持する第2の外部リードを
備える構成である。
Further, another semiconductor device of the present invention has a bottom surface and
And an upper surface facing the lower surface, the upper surface and the lower surface
Longitudinally of each provided with four side surfaces perpendicular to, comprising a first external lead L-shaped having a lower surface parallel to the bottom piece portion of the substantially vertically projecting the package of the semiconductor device from the lower surface of the sealed package In a surface-mounting type semiconductor device, a bottom piece and a tip of the bottom piece, which project substantially vertically from the upper surface facing the lower surface of the package and are parallel to the upper surface , are provided.
Previous possess a side piece portion formed by bending the upper surface perpendicular to the direction
A horizontal surface mounting that mounts one of the side surfaces facing the board surface.
This is a configuration including a second external lead that supports the semiconductor device during mounting.

【0010】さらに、本発明の半導体装置は、前記パッ
ケージの下面からほぼ垂直に突出し前記パッケージの下
面と平行な底片部を有する第3の外部リードを備える構
成とすることもできる。
Further, the semiconductor device of the present invention may be configured to include a third external lead which has a bottom piece portion which projects substantially vertically from the lower surface of the package and is parallel to the lower surface of the package.

【0011】さらにまた、本発明の半導体装置は、前記
第1の外部リードの側片部と前記第2の外部リードの側
片部とが前記パッケージの下面と垂直な面と平行で同一
平面内にある構成とすることもできる。
Furthermore, in the semiconductor device of the present invention, the side piece portion of the first external lead and the side piece portion of the second external lead are parallel to a surface perpendicular to the lower surface of the package and are in the same plane. It is also possible to adopt the configuration in.

【0012】[0012]

【実施例】次に本発明について図面を参照して説明す
る。
The present invention will be described below with reference to the drawings.

【0013】図1は、本発明の第1の実施例の半導体装
置の斜視図である。
FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present invention.

【0014】図1を参照すると、この実施例の半導体装
置は、樹脂封止部1の下面より突出した信号リード3を
凹字形に形成し、信号リード3が突出した樹脂封止部1
の同一面より支持リード5を突出して形成し、かつ信号
リード3とは逆方向にL字形を形成する構成である。
Referring to FIG. 1, in the semiconductor device of this embodiment, the signal leads 3 protruding from the lower surface of the resin encapsulation portion 1 are formed in a concave shape, and the resin encapsulation portion 1 from which the signal leads 3 protrude.
The support lead 5 is formed so as to project from the same surface as the above, and an L-shape is formed in the opposite direction to the signal lead 3.

【0015】さらに、この実施例は樹脂封止部1の信号
リード3と対向する面から支持リード2を突出して凹字
形に形成する。支持リード2を凹字形に形成する方向は
信号リード3の凹字形に形成した方向と同一方向であ
る。
Further, in this embodiment, the support lead 2 is formed in a concave shape by protruding from the surface of the resin sealing portion 1 facing the signal lead 3. The direction in which the support lead 2 is formed in the concave shape is the same as the direction in which the support lead 2 is formed in the concave shape.

【0016】この実施例の半導体装置は、2本の支持リ
ード2を有し、この支持リード2の突出する位置は信号
リード3の突出する面の対向面の3等分する位置にあ
り、樹脂封止部1のバランスをくずさない様な構成を有
する。
The semiconductor device of this embodiment has two support leads 2, and the projecting positions of the support leads 2 are at three equally divided positions on the opposite surface of the projecting surface of the signal lead 3. It has a configuration that does not break the balance of the sealing portion 1.

【0017】この信号リード3と支持リード5により半
導体装置を支持し縦型に実装することができる。
The signal leads 3 and the support leads 5 can support the semiconductor device and mount it vertically.

【0018】図2はこの第1の実施例の半導体装置を横
方向に実装した時の構成例である。信号リード3と支持
リード2により半導体装置を水平に支持し、横方向に実
装することができる。この時、信号リード3にある信号
リード側面部4と支持リード2の先端面は、それぞれ同
一面にある。この実施例の半導体装置を横方向に実装す
る際は信号リード3は側面部4を形成する構成のため半
田付性も十分に確保される。
FIG. 2 shows an example of the structure when the semiconductor device of the first embodiment is laterally mounted. The semiconductor device can be horizontally supported by the signal leads 3 and the support leads 2 and can be laterally mounted. At this time, the signal lead side surface portion 4 of the signal lead 3 and the tip end surface of the support lead 2 are on the same plane. When the semiconductor device of this embodiment is mounted in the lateral direction, the signal lead 3 has the side surface portion 4 so that solderability is sufficiently ensured.

【0019】すなわち、本発明の半導体装置は使用する
用途によって縦方向にも横方向にも実装可能となる。
That is, the semiconductor device of the present invention can be mounted vertically or horizontally depending on the intended use.

【0020】次に、本発明の第2の実施例の半導体装置
について説明する。
Next, a semiconductor device according to the second embodiment of the present invention will be described.

【0021】図3は、本発明の第2の実施例の半導体装
置の斜視図である。
FIG. 3 is a perspective view of a semiconductor device according to the second embodiment of the present invention.

【0022】図3を参照すると、この実施例の半導体装
置は、1本の支持リード32を有し、この支持リード3
2の突出する位置は信号リード3の突出する面の対向面
の中央にあり、樹脂封止部1のバランスを保つような構
成を有する以外は、第1の実施例の半導体装置と同一の
構成であり、同じ構成要素には同一の参照符号が付して
ある。
Referring to FIG. 3, the semiconductor device of this embodiment has one support lead 32.
The projecting position of 2 is in the center of the opposing surface of the projecting surface of the signal lead 3 and has the same configuration as the semiconductor device of the first embodiment except that the configuration is such that the balance of the resin sealing portion 1 is maintained. The same reference numerals are attached to the same components.

【0023】図4はこの第2の実施例の半導体装置を横
方向に実装した時の構成例である。第1の実施例で述べ
た様に、この第2の実施例の半導体装置は、信号リード
3と支持リード32によりこの半導体装置を水平に支持
し、横方向に実装することができる。
FIG. 4 shows an example of the structure when the semiconductor device of the second embodiment is laterally mounted. As described in the first embodiment, the semiconductor device of the second embodiment can be mounted horizontally by horizontally supporting the semiconductor device by the signal lead 3 and the support lead 32.

【0024】この時、信号リード3にある信号側面部4
と支持リード32の先端面はそれぞれ同一面内にあるこ
とは言うまでもない。この実施例の半導体装置を横方向
に実装する際は、信号リード3は側面部4を形成する構
成であるため半田付性が十分に確保できるのも第1の実
施例と同様である。
At this time, the signal side surface portion 4 on the signal lead 3
It goes without saying that the tip surfaces of the support lead 32 and the support lead 32 are in the same plane. When the semiconductor device of this embodiment is mounted in the lateral direction, the signal lead 3 has the side surface 4 so that sufficient solderability can be ensured as in the first embodiment.

【0025】また、第1および第2の実施例の半導体装
置のそれぞれを横方向に実装する時樹脂封止部1より突
出した支持リード2および32のそれぞれを半田付で固
定することで信号リード3もその位置ずれを防止でき、
半田付が可能となる。
Further, when the semiconductor devices of the first and second embodiments are mounted in the lateral direction, the support leads 2 and 32 protruding from the resin sealing portion 1 are fixed by soldering so that the signal leads are formed. 3 can also prevent the displacement,
Soldering is possible.

【0026】次に、本発明の第3の実施例の半導体装置
を説明する。
Next, a semiconductor device according to the third embodiment of the present invention will be described.

【0027】図5は本発明の第3の実施例の半導体装置
の斜視図である。
FIG. 5 is a perspective view of a semiconductor device according to the third embodiment of the present invention.

【0028】図5を参照すると、この実施例の半導体装
置は樹脂封止部1の下面より突出した信号リード53を
L字形に形成し信号リード53が突出した樹脂封止部1
の同一面より支持リード55を信号リード53とは逆方
向にL字形を突出させて形成し、この信号リード53と
対向する面から2本の支持リード52を突出して凹字形
に形成する。この支持リード52を凹字形に形成する方
向は信号リード53のL字に形成した方向と同一方向
で、突出する位置は信号リード53の突出する面の対向
面の3等分する位置にあり、樹脂封止部1のバランスを
保つ様な構成を有する。
Referring to FIG. 5, in the semiconductor device of this embodiment, the signal lead 53 protruding from the lower surface of the resin sealing portion 1 is formed in an L shape, and the resin sealing portion 1 having the signal lead 53 protruding.
The support lead 55 is formed by protruding an L-shape in the direction opposite to the signal lead 53 from the same surface, and the two support leads 52 are formed in a concave shape by protruding from the surface facing the signal lead 53. The direction in which the support lead 52 is formed in the concave shape is the same as the direction in which the signal lead 53 is formed in the L shape, and the protruding position is at a position that is divided into three equal parts of the facing surface of the protruding surface of the signal lead 53. It has a structure for maintaining the balance of the resin sealing portion 1.

【0029】図6はこの第3の実施例の半導体装置を横
方向に実装した時の構成例である。
FIG. 6 shows an example of the structure when the semiconductor device of the third embodiment is laterally mounted.

【0030】信号リード53と支持リード52によりこ
の半導体装置を水平に支持し横方向に実装できるのは、
第1および第2の実施例の半導体装置と同様である。
This semiconductor device can be horizontally supported by the signal leads 53 and the support leads 52 and mounted laterally.
This is similar to the semiconductor devices of the first and second embodiments.

【0031】[0031]

【発明の効果】以上説明した様に本発明は、樹脂封止部
より突出た信号リード先端を凹字形またはL字形に曲げ
た信号リードと、反対方向のL字形に突出た支持リード
により縦方向の実装が、また、前述の信号リードと対向
する凹字形の支持リードにより横方向の実装が可能とな
る効果がある。さらに、横方向の実装時には支持リード
を半田付することにより、縦方向に実装する時と同等以
上にリード密着性を持つことが可能であるという効果も
有する。
As described above, according to the present invention, the signal lead projecting from the resin-sealed portion is bent in the concave or L-shape, and the supporting lead projecting in the L-direction in the opposite direction extends in the vertical direction. In addition, there is an effect that the concave-shaped support lead facing the above-mentioned signal lead enables lateral mounting. Furthermore, by soldering the support leads during lateral mounting, there is an effect that it is possible to have lead adhesion that is equal to or better than that during vertical mounting.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例の半導体装置の斜視図で
ある。
FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present invention.

【図2】図1に示す半導体装置の横方向の実装例を示す
構成図である。
FIG. 2 is a configuration diagram showing a lateral mounting example of the semiconductor device shown in FIG.

【図3】本発明の第2の実施例の半導体装置の斜視図で
ある。
FIG. 3 is a perspective view of a semiconductor device according to a second embodiment of the present invention.

【図4】図3に示す半導体装置の横方向の実装例を示す
構成図である。
FIG. 4 is a configuration diagram showing a lateral mounting example of the semiconductor device shown in FIG. 3;

【図5】本発明の第3の実施例の半導体装置の斜視図で
ある。
FIG. 5 is a perspective view of a semiconductor device according to a third embodiment of the present invention.

【図6】図5に示す半導体装置の横方向の実装例を示す
構成図である。
6 is a configuration diagram showing a lateral mounting example of the semiconductor device shown in FIG. 5;

【図7】従来例の半導体装置を示す図であり(a)はこ
の半導体装置の正面図であり(b)は側面図であり
(c)は斜視図である。
FIG. 7 is a view showing a semiconductor device of a conventional example, (a) is a front view of this semiconductor device, (b) is a side view, and (c) is a perspective view.

【図8】他の従来例の半導体装置の斜視図である。FIG. 8 is a perspective view of another conventional semiconductor device.

【図9】図8に示す他の従来例の半導体装置を示す図で
あり(a)はこの半導体装置の正面図であり(b)は側
面図である。
9A and 9B are diagrams showing another conventional semiconductor device shown in FIG. 8, FIG. 9A being a front view and FIG. 9B being a side view.

【図10】さらに他の従来例の半導体装置の斜視図であ
る。
FIG. 10 is a perspective view of still another conventional semiconductor device.

【図11】図10に示すさらに他の従来例の半導体装置
の実装時の側面図である。
11 is a side view of the semiconductor device of still another conventional example shown in FIG. 10 when the semiconductor device is mounted.

【符号の説明】 1,7,10 樹脂封止部 2,5,52,55 支持リード 3,8,8a,8b,9,9a,9b,11,32,5
3 信号リード 4 信号リード側面部 6,12 プリント基板 13 部品取付けランド 14 はんだ
[Sign Description] 1,7,10 resin sealing portion 2, 5, 52, 55 supporting leads 3,8,8a, 8b, 9,9a, 9b, 11,32, 5
3 Signal lead 4 Signal lead side surface 6,12 Printed circuit board 13 Component mounting land 14 Solder

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 下面および前記下面に対向した上面と前
記上面および前記下面のそれぞれに垂直な4つの側面と
を具備し、半導体素子を封止したパッケージの前記下面
からほぼ垂直に突出し前記パッケージの下面と平行な底
片部とその先端を前記パッケージ下面と直角方向に曲
げて形成する側片部とを有する凹字形の第1の外部リー
ドを備える縦型表面実装の半導体装置において、 前記パッケージの下面と対向する前記上面からほぼ垂直
に突出し前記上面と平行な底片部とその先端を前記上面
と直角方向に曲げて形成する側片部とを有し前記側面の
1つを基板面に対向させて実装する横型表面実装の際に
前記半導体装置を支持する第2の外部リードを備えるこ
とを特徴とする縦型表面実装の半導体装置。
1. A lower surface and an upper surface facing the lower surface and front.
Four side surfaces perpendicular to each of the upper surface and the lower surface
Comprising a has a substantially perpendicular to the bottom surface parallel to the bottom piece portion of projecting the package and the side piece portion of the tip is formed by bending the lower surface perpendicular direction of the package from the lower surface of the sealed package of a semiconductor device In a vertical surface-mounting semiconductor device having a concave-shaped first external lead, a bottom piece portion that protrudes substantially perpendicularly from the upper surface facing the lower surface of the package and is parallel to the upper surface, and a tip thereof is the upper surface. possess a side piece to form bent at a right angle direction of the side surface
For horizontal surface mounting, where one is mounted facing the board
A vertical surface-mount semiconductor device comprising a second external lead that supports the semiconductor device.
【請求項2】 下面および前記下面に対向した上面と前
記上面および前記下面のそれぞれに垂直な4つの側面と
を具備し、半導体素子を封止したパッケージの前記下面
からほぼ垂直に突出し前記パッケージの下面と平行な底
片部を有するL字形の第1の外部リードを備える縦型表
面実装の半導体装置において、 前記パッケージの下面と対向する前記上面からほぼ垂直
に突出し前記上面と平行な底片部とその先端を前記上面
と直角方向に曲げて形成する側片部とを有し前記側面の
1つを基板面に対向させて実装する横型表面実装の際に
前記半導体装置を支持する第2の外部リードを備えるこ
とを特徴とする縦型表面実装の半導体装置。
2. A lower surface and an upper surface facing the lower surface and front.
Four side surfaces perpendicular to each of the upper surface and the lower surface
Comprises a, in the semiconductor device of the vertical type surface mounting comprising a first external lead L-shaped having a lower surface parallel to the bottom piece portion of the substantially vertically projecting the package of the semiconductor device from the lower surface of the sealed package, the possess a side piece portion formed by bending substantially vertically projecting the surface parallel to the upper bottom piece portion and its distal end to said upper surface <br/> perpendicular direction from the upper surface to the lower surface facing the package of the side
For horizontal surface mounting, where one is mounted facing the board
A vertical surface-mount semiconductor device comprising a second external lead that supports the semiconductor device.
【請求項3】 前記パッケージの下面からほぼ垂直に突
出し前記パッケージの下面と平行な底片部を有する第3
の外部リードを備えることを特徴とする請求項1または
2記載の縦型表面実装の半導体装置。
3. A third piece having a bottom piece protruding substantially vertically from the lower surface of the package and parallel to the lower surface of the package.
The vertical surface mount semiconductor device according to claim 1 or 2, further comprising:
【請求項4】 前記第1の外部リードの側片部と前記第
2の外部リードの側片部とが前記パッケージの下面と垂
直な面と平行で同一平面内にあることを特徴とする請求
項1または3記載の縦型表面実装の半導体装置。
4. The side piece portion of the first external lead and the side piece portion of the second external lead are in the same plane parallel to a surface perpendicular to the lower surface of the package. Item 5. The vertical surface mount semiconductor device according to item 1 or 3.
JP5133759A 1993-06-04 1993-06-04 Semiconductor device Expired - Lifetime JP2565079B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5133759A JP2565079B2 (en) 1993-06-04 1993-06-04 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5133759A JP2565079B2 (en) 1993-06-04 1993-06-04 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH06350004A JPH06350004A (en) 1994-12-22
JP2565079B2 true JP2565079B2 (en) 1996-12-18

Family

ID=15112290

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5133759A Expired - Lifetime JP2565079B2 (en) 1993-06-04 1993-06-04 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2565079B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60257159A (en) * 1984-06-01 1985-12-18 Nec Corp Semiconductor device

Also Published As

Publication number Publication date
JPH06350004A (en) 1994-12-22

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